JP2003255903A - Display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display in which the total number of signal lines is never increased even when display resolution is made high. <P>SOLUTION: A liquid crystal display is provided with a plurality of signal lines S1 to Sm which are provided in lines in an X direction, a plurality of scanning lines G1 to Gn which are provided in lines in a Y direction, a plurality of display pixel parts 1 which are provided in lines in the vicinity of respective intersection points of the signal lines and the scanning lines, a signal line driving circuit 2 driving the signal lines S1 to Sm, and a scanning line driving circuit 3 driving the scanning lines G1 to Gm. Each display pixel part 1 has a pixel electrode 5, a writing TFT (thin film transistor) 6 which is connected to the pixel electrode 5 and a decoder part 7 which controls the gate voltage of the writing TFT6. Since data from a signal line are fetched by the decoder part 7 in accordance with the logic of the plurality of the scanning lines, the same signal line can be used in common by a plurality of display pixel electrodes 1. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type display device and is intended for a liquid crystal display device, an EL display device and the like.

[0002]

2. Description of the Related Art Recently, since the manufacturing technology of liquid crystal display devices has made remarkable progress, liquid crystal display devices are generally used as display devices for electronic equipment such as computers and mobile phones used in offices and homes. Has become.

Further, an organic EL display device has been actively developed because it has a simple structure and does not have an afterimage like a liquid crystal display device.

[0004]

The display resolution of these display devices tends to be gradually higher, but the higher the display resolution of the display device, the more the number of signal lines. Therefore, the distance between the wiring patterns is shortened, and the wiring patterns are easily affected by noise and crosstalk. In a display device in which a drive circuit is not integrally formed on a glass substrate, TCP or the like is used to mount the drive circuit, but as the number of signal lines increases, the pitch of the connection terminals of the TCP becomes narrower, and the drive circuit is mounted. Becomes difficult.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a display device in which the total number of connection terminals of the display panel does not increase even if the display resolution becomes high. . Another object of the present invention is to provide a display device in which the occurrence of display defects due to the effects of noise and crosstalk is suppressed.

[0006]

In order to solve the above-mentioned problems, the present invention provides a plurality of display pixel portions arranged in a matrix and provided with at least display elements, and a predetermined number of display pixels of 2 or more. A plurality of connection wirings arranged in common for each unit and a signal line driving circuit for supplying data to the display pixel unit via the connection wirings, each of the display pixel units corresponding to the data To a display element.

In the present invention, since the signal lines are distributed by the decoding circuit, a plurality of display pixel sections can share the same signal line, the number of signal lines can be reduced, and the mounting becomes easy.

Further, according to the present invention, a plurality of display pixel portions arranged in a matrix and provided with at least display elements,
A plurality of connection wirings that are arranged in common for each of the predetermined number of the display pixel sections, and a signal line drive circuit that supplies data to the display pixel section via the connection wirings, each of the display pixel sections Is a memory unit that stores data corresponding to pixel data, a display unit that displays according to the data stored in the memory unit, and a decoder unit that selects whether or not to store the data in the memory unit. , And a plurality of sub-pixel portions having the same, and data from the same connection wiring is supplied to the plurality of sub-pixel portions in the same display pixel portion.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, a display device according to the present invention will be specifically described with reference to the drawings. (First Embodiment) FIG. 1 shows a first embodiment of a display device according to the present invention.
FIG. 3 is a block diagram showing a schematic configuration of a liquid crystal display device which is the embodiment of FIG. The liquid crystal display device includes a display panel, a drive circuit board on which a drive circuit that drives the display panel is arranged, and a flexible wiring board that connects the display panel and the drive circuit board. The liquid crystal display panel of FIG.
A plurality of signal lines S1 to Sm arranged in the Y direction, a plurality of scanning lines G1 to Gn arranged in the Y direction, and a plurality of display pixel units arranged near each intersection of the signal lines and the scanning lines. 1, a signal line driving circuit 2 for driving the signal lines S1 to Sm, and a scanning line G1
Scanning line drive circuit 3 for driving Gn to Gn. The signal line S1 to Sn, the scanning lines G1 to Gn, and the display pixel section form a pixel array section 4.

A plurality of scanning lines are provided for each column of the display pixel portion arranged in the X direction. In FIG. 1, two scanning lines G (2i-
1) and G (2i) (i = 1, 2, ..., N) are provided.

Three display pixel sections (11 to 13), (14 to 16), (21 to 23), which are arranged adjacent to each other in the X direction,
Data from the same connection terminal is supplied to the signal lines connected to the three display pixel units 1 of each set by using (24 to 26), ..., ((m−2) to m) as a set. To be done. More specifically, each signal line is branched from the connection wiring CL corresponding to each of the plurality of display pixel units 1 of each set.

As described above, since the connection wiring CL connecting the signal line drive circuit 2 and the signal line of the pixel array section 4 is shared by the plurality of display pixel sections 1, the number of the connection wiring CL can be reduced. Therefore, even if the display resolution is increased, the connection wiring C
The number of L does not increase, the number of drivers 10 in the signal line driving circuit 2 can be reduced, and manufacturing cost and power consumption can be reduced.

In this embodiment, three display pixels of different colors (RGB) forming the same pixel are grouped. That is, the display pixels for red (R) color, green (G) color, and blue (B) color of the same pixel are in the same group.

FIG. 2 shows a display pixel section ij (i = 1, 2, ...
, N j = 1, 2, ... M) is a block diagram showing an internal configuration. As shown in the figure, each display pixel section ij is connected to the pixel electrode 5, a display element including a pixel electrode 5, a counter electrode arranged to face the pixel electrode, and a liquid crystal layer held between these electrodes. Auxiliary capacitor for holding a signal voltage, a writing TFT 6 connected to the pixel electrode 5, and a writing TF.
The decoder section 7 controls the gate voltage of T6.

The decoder section 7 includes two scanning lines G (2i-1),
It outputs a signal according to the logic of G (2i). For example, considering the same set of display pixel units 11 to 13 in FIG.
When the logic of the scanning lines G1 and G2 is (0, 1), the decoder unit 7 of the left display pixel unit 11 of the three display pixel units 11 to 13 in the same set outputs “1”. Then, the display of the display pixel portion 11 is performed.

The logic of the two scanning lines G1 and G2 is
When (1,0), the three display pixel units 11 to 13 in the same group
Of these, the decoder unit 7 of the central display pixel unit 12 is “1”.
Is output, and the display of the display pixel unit 12 is performed.

The logic of the two scanning lines G1 and G2 is
When (1,1), the three display pixel units 11 to 13 in the same group
Of these, the decoder unit 7 of the display pixel unit 13 on the right side is “1”.
Is output, and the display of the display pixel unit 13 is performed.

Further, when the logic of the two scanning lines is (0,0), all the display pixel sections 11 to 13 in the same group are unselected.

FIG. 3 is a display timing chart of FIG. As shown in the figure, three display periods D1, D2, D3 are included in one horizontal period.
Is provided. In the first display period D1, the logic of the scanning line of the corresponding row becomes (0, 1), and the display pixel units 11, 14, 17 on the left side in each set arranged in the X direction are displayed (for example, red display). ) Is performed, and in the next display period D2,
The logic of the scanning line of the corresponding row becomes (0, 1), the display pixel portions 12, 15, 18 in the center of each set are displayed (for example, green display), and in the last display period D3, The logic of the scanning line of the row to be set becomes (1, 1), and the display pixel portions 13 and 16 on the right side in each set are displayed (for example, blue display).

When the display of one horizontal period is completed, the line (i + 1 line) next to the line (i line) on which the display is performed is similarly divided into three display periods for display.

As described above, in this embodiment, the display pixel section
Since the decoder unit 7 is provided inside ij and the data from the signal line is taken in according to the logic of the plurality of scanning lines,
The same connection wiring CL can be shared by a plurality of display pixel portions.

For example, conventionally, in order to perform display in a display device period having n × m display pixels, the same number of connection wirings CL as the number of signal lines m was required, but according to this embodiment,
Since the connection wiring CL is shared by a plurality of signal lines, it is possible to reduce the number of wirings. For example, when the connection wiring CL is shared by three signal lines as described above, the number of connection wirings can be reduced to 1/3.

Therefore, since the internal structure of the signal line drive circuit 2 can be simplified, the manufacturing cost can be reduced, and the pitch between the wirings can be increased, so that the yield can be improved.

According to this embodiment, the horizontal period is set to 3
Since the data is divided and the data is written into the pixel, the time for writing the pixel is shorter than in the conventional case, but if a TFT having high mobility such as a polysilicon TFT is used, no particular problem occurs.

(Second Embodiment) The second embodiment is characterized in that a signal line is arranged for each of a plurality of display pixel portions forming a set.

FIG. 4 is a block diagram showing a schematic configuration of a liquid crystal display device which is a second embodiment of the display device according to the present invention. In the present embodiment, the signal line drive circuit is arranged on the drive circuit board, and the display panel and the drive circuit board are connected via the flexible wiring board. Each output of the signal line drive circuit is supplied to the corresponding signal line via the connection wiring CL.

The liquid crystal display device of FIG. 4 has three display pixel sections (11 to 13), (14 to 16), (21 to 23),
(24 to 26) and the like are set as a set, and one signal line is arranged for each set. The internal configuration of the display pixel unit 1 is similar to that of FIG. Three display pixel units (11 to 1) in the same group
3), (14-16), (21-23), (24-2)
6) and the like are connected to the corresponding signal lines.
For each display pixel unit 1, based on the output of the decoder unit 7,
Select whether to take in the data of the corresponding signal line.

As described above, since one signal line is shared by the plurality of display pixel portions 1, the pitch between adjacent signal lines can be widened. Further, when the signal line drive circuit is arranged on the external substrate, the number of connection terminals can be reduced, and mounting becomes easy. Since the number of drivers in the signal line drive circuit 2 can be reduced, the manufacturing cost can be reduced.

(Third Embodiment) In the third embodiment, the number of signal lines is reduced when the area gradation display is performed.

FIG. 5 is a block diagram showing a schematic structure of a liquid crystal display device in a third embodiment of the display device according to the present invention. In the present embodiment, the signal line drive circuit is arranged as an IC on the flexible wiring connecting the drive circuit board and the display panel, and each output of the signal line drive circuit is connected to the corresponding signal line via the connection wiring CL. Supplied.

Pixel array section 4 in the liquid crystal display device of FIG.
Has a plurality of display pixel portions that perform area gray scale display. Each display pixel portion has a plurality of (for example, three in FIG. 5) sub-pixel portions (31 to 33), (34 to 36), which have different areas,
(37-39), (41-43), (44-46),
(47 to 49) and the like. Each sub-pixel unit is a memory unit 5
1, a writing TFT 6, and a decoder section 7.

In FIG. 5, three sub-pixels (31 to 33) and (41 to 43) corresponding to red and three sub pixels corresponding to green are shown.
One sub-pixel (34-36), (44-46) and three sub-pixels (37-39), (47-49) corresponding to blue.
, And these nine sub-pixels form one pixel. That is, FIG. 5 shows the structure of two pixels.

Each decoder section 7 in the same display pixel section 1 has a plurality of scanning lines (for example, two scanning lines (G in FIG. 5).
1, G2) and (G3, G4) are connected. Each decoder unit 7 outputs a signal according to the logic of a plurality of scanning lines. The output of each decoder unit 7 corresponds to the corresponding write TFT.
6 is input to the gate terminal.

Each writing TFT in the same display pixel section 1
The drain terminals of 6 are connected to the same signal line,
When the write TFT 6 is turned on, the data of the signal line is written in the corresponding memory section 51.

For example, the two scanning lines G1 and G2 in FIG.
When (0,1), the sub-pixel portions 31, 34 and 37 are displayed, and when the scanning lines G1 and G2 are (1,0), the sub-pixel portion 32,
35 and 38 are displayed, and when the scanning line is (1,1), the sub-pixel portions 33, 36 and 399 are displayed.

FIG. 6 is a display timing chart of FIG. As shown in the figure, three display periods D1 and D are provided in one horizontal writing period.
2, D3 are provided, and in the first display period D1, the logic of the scanning line of the corresponding row is (0, 1), and the sub-pixel portions 31, 34 on the left side of the drawing in the display pixel portion arranged in the X direction are shown. , 37
In the next display period D2, the logic of the scanning line of the corresponding row becomes (1,0), and X is written.
Center sub-pixel portion 3 in the drawing in the display pixel portion arranged in the direction
Data is written to 2, 35, 38, etc., and in the next display period D3, the logic of the scanning line of the corresponding row is (1, 1).
Therefore, data writing is performed to the sub-pixel portions 33, 36, 39 and the like on the right side of the drawing in the display pixel portion arranged in the X direction. Thus, by performing writing from the sub-pixel portion having a small display area when performing the area gray scale display, a good display image can be obtained.

As described above, in the third embodiment, since the decoder section 7 is provided for each sub-pixel, the signal lines can be shared by a plurality of sub-pixels, and the number of signal lines can be reduced.

FIG. 7 is a block diagram showing a schematic structure of an area gradation type display device showing a modification of FIG. The display device of FIG. 7 has sub-pixel portions (31 to 33), (34 to 36),
(37-39), (41-43), (44-46),
The internal configuration such as (47 to 49) is different from that in FIG. The sub-pixel portion of FIG. 7 includes a memory portion 51 and a writing TFT 6
And an AND gate 52 and a decoder unit 7.

The decoder section 7 has two control signals (C1,
A signal corresponding to the logic of C2) is output. AND gate 5
2 calculates the logical product of the output of the decoder unit 7 and the scanning lines G1 to G3. The output of the AND gate 52 is the write TF
It is input to the gate terminal of T6. That is, the control signals C1 and C2 for time division are wired commonly to all pixels, and each sub-pixel is driven by a combination of this control signal and the scanning signal supplied to the scanning line.

For example, if the control signals C1 and C2 are (0,1), the column of sub-pixels 31, 34, 37, ... Is selected,
If the control signal is (1,0), sub-pixels 32, 35, 38, ...
.. is selected, and if the control signal is (1,1), the columns of sub-pixels 33, 36, 39, ... Are selected. And
The pixels controlled by the control signals C1 and C2 in the row selected by the scanning signal perform display.

Also in the case of the display device shown in FIG. 7, since the decoder section 7 is provided for each sub-pixel section, the signal lines can be shared by a plurality of sub-pixel sections, and the number of signal lines can be reduced.

Although FIG. 5 and FIG. 7 show the example in which the signal lines are arranged for each of the plurality of sub-pixel portions, the signal lines corresponding to the respective sub-pixels are provided and the signal lines are driven similarly to FIG. It may be connected to the common connection wiring CL at the connection portion with the circuit.

In each of the above-described embodiments, an example in which the display device of the present invention is applied to a liquid crystal display device has been described, but the present invention is also applicable to an EL (electro luminescence) display device. The overall structure of the EL display device is as shown in FIGS.
Is similar to the block diagram of FIG.

FIG. 8 is a block diagram showing the internal structure of the display pixel portion of the EL display device. The display pixel section of FIG. 8 includes a writing TFT 6, a decoder section 7 that controls the gate voltage of the writing TFT 6, a driving TFT 53, and an organic EL light emitting section 54. This organic EL light emitting portion functions as a display element.

The decoder section 7 selects whether or not to turn on the writing TFT 6 according to the logic of a plurality of scanning lines.
When the writing TFT 6 is turned on, the data of the signal line is supplied to the gate terminal of the driving TFT 53, and the organic EL light emitting unit 54 emits light according to the gate voltage.

[0046]

As described in detail above, according to the present invention, since a plurality of display elements share a connection wiring, the number of connection wirings can be reduced. Further, the signal line drive circuit can be easily mounted, and the configuration in the signal line drive circuit can be simplified, so that the cost of parts and the power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a liquid crystal display device which is a first embodiment of a display device according to the present invention.

FIG. 2 is a block diagram showing an internal configuration of a display pixel section.

FIG. 3 is a display timing chart of FIG.

FIG. 4 is a block diagram showing a schematic configuration of a liquid crystal display device which is a second embodiment of the display device according to the present invention.

FIG. 5 is a block diagram showing a schematic configuration of a liquid crystal display device in a third embodiment of the display device according to the present invention.

FIG. 6 is a display timing chart of FIG.

7 is a block diagram showing a schematic configuration of an area gradation type display device showing a modification of FIG.

FIG. 8 is a block diagram showing an internal configuration of a display pixel portion of an EL display device.

[Explanation of symbols]

1 Display pixel section 2 signal line drive circuit 3 Scan line drive circuit 4 pixel array section 5 pixel electrodes 6 writing TFT 7 Decoder section

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 623 G09G 3/20 623U 624 624B 680 680G F term (reference) 2H093 NA16 NC09 NC11 NC29 NC34 ND06 ND15 ND54 NE07 5C006 AA01 AA12 AA16 AA22 AC11 AF42 AF43 AF71 AF85 BB16 BC03 BC06 BC11 BC20 BC23 EB04 FA16 FA32.

Claims (8)

[Claims] 1. A plurality of display pixel portions arranged in a matrix, each display pixel portion including at least a display element, a plurality of connection wirings arranged in common for each of a predetermined number of two or more display pixel portions, and the connection wirings. A signal line driving circuit for supplying data to the display pixel section via a display circuit, each display pixel section having a decoding circuit for supplying the corresponding data to the display element. apparatus. 2. The display device according to claim 1, wherein the display device has a signal line connected to the connection wiring for each column of the display pixel portion. 3. The display device according to claim 1, wherein the display device has a signal line connected to the connection wiring for each column of the predetermined number of the display pixel portions. 4. The display circuit of the display circuit comprises: a plurality of display pixel units to which the data from the same connection wiring is supplied for each column of the display pixel units; The display device according to claim 1, wherein the pixel portions are selected one by one at the same time. 5. The display device according to claim 1, wherein each of the predetermined number of display pixel portions has a display pixel portion having a different display area. 6. A plurality of display pixel portions arranged in a matrix, each display pixel portion including at least a display element, a plurality of connection wirings arranged in common for each predetermined number of the display pixel portions, and the connection wirings interposed therebetween. A signal line driving circuit that supplies data to the display pixel unit, each of the display pixel units including a memory unit that stores data corresponding to pixel data, and a memory unit that stores data corresponding to the pixel data. A plurality of sub-pixel parts each having a display part for displaying and a decoder part for selecting whether or not to store data in the memory part, wherein the plurality of sub-pixel parts in the same display pixel part are provided. Is supplied with data from the same connection wiring. 7. The display according to claim 6, wherein a signal line branched from the same connection wiring is provided corresponding to each of the plurality of sub-pixel portions in the same display pixel portion. apparatus. 8. The connection wiring is provided for each of the display pixel portions, and each of the plurality of sub-pixel portions in the same display pixel portion is supplied with data from the corresponding connection wiring. The display device according to claim 6.