JP2017102472A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an active matrix type electrophoretic display configured to further reduce the number of writing times.SOLUTION: The display is characterized in that microcapsules each incorporating a plurality of charging particles are arranged on a plurality of pixel electrodes, and brightness and darkness are expressed by controlling the charging particles according to the potentials of the pixel electrodes. By performing an operation to rewrite an image signal to the pixel electrodes when an image to be displayed in the pixels is changed, the number of writing times is reduced.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor display device (hereinafter referred to as a display device), and in particular, an active matrix having a thin film transistor (hereinafter referred to as a TFT) manufactured on an insulator and using an electrophoretic element as a pixel. The present invention relates to a type display device.

At SID01 held in San Jose in June 2001, EINK introduced an electrophoretic display device and was in the spotlight. The electrophoretic display device announced by E INK Company uses electronic ink as a material and prints it to form a display device.

As shown in FIG. 9, the electronic ink forms a microcapsule 906 having a diameter of about 80 [μm], and encloses a transparent liquid, positively charged white fine particles 901, and negatively charged black fine particles 902 therein. doing. When an electric field is applied to the microcapsule 906, the white fine particles 901 and the black fine particles 902 move in opposite directions. As shown in FIG. 9, when a positive or negative electric field is applied between the counter electrode (transparent electrode) 903 and the pixel electrodes 904 and 905, white or black fine particles appear on the surface and display white or black. This electronic ink and counter electrode
The (transparent electrode) can be formed by a printing method, and an electrophoretic display device is obtained by printing electronic ink on a circuit board.

An electrophoretic display device using electronic ink has an advantage of lower power consumption than a liquid crystal display device. First, it has a reflectance of around 30% and has a reflectance several times that of a reflective liquid crystal. Reflective liquid crystal has low reflectivity, so it is advantageous in places with strong light such as under sunlight, but auxiliary lighting such as a front light is necessary in places with low light, but an electrophoretic display device using electronic ink The front light is unnecessary because of its high reflectivity. The front light requires several hundreds [mW] of power, but this power is unnecessary. Further, since the liquid crystal uses an organic material, if the direct current drive is continued, a deterioration phenomenon occurs. Therefore, AC inversion driving is necessary. However, when the inversion frequency is low, flicker is visually recognized and the user feels uncomfortable, so AC inversion driving is usually performed at 60 to 100 [Hz]. In the electrophoretic display device, it is not necessary to perform AC inversion driving as in the case of liquid crystal, so that it is not necessary to perform writing at 60 [Hz] every time. The above two points can reduce power consumption.

E INK has announced an electrophoretic display device using amorphous silicon (a-Si) TFTs in SID01 DIGEST p152-155.

A display device using an a-Si TFT includes external source signal line driver circuits 1101 and 1102 and a gate signal line driver circuit 1103 which are supplied in a package such as an IC around the pixel portion 1100. Each pixel includes a source signal line 1104 and a gate signal line 110.
5, a pixel TFT 1106, a pixel electrode 1107, a storage capacitor 1108, and the like.

FIG. 10 is a cross-sectional view of the pixel after the microcapsule 1004 and the counter electrode 1001 to be electronic ink are formed.
The operation of the fine particles in 04 is controlled to display white or black.

As described above, in the conventional electrophoretic display, since the drive circuit is mounted externally, there are problems in cost, frame size, reliability of terminal connection, and the like.

In addition, when an electrophoretic display is configured using an amorphous TFT substrate, writing corresponding to a time constant determined by the pixel holding capacity and the off-current of the pixel TFT is used to hold the potential applied to the pixel electrode. It is necessary to do. This is 60 [Hz] like flicker countermeasures
However, it is not necessary to perform writing in the above-mentioned manner, but refresh writing in a certain period is necessary. Therefore, in order to further reduce power consumption, there is a need for an electrophoretic display device that does not require writing unless the video is changed.

Therefore, an object of the present invention is to provide an active matrix electrophoretic display device which is an electrophoretic display device and has a smaller number of writing operations.

In the electrophoretic display device of the present invention, by incorporating a driver circuit, cost and power consumption and reliability of a terminal portion are improved, and by incorporating a highly retainable memory circuit in a pixel portion, the number of times of writing is increased. And a display device with low power consumption.

The configuration of the electrophoretic display device of the present invention will be described below. Note that in this specification, when circuit connection is described, one of a source region and a drain region of a TFT is referred to as an input electrode, and the remaining one is referred to as an output electrode. This is because it is difficult to clearly distinguish the source region and the drain region from the viewpoint of TFT cultivation.

In the present invention, a display device is characterized in that microcapsules containing a plurality of charged particles are arranged on a plurality of pixel electrodes, and brightness and darkness are displayed by controlling the charged particles by the potential of the pixel electrodes. The display device is characterized in that a drive circuit for driving a source signal line or a gate signal line is formed on the same substrate as the pixel.

In the present invention, a display device is characterized in that microcapsules containing a plurality of charged particles are arranged on a plurality of pixel electrodes, and brightness and darkness are displayed by controlling the charged particles by the potential of the pixel electrodes. Each of the pixel electrodes is connected to one memory circuit, and a potential of the pixel electrode is changed according to data stored in the memory circuit.

According to the present invention, in a display device in which a microcapsule containing a plurality of charged particles is disposed on a pixel electrode and brightness is displayed by controlling the charged particles by the potential of the pixel electrode, a plurality of pixels are formed on a substrate. The pixel electrode is composed of a plurality of sub-pixel electrodes, and each of the sub-pixel electrodes is connected to one memory circuit, and the potential of the sub-pixel electrode changes depending on data stored in the memory circuit A display device characterized by this is provided.

In the present invention, a source signal line driver circuit, a gate signal line driver circuit, and a pixel portion in which x × y pixels are arranged in a matrix form, an n-bit digital video signal is input to input video. In the display device that performs display, each of the x × y pixels includes n source signal lines, gate signal lines, and n sub-pixels, and the n sub-pixels each switch Transistor, a memory circuit, and a pixel electrode, the gate electrode of the switching transistor is electrically connected to the gate signal line, and the input electrode is different among the n source signal lines. The output electrode is electrically connected to the pixel electrode through the memory circuit, and the source signal line driver circuit includes a clock signal and a start pulse. Therefore, means for sequentially outputting sampling pulses, means for holding an n-bit digital video signal in accordance with the sampling pulses, means for transferring the held n-bit digital video signal, and the transferred n Means for outputting bit digital video signals in parallel to n × x source signal lines, and the gate signal line driving circuit sequentially outputs y gate signal lines in accordance with a clock signal and a start pulse. There is provided a display device comprising at least means for outputting a gate signal line selection pulse to be selected.

In the present invention, a source signal line driver circuit, a gate signal line driver circuit, and a pixel portion in which x × y pixels are arranged in a matrix form, an n-bit digital video signal is input to input video. In the display device that performs display, each of the x × y pixels includes a source signal line, n gate signal lines, and n subpixels, and each of the n subpixels is switched. A switching transistor, a gate electrode of the switching transistor is electrically connected to any one of the n gate signal lines, and an input electrode is The source signal line is electrically connected, the output electrode is electrically connected to the pixel electrode through the memory circuit, and the source signal line driver circuit includes a clock signal and a start pulse. Therefore, means for sequentially outputting sampling pulses, means for holding an n-bit digital video signal in accordance with the sampling pulses, means for transferring the held n-bit digital video signal, and the transferred n Means for sequentially selecting a bit digital video signal for each bit and outputting the digital signal to the source signal line, wherein the gate signal line driving circuit includes a clock signal, a start pulse, and a multiplex signal. , A display device comprising at least means for outputting a gate signal line selection pulse for sequentially selecting n × y gate signal lines is provided.

Note that an SRAM may be used for the memory circuit arranged in the pixel portion of the display device described above.

  In addition, according to the present invention, an electronic device using the display device described above is provided.

In the conventional electrophoretic display device, the driver circuit is externally attached, and there are problems in cost, reliability, and the like. In addition, since the pixel is configured by a combination of the storage capacitor and the switch TFT similar to the liquid crystal, periodic refresh is necessary, and power consumption is increased.

In the present invention, as described above, the pixel and the driver are integrally formed to improve cost and reliability, and by incorporating a memory circuit in the pixel, the number of writings can be reduced and power consumption can be reduced. It became possible.

1 is a diagram illustrating a configuration example of an electrophoretic display device of the present invention. FIG. 9 illustrates a configuration example of a source signal line driver circuit. FIG. 6 illustrates a configuration example of a pixel of the present invention. The figure which shows the structural example of the pixel corresponding to 3 bit gradation using this invention. The figure which shows the drive timing of the electrophoretic display device which has a pixel corresponding to 3 bit gradation display. FIG. 6 is a diagram illustrating a configuration example of a pixel using an SRAM as a memory circuit. FIG. 9 is a diagram showing a layout example on a substrate of a pixel using SRAM as a memory circuit. FIG. 9 is a cross-sectional view of a pixel using an SRAM as a memory circuit. The figure which shows the structure of an electrophoretic element. Sectional drawing of the pixel of the electrophoretic display apparatus using the conventional amorphous TFT. The figure which shows the display apparatus using the conventional amorphous TFT. Sectional drawing explaining the process of this invention. Sectional drawing explaining the process of this invention. The figure which shows the application apparatus of the display apparatus of this invention. The figure which shows the application apparatus of the display apparatus of this invention. FIG. 10 illustrates a configuration example of a gate signal line driver circuit. FIG. 9 illustrates a configuration example of a source signal line driver circuit. FIG. 9 illustrates a configuration example of a source signal line driver circuit. FIG. 10 illustrates a configuration example of a gate signal line driver circuit. FIG. 6 illustrates a configuration example of a pixel of the present invention. The figure which shows the drive timing of the electrophoretic display device which has a pixel corresponding to 3 bit gradation display.

[Embodiment 1]
The configuration of the electrophoretic display device of the present invention will be described below. The electrophoretic display device of the present invention includes a source signal line driver circuit and / or a gate signal line driver circuit over an insulating substrate, and includes a switching thin film transistor and a memory circuit in a pixel region.

FIG. 1 shows an embodiment of a display device of the present invention. The operation will be described below.

A pixel portion 106 is disposed in the center. A source signal line driver circuit 101 for controlling a signal input to the source signal line is disposed above the pixel portion.
The source signal line driver circuit 101 includes a first latch circuit 104, a second latch circuit 105, and the like. On the left and right sides of the pixel portion, gate signal line driving circuits 102 for controlling signals input to the gate signal lines are arranged. In FIG. 1, the gate signal line driving circuit 10
2 is disposed on both the left and right sides of the pixel portion, but may be disposed on one side. However, it is desirable to dispose them on both sides of the pixel portion from the viewpoint of driving efficiency and driving reliability.

The source signal line driver circuit 101 has a configuration as shown in FIG. The source signal line driver circuit shown as an example in FIG. 2 has x pixels in the horizontal direction, and is a source signal line driver circuit corresponding to a display device that inputs a 1-bit digital video signal and displays two gradations. A shift register 202 using a plurality of stages of flip-flops (FF) 201, NAND 203,
A first latch circuit (LAT1) 204, a second latch circuit (LAT2) 205, and the like are included. Here, the NAND 203 need not be provided. Although not shown in FIG. 2, a buffer circuit, a level shifter circuit, etc. may be arranged as necessary.

The operation will be briefly described with reference to FIG. First, a source-side clock signal, a source-side clock inverted signal, and a source-side start pulse are input to the shift register 202, and sampling pulses are sequentially output from the shift register 202 accordingly. In FIG. 2, the sampling pulse is prevented from being duplicated in the adjacent stage by the NAND 203, but this procedure is not necessarily provided. Then NAND20
The sampling pulse output from 3 is input to the first latch circuit 204 and holds the digital video signal input to the first latch circuit 204 in accordance with the timing.

When the holding of the digital video signal for one horizontal period is completed in the first latch circuit 204, a latch latch pulse is input during the blanking period, and the digital video signal held in the first latch circuit 204 is The data is transferred all at once to the second latch circuit 205.

Thereafter, the shift register circuit 202 operates again to output a sampling pulse, and the holding of the digital video signal for the next horizontal period is started. At the same time, the second latch circuit 205
The digital video signal held by the source signal line (in FIG. 2, S1, S2,..., S
is written in each pixel.

The gate signal line driver circuit 102 has a configuration as shown in FIG. The gate signal line driver circuit shown as an example in FIG. 16 has y pixels in the vertical direction, and includes a flip-flop (F
F) A shift register 1602, a NAND 1603, a buffer 1604, and the like using a plurality of stages 1601 are provided. Here, there is no need to provide the NAND 1603 in particular. Further, although not shown in FIG. 16, a level shifter circuit or the like may be arranged as necessary.

The operation will be briefly described with reference to FIG. First, a gate-side clock signal, a gate-side clock inverted signal, and a gate-side start pulse are input to the shift register 1602, and pulses are sequentially output from the shift register 1602 accordingly. In FIG. 16, NAND 1603 is used so that the output timings of pulses in adjacent stages do not overlap. Thereafter, the gate signal lines are sequentially selected through the buffer 1604. A period during which a certain gate signal line is selected is one horizontal period.

FIG. 3 shows a configuration of a pixel portion of the electrophoretic display device of the present invention. In FIG. 3A, a portion surrounded by a dotted line frame 300 is one pixel, and its structure is shown in FIG.

Each pixel includes a source signal line 301, a gate signal line 302, and a switching TFT.
303, a memory circuit 304, and an electrophoretic element 305. Switching TFT 303
Is connected to any one of the gate signal lines G1 to Gy, and the switching T
One of the source region and the drain region of the FT 303 is connected to one of the source signal lines S <b> 1 to Sx, and the other is connected to the memory circuit 304.

Signals input to the source signal lines S1 to Sx are transferred to the memory circuits 310 to 312 via the drains and sources of the switching TFTs 307 to 309 that are turned on by the signals input to the gate signal lines G1 to Gy. Entered. In accordance with the output potential of the memory circuit, the electrophoretic elements 313 to 315 move to express the luminance of each pixel.

[Embodiment 2]
FIG. 4 shows a configuration example of a pixel in the case of 3 bits (8 gradations). The pixel shown in FIG. 4 receives a 3-bit digital video signal per pixel and displays 2 ³ = 8 gradations. Each pixel has switching TFTs 407 to 409, memory circuits 410 to 412, and electrophoretic elements 413 to 415. The gate electrodes of the switching TFTs 407 to 409 are connected to any one of the gate signal lines G1 to Gy, respectively.
One of the two source regions and the drain region is connected to any one of the source signal lines S1 to Sx, and the other is connected to any one of the memory circuits 310 to 312.

In each pixel, the electrophoretic element is divided into three regions having different areas, the respective area ratios are set to 1: 2: 4, and each is controlled, so that eight gradations can be realized.
In the case of color, (2 ³ ) ³ = 512 colors can be realized. Next, the operation of the pixel in this case will be described.

A configuration example of a source signal line driver circuit corresponding to a 3-bit digital video signal is shown in FIG. The source signal line driver circuit shown as an example in FIG. 17 has x pixels in the horizontal direction, has three source signal lines per pixel, and inputs a 3-bit digital video signal to 2 ^3. = 8
This is a source signal line driver circuit corresponding to a display device that performs gradation display, and a flip-flop (
FF) 1701 using a plurality of stages, a shift register 1702, a NAND 1703, a first latch circuit (LAT1) 1704, a second latch circuit (LAT2) 1705, and the like. First
And the second latch circuit includes three bits arranged in parallel, and a three-bit digital video signal (
D1 to D3) are held. Here, the NAND 1703 is not necessarily provided. Although not shown in FIG. 2, a buffer circuit, a level shifter circuit, etc. may be arranged as necessary.

The gate signal line driver circuit may be the same as that shown in FIG. One gate signal line selection pulse is simultaneously input to the gate electrodes of the switching TFTs 407 to 409 in one pixel.

The timing chart shown in FIG. 5 shows a source side clock signal (CK), a source side clock inverted signal (CKb), a source side start pulse (SP), and shift register outputs (SR1 to SR2).
, Sampling pulses (Samp1 to SampX), latch pulses (Latch), and digital video signals (D1 to D3).
The operation will be described based on the timing chart.

The next horizontal period is indicated by 502 with respect to a certain horizontal period 501. Each horizontal period has dot sampling periods 503 and 505 and horizontal blanking periods 504 and 506. That is, the horizontal period is a period from when the first-stage sampling pulse is output until the first-stage sampling pulse is output again. The dot sampling period is 1
This is a period from when the sampling pulse at the stage is output until the sampling pulse at the final stage is output.

Note a certain horizontal period 501. In the dot sampling period, the digital video signal is held in the first latch circuit in accordance with the output of the sampling pulse. The holding timing follows the down edge of the sampling pulse in the example of FIG. 5, and the digital video signal input to 3 bits, that is, one pixel is simultaneously held. This operation is performed in order from the first stage and continues to the last stage.

When the holding operation in the first latch circuit at the final stage ends, a horizontal blanking period starts. When a latch pulse is input in the horizontal blanking period (521), the digital video signals held in the first latch circuit are transferred to the second latch circuit all at once.

Thereafter, the horizontal blanking period ends and the next horizontal period 502 is entered. In the first latch circuit, the digital video signal is similarly held. On the other hand, the digital video signal held in the second latch circuit is written into the memory circuit of the pixel portion during the dot sampling period 505, precisely until the next latch pulse is input. The write operation to the memory circuit is performed simultaneously for 3 bits.

  Examples of the present invention will be described below.

FIG. 6A shows an example in which an SRAM is used for a pixel. SRAM is a combination of two inverters and has a holding function. Like a DRAM, it does not require a refresh operation. Once held, the contents will not be erased unless the power is turned off. Rewriting is not necessary. Therefore, in combination with the electrophoretic display device, a great effect is exhibited in reducing power consumption.

A second embodiment is shown in FIG. The pixel in FIG. 6B is an example of a pixel configuration in which an SRAM is used for the memory circuit shown in Embodiment 1 and 3-bit gradation expression is performed. Eight gradations can be realized by dividing the pixel into three regions having different areas, setting the area ratio to 1: 2: 4, and changing the white and black regions according to the area ratio. In the case of color, (2 ³ ) ³ = 5
12 colors can be realized.

The configuration of the drive circuit is the same as that shown in FIGS. The operation is the same as that described with reference to FIG. 5 in the embodiment, and the description thereof is omitted here.

FIG. 7 shows an example in which the pixel portion is actually laid out with the configuration shown in FIG. 1
The pixel has three 1-bit SRAMs, each connected to a switching TFT and further connected to an electrophoretic element. The numbers given in the figure correspond to FIG. 6 (B). The area of the pixel electrode of the electrophoretic elements 620 to 622 is 1: 2: 4. The same gate signal line selection pulse is input to the gate signal lines connected to the switching TFTs 617 to 619. Therefore, the switching TFTs 617 to 619 are simultaneously turned on.
-Turn off.

In FIG. 7, the cross section shown by AA ', BB', and CC 'is shown in FIG. In this embodiment, the switching TFT, SRAM, etc. are constituted by a top gate type polysilicon TFT. The numbers given in the figure correspond to FIG. 6 (B).

In the first and second embodiments, the digital video signals for 3 bits are written to the pixels in parallel from different source signal lines. However, each bit is switched by sharing the source signal line. You can also write in order.

A configuration example of a source signal line driver circuit in the case of performing such writing is shown in FIG. The structures of the shift register 1802 to the second latch circuit 1805 are the same as those shown in FIG.

Here, since a 3-bit digital video signal is written to the memory circuit in the pixel through one source signal line, a selection switch 1806 is provided between the output of the second latch circuit 1805 and the source signal line. Is provided. Up to the second latch circuit 1805, each bit of the 3-bit digital video signal has been processed in parallel, but the input to the source signal line is sequentially performed by the selection switch. The practitioner may set the order appropriately.

FIG. 19 shows a configuration example of a gate signal line driving circuit used in this embodiment.
The configuration of the shift register 1902 to the buffer 1904 may be the same as that shown in FIG.

The buffer 1604 in FIG. 16 and the buffer 1904 in FIG. 19 are different in the number of stages, but the number of stages may be set depending on whether the buffer output is obtained at the H level or the L level. It does not matter about the number of steps.

In the first embodiment and the second embodiment, one gate signal line selection pulse is set to 3 in one pixel.
Two switching TFTs are driven simultaneously, and thereby a 3-bit digital video signal is simultaneously written. In this embodiment, after the output of the buffer 1904, a multiplexer 1905 is used to set a plurality of horizontal periods. Divided into sub-periods. This number of divisions is equal to the number of bits of the digital video signal, and is divided into three in this embodiment. The switching timing of the selection switch provided in the source signal line driver circuit and the division timing of the horizontal period by the multiplexer are synchronized, and the digital video signal of each bit is written in each sub period.

FIG. 21 shows a timing chart. The sampling and latching operations of the digital video signal are the same as those in the first and second embodiments. The digital video signal sampled and held in a certain horizontal period 2101 is transferred to the second latch circuit during the blanking period. After that, in the next horizontal period 2102, the digital video signal is output from the second latch circuit to the source signal line and written to the memory circuit in the pixel while the digital video signal of the next row is being sampled. It is.
At this time, the writing period to the pixel is divided by the multiplexed signals (MPX1 to MPX1), and the digital video signal of each bit is sequentially written in the memory circuit in the pixel. Note that the timing at which the selection switch in the source signal line driver circuit selects the source signal line is also synchronized with the multiplex signal.

In this embodiment, a method for simultaneously manufacturing a pixel portion of an electrophoretic display device of the present invention and a TFT of a driver circuit portion provided around the pixel portion will be described. However, in order to simplify the description, a CMOS circuit which is a basic unit is illustrated in the drive circuit portion.

As for the pixel portion, only the connection portion of the source signal line, the switching TFT, and the pixel electrode is shown. Regarding the memory circuit, in the case of using an SRAM, the configuration is the same as that of the CMOS circuit of the drive circuit section, and therefore not particularly shown.

First, as shown in FIG. 12A, a silicon oxide film on a substrate 5001 made of glass such as barium borosilicate glass represented by Corning # 7059 glass or # 1737 glass or aluminoborosilicate glass, A base film 5002 made of an insulating film such as a silicon nitride film or a silicon oxynitride film is formed.
For example, a silicon oxynitride film 5002a formed from SiH ₄ , NH ₃ , and N ₂ O by plasma CVD is formed to 10 to 200 [nm] (preferably 50 to 100 [nm]), and similarly SiH ₄ ,
A silicon oxynitride silicon nitride film 5002b formed from N ₂ O is stacked to a thickness of 50 to 200 [nm] (preferably 100 to 150 [nm]). Although the base film 5002 is shown as a two-layer structure in this embodiment, it may be formed as a single-layer film of the insulating film or a structure in which two or more layers are stacked.

The island-shaped semiconductor layers 5003 to 5005 are formed using a crystalline semiconductor film in which a semiconductor film having an amorphous structure is formed using a laser crystallization method or a known thermal crystallization method. This island-shaped semiconductor layer 50
The thickness of 03 to 5005 is 25 to 80 [nm] (preferably 30 to 60 [nm]).
The material of the crystalline semiconductor film is not limited, but preferably silicon or silicon germanium
It may be formed of (SiGe) alloy or the like.

In order to fabricate a crystalline semiconductor film by a laser crystallization method, a pulse oscillation type or a continuous emission type excimer laser, a YAG laser, or a CW laser is used. When these lasers are used, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly collected by an optical system and irradiated onto a semiconductor film. The conditions for crystallization are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 30 [Hz] and the laser energy density is 100 to 400 [mJ / cm ² ] (typically 200 to 300 [mJ / cm ² ]). When a YAG laser is used, the second harmonic is used and the pulse oscillation frequency is 1 to 10 [kHz], and the laser energy density is 300 to 600 [mJ / cm ² ] (typically 350 to 500 [mJ]. / cm ² ]). Then, a laser beam condensed in a linear shape with a width of 100 to 1000 [μm], for example, 400 [μm] is irradiated over the entire surface of the substrate, and the superposition ratio (overlap ratio) of the linear laser light at this time is 80 Perform as ~ 98 [%].

Next, a gate insulating film 5006 is formed to cover the island-shaped semiconductor layers 5003 to 5005. The gate insulating film 5006 is formed by plasma CVD or sputtering, and has a thickness of 40 to 150 [n].
m] is formed of an insulating film containing silicon. In this embodiment, a silicon oxynitride film is formed with a thickness of 120 [nm]. Needless to say, the gate insulating film is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. For example, when a silicon oxide film is used, TEOS (Tetraethyl Orth
osilicate) and O ₂ are mixed, the reaction pressure is 40 [Pa], the substrate temperature is 300 to 400 [° C.], the high frequency (13.56 [MHz]), and the power density 0.5 to 0.8 [W / cm]. ² ] and can be formed by discharging. The silicon oxide film thus produced can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 [° C.].

Then, a first conductive film 5007 for forming a gate electrode over the gate insulating film 5006.
And a second conductive film 5008 are formed. In this embodiment, the first conductive film 5007 is made of 5 with Ta.
The second conductive film 5008 is formed to a thickness of 100 to 300 [nm] with W.

The Ta film is formed by sputtering, and a Ta target is sputtered with Ar.
In this case, when an appropriate amount of Xe or Kr is added to Ar, the internal stress of the Ta film can be relieved and peeling of the film can be prevented. The resistivity of the α-phase Ta film is about 20 [μΩcm] and can be used for the gate electrode, but the resistivity of the β-phase Ta film is about 180 [μΩcm] and is used as the gate electrode. It is unsuitable. In order to form an α-phase Ta film, tantalum nitride having a crystal structure close to Ta's α-phase is formed on a Ta base with a thickness of about 10 to 50 nm. It can be easily obtained.

When forming a W film, it is formed by sputtering using W as a target. In addition, it can be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, in order to use as a gate electrode, it is necessary to reduce the resistance, and the resistivity of the W film is 20 [μ.
Ωcm] or less is desirable. Although the resistivity of the W film can be reduced by increasing the crystal grains, if the impurity element such as oxygen is large in W, the crystallization is hindered and the resistance is increased. From this, in the case of the sputtering method, by using a W target having a purity of 99.9999 [%] and further forming a W film with sufficient consideration so that impurities are not mixed in from the gas phase during film formation, A resistivity of 9 to 20 [μΩcm] can be realized.

Note that in this embodiment, the first conductive film 5007 is Ta and the second conductive film 5008 is W, but there is no particular limitation, and any of them is selected from Ta, W, Ti, Mo, Al, Cu, and the like. Or an alloy material or a compound material containing the element as a main component. Also,
A semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. As an example of a combination other than this embodiment, the first conductive film 5007 is preferable.
In which tantalum nitride (TaN) is formed and the second conductive film 5008 is W, and the first conductive film 5007 is formed of tantalum nitride (TaN) and the second conductive film 5008 is Al. The first conductive film 5007 is formed of tantalum nitride (TaN), and the second conductive film 500
The combination which makes 8 Cu is mentioned.

When the LDD region (Lightly Doped Drain) can be made small, a W single layer or the like may be used. Even if the configuration is the same, the LDD can be formed by increasing the taper angle. The length of can be reduced.

Next, a resist mask 5009 is formed, and a first etching process is performed to form electrodes and wirings. In this embodiment, an ICP (Inductively Coupled Plasma) etching method is used, CF ₄ and Cl ₂ are mixed in an etching gas, and a coil type electrode of 500 [W] is applied at a pressure of 1 [Pa]. RF (13.56 [MHz]) power is applied to generate plasma. 100 [W] RF (13.56 [MHz]) power is also applied to the substrate side (sample stage),
A substantially negative self-bias voltage is applied. When CF ₄ and Cl ₂ are mixed, W film and T
The a film is etched to the same extent.

Under the above etching conditions, by making the shape of the resist mask suitable, the end portions of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. The angle of the tapered portion is 15 to 45 °.
In order to perform etching without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of about 10 to 20%. The selectivity of the silicon oxynitride film to the W film is 2
Since it is ˜4 (typically 3), the surface where the silicon oxynitride film is exposed is etched by about 20 to 50 [nm] by the over-etching process. In this manner, the first shape conductive layers 5010 to 50 including the first conductive layer and the second conductive layer by the first etching process.
13 (first conductive layers 5010a to 5013a and second conductive layers 5010b to 5013b) are formed. At this time, in the gate insulating film 5006, the first shape conductive layers 5010 to 5 are used.
A region not covered with 013 is etched by about 20 to 50 [nm] to form a thinned region.

Then, an impurity element imparting N-type is added by performing a first doping process.
As a doping method, an ion doping method or an ion implantation method may be used. The conditions for the ion doping method are a dose of 1 × 10 ^{13 to} 5 × 10 ¹⁴ [atoms / cm ² ] and an acceleration voltage of 60 to 100 [
keV]. An element belonging to Group 15 as an impurity element imparting n-type, typically phosphorus
(P) or arsenic (As) is used, and phosphorus (P) is used here. In this case, the conductive layer 501
0 to 5013 serve as a mask for the impurity element imparting n-type, and first impurity regions 5014 to 5016 are formed in a self-aligning manner. 1 in the first impurity regions 5014 to 5016
An impurity element imparting n-type conductivity is added in a concentration range of × 10 ²⁰ to 1 × 10 ²¹ [atoms / cm ³ ] (FIG. 12B).

Next, as shown in FIG. 12C, a second etching process is performed without removing the resist mask. The W film is selectively etched using CF ₄ , Cl ₂ and O _{2 as an} etching gas. At this time, second shape conductive layers 5017 to 5020 (first conductive layers 5017a to 5020a and second conductive layers 5017b to 5020b) are formed by the second etching process. At this time, in the gate insulating film 5006, the second shape conductive layers 5017 to 5020 are used.
The region not covered with is further etched by about 20 to 50 [nm] to form a thinned region.

The etching reaction of the W film or Ta film with the mixed gas of CF ₄ and Cl ₂ can be estimated from the generated radicals or ion species and the vapor pressure of the reaction product. When the vapor pressures of W and Ta fluorides and chlorides are compared, WF _6, which is a fluoride of W, is extremely high, and other WCl ₅
, TaF ₅ and TaCl ₅ are comparable. Therefore, in the mixed gas of CF ₄ and Cl ₂ , the W film and T
Both a films are etched. However, when an appropriate amount of O ₂ is added to this mixed gas, CF ₄ and O ₂
Reacts to CO and F, and a large amount of F radicals or F ions are generated. As a result, the etching rate of the W film having a high fluoride vapor pressure is increased. On the other hand, the increase in etching rate of Ta is relatively small even when F increases. Also, Ta is more easily oxidized than W, so
The surface of Ta is oxidized by adding O ₂ . Since the Ta oxide does not react with fluorine or chlorine, the etching rate of the Ta film further decreases. Therefore, it is possible to make a difference in the etching rate between the W film and the Ta film, and the etching rate of the W film can be made larger than that of the Ta film.

Subsequently, a second doping process is performed. In this case, an impurity element imparting n-type conductivity is doped as a condition of a high acceleration voltage by lowering the dose than in the first doping process. For example, the acceleration voltage is set to 70 to 120 [keV] and the dose is 1 × 10 ¹³ [atoms / cm ² ].
In 2 (B), a new impurity region is formed inside the first impurity region formed in the island-shaped semiconductor layer. Doping is performed using the second shape conductive layers 5017 to 5020 as masks against the impurity elements so that the impurity elements are also added to the semiconductor layers in the lower regions of the first conductive layers 5017 a to 5020 a. Thus, the second impurity regions 5021 to 5023 are obtained.
Is formed. The concentration of phosphorus (P) added to the second impurity regions 5021 to 5023 has a gradual concentration gradient according to the thickness of the tapered portions of the first conductive layers 5017a to 5020a. Specifically, in the semiconductor layer overlapping the tapered portions of the first conductive layers 5017a to 5020a, the impurity concentration is slightly lower from the end of the tapered portions of the first conductive layers 5017a to 5020a toward the inside. However, the concentration is almost the same (FIG. 12C)
.

Subsequently, a third etching process is performed as shown in FIG. CH as etching gas
Using F ₆ , a reactive ion etching method (RIE method) is used. By the third etching process, the tapered portions of the first conductive layers 5017a to 5020a are partially etched,
The region where the first conductive layer overlaps with the semiconductor layer is reduced.
By the third etching process, third shape conductive layers 5024 to 5027 (first conductive layers 5024a to 5027a and second conductive layers 5024b to 5027b) are formed. At this time, in the gate insulating film 5006, regions that are not covered with the third shape conductive layers 5024 to 5027 are further etched and thinned by about 20 to 50 [nm].

By the third etching treatment, the third impurity region 5028 is formed in a part of the second impurity regions 5021 to 5023, that is, in a region which does not overlap with the first conductive layers 5024a to 5027a.
˜5030 are formed (FIG. 12D).

Then, as shown in FIG. 13A, a resist mask 5031 is newly formed, and an island-like semiconductor layer 5003 for forming a P-channel TFT is provided with a fourth conductivity type opposite to the first conductivity type. Impurity regions 5032 are formed. Using the first conductive layer 5025b as a mask for the impurity element, an impurity region is formed in a self-aligning manner. At this time, in the impurity region 5032,
Phosphorus is added to each of the parts at different concentrations, but P-type can be imparted by making the dose amount of diborane (B ₂ H ₆ ) sufficiently higher than the dose amount of phosphorus. Note that, in the impurity region 5032, the impurity concentration is 2 × 10 ²⁰ to 2 in any region.
× 10 ²¹ [atoms / cm ³ ].

Through the above steps, impurity regions are formed in each island-like semiconductor layer. The third shape conductive layers 5024, 5025, and 5027 overlapping with the island-shaped semiconductor layers function as gate electrodes.
Reference numeral 5026 functions as a source signal line.

After the resist mask 5031 is removed, a process of activating the impurity element added to each island-shaped semiconductor layer is performed for the purpose of controlling the conductivity type. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. In the thermal annealing method, the oxygen concentration is 1 [ppm]
In the following, preferably in a nitrogen atmosphere of 0.1 [ppm] or less, 400 to 700 [° C.], typically 5
The heat treatment is performed at 00 to 600 [° C.], and in this embodiment, heat treatment is performed at 500 [° C.] for 4 hours.
However, when the wiring material used for the third shape conductive layers 5024 to 5027 is weak against heat,
In order to protect the wiring and the like, activation is preferably performed after an interlayer insulating film (having silicon as a main component) is formed.

Further, a heat treatment is performed at 300 to 450 [° C.] for 1 to 12 hours in an atmosphere containing 3 to 100 [%] hydrogen to perform a step of hydrogenating the island-shaped semiconductor layer. This step is a step of terminating dangling bonds in the semiconductor layer with thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

Next, as shown in FIG. 13B, the first interlayer insulating film 5033 is formed from a silicon oxynitride film with a thickness of 100 to 200 [nm]. A second interlayer insulating film 5034 made of an organic insulating material is formed thereon. The second interlayer insulating film also has the purpose of sufficiently planarizing the substrate surface. Next, an etching process for forming a contact hole is performed.

  Thereafter, wirings 5035 to 5039 and gate signal lines 5040 are formed.

In this embodiment, the writing TFT has a double gate structure, but may have a single gate structure, a triple gate structure, or a multi-gate structure.

As described above, a driver circuit portion having an N-channel TFT and a P-channel TFT,
The writing TFT and the pixel portion having a storage capacitor can be formed over the same substrate. In this specification, such a substrate is called an active matrix substrate.

Further, according to the steps shown in this embodiment, the number of photomasks necessary for the production of the active matrix substrate is 5 (island-like semiconductor layer pattern, first wiring pattern (source signal line, capacitor wiring)
, P channel region mask pattern, contact hole pattern, second wiring pattern). As a result, the process can be shortened, and the manufacturing cost can be reduced and the yield can be improved.

Subsequently, after a third interlayer insulating film 5041 is formed, a contact hole is formed. Thereafter, a pixel electrode is formed in the pixel portion by patterning.

Next, a microcapsule 5043 enclosing a transparent liquid and charged particles is applied on the pixel electrode. Since the microcapsules 5043 are generally around 80 [μm] as described above, they can be applied by a printing method or the like, and the microcapsules need only be applied at desired positions in the pixel portion.

Thereafter, a counter electrode 5044 made of a transparent conductive film is formed. As a material of the transparent conductive film,
Typically, indium tin oxide (ITO) or the like may be used.

Finally, a protective film 5045 for protecting the surface is formed to complete an active matrix electrophoretic display device as shown in FIG. Note that although the protective film is formed over the entire surface of the substrate in FIG. 13C, it may be formed only over the pixel portion or over the entire surface except on the FPC.

Note that the TF in the active matrix type liquid crystal display device produced by the above process.
Although T has a top gate structure, the present embodiment can be easily applied to a TFT having a bottom gate structure, a dual gate structure, and other structures.

In this embodiment, the glass substrate is used. However, the present invention is not limited to the glass substrate, and can be implemented by using a substrate other than the glass substrate, such as a plastic substrate, a stainless steel substrate, and a single crystal wafer. is there. In particular, by using a substrate rich in elasticity, the display device itself can be flexible.

  This embodiment can be implemented by being freely combined with Embodiments 1 to 3.

The electrophoretic display device of the present invention has various uses. In this embodiment, an example in which the electrophoretic display device of the present invention is applied to an electronic device will be described.

Examples of semiconductor devices incorporating a liquid crystal display device include portable information terminals (electronic notebooks, mobile computers, mobile phones, and the like), video cameras, digital cameras, personal computers, televisions, and the like. Examples of these are shown in FIGS.

FIG. 14A illustrates a mobile phone, which includes a main body 3001, an audio output unit 3002, and an audio input unit 300.
3, a display unit 3004, an operation switch 3005, and an antenna 3006. The present invention can be applied to the display portion 3004.

FIG. 14B illustrates a video camera, which includes a main body 3011, a display portion 3012, and an audio input portion 301.
3, an operation switch 3014, a battery 3015, and an image receiving unit 3016. The present invention can be applied to the display portion 3012.

FIG. 14C illustrates a personal computer, which includes a main body 3021, a display portion 3022, a keyboard 3023, and the like. The present invention can be applied to the display portion 3022.

FIG. 14D illustrates a portable information terminal, which includes a main body 3031, a stylus pen 3032, and a display portion 3.
033, an operation button 3034, and an external interface 3035. The present invention can be applied to the display portion 3033.

FIG. 15A illustrates a digital camera, which includes a main body 3101, a display portion (A) 3102, and an eyepiece unit 3.
103, an operation switch 3104, a display unit (B) 3105, an image receiving unit (not shown), a battery 3106, and the like. The present invention includes a display portion (A) 3102 and a display portion (B) 3105.
Can be applied to.

FIG. 15B illustrates a portable book, which includes a main body 3111, a display portion 3112, a storage medium 3113, an operation switch 3114, and the like, and includes a mini disc (MD) and a DVD (Digital).
l Versatile Disc) and the received data are displayed. The present invention can be applied to the display portion 3112.

FIG. 15C illustrates a television set including a main body 3121, a speaker 3122, a display portion 3123, a receiving device 3124, an amplifying device 3125, and the like. The present invention can be applied to the display portion 3123.

FIG. 15D shows a player using a recording medium on which a program is recorded.
, A display portion 3132, a speaker portion 3133, a recording medium 3134, and an operation switch 3135. This apparatus uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 3132.

Claims (3)

On a substrate, a source signal line driver circuit, a gate signal line driver circuit, and a pixel portion having a plurality of pixels,
The pixel portion is located at a central portion on the substrate,
The source signal line driving circuit and the gate signal line driving circuit are provided at a position different from the central portion on the substrate,
The pixel has a plurality of sub-pixels,
Each of the sub-pixels includes a switching transistor, a memory circuit, and a pixel electrode,
The memory circuit includes a first inverter and a second inverter,
The video signal is written to the memory circuit via the switching transistor,
In accordance with the data written in the memory circuit, the potential of the pixel electrode is controlled,
In the plurality of sub-pixels, the gates of the switching transistors are electrically connected to the same gate signal line,
In the plurality of subpixels, one of a source and a drain of each of the switching transistors is electrically connected to different source signal lines. On a substrate, a source signal line driver circuit, a gate signal line driver circuit, and a pixel portion having a plurality of pixels,
The pixel portion is located at a central portion on the substrate,
The source signal line driving circuit and the gate signal line driving circuit are provided at a position different from the central portion on the substrate,
The pixel has a plurality of sub-pixels,
Each of the sub-pixels includes a switching transistor, a memory circuit, and a pixel electrode,
The memory circuit includes a first inverter and a second inverter,
The video signal is written to the memory circuit via the switching transistor,
In accordance with the data written in the memory circuit, the potential of the pixel electrode is controlled,
In the plurality of subpixels, one of the source and the drain of each of the switching transistors is electrically connected to the same source signal line,
In the plurality of subpixels, a gate of each of the switching transistors is electrically connected to different gate signal lines. In claim 1 or claim 2,
A display device, wherein the plurality of sub-pixels have different areas.

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