JP2000338918A - Display device and driving method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display device and driving method thereof capable of realizing multi-gradation while suppressing an increase of device cost and an enlargement of occupying space of a peripheral circuit. SOLUTION: This display device features being equipped with a data source 10 supplying n×m bits (n and m are integers more than 1) of display data per one picture element, a horizontal driving circuit 12 having a digital analog converter 12c converting m bit units of the display data inputted from the data source 10 into a 2m gradation analog signal, a display zone 11 having a picture element 14 comprising n pieces of display elements 14a-1, 14a-2,..., 14a-n having a rate of display areas of 2(n-1)*m:2(n-2)*m:...: 2(n-n)*m, and a vertical driving circuit 13 outputting a selection signal for allocating and writing n piece units of the analog signals outputted from the digital analog converter 12c each into n pieces of the display elements 14a-1, 14a-2,..., 14a-n.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device and a driving method thereof, and more particularly to an active matrix type display device for sequentially driving a plurality of pixels arranged in a matrix for each horizontal line and a driving method thereof.

[0002]

2. Description of the Related Art FIG. 12 shows a configuration diagram of an active matrix type display device. This display device has a display area 101, a horizontal drive circuit 102, and a vertical drive circuit 103. In the display area 101, as shown in an enlarged view in a circle in the figure, gate lines g1, g2,... For a plurality of rows and column lines c1, c2,. The pixel 104 is arranged in the configuration. Each pixel 104 is a thin film transistor
or) a liquid crystal element or an electroluminescence element having a TFT, wherein the gate electrode of the thin film transistor TFT is connected to gate lines g1, g2,..., and the source electrode is connected to column lines c1, c2,. . The horizontal drive circuit 102 sequentially samples m-bit independent display data in accordance with the clocks (HST, HCK) and sequentially outputs each of the column lines c1, c.
.., A sampling latch 102a that latches every 2.
A line memory 102b for storing the latched display data for one horizontal line in response to a latch pulse, and converting display data simultaneously output for one horizontal line from the line memory 102b to an analog signal to convert each column line c
, C2,... And a digital-to-analog converter (hereinafter referred to as DAC) 102c. Then, the vertical drive circuit 103 supplies the clocks (VST, VC
K), a selection signal is sequentially applied to each of the gate lines g1, g2,.

According to the display device having such a configuration, the m-bit display data input to the horizontal drive circuit 102 is 2 bits.
^The signal is converted into an analog signal of ^m gradations and is simultaneously input to each column line c1, c2,... for one horizontal line. The analog signal input to the column lines c1, c2,... Is applied to the gate line g1 (or g1) selected by the vertical drive circuit 103.
,...) Are written to the respective pixels 104 and held as image data for one frame. As a result, in each pixel 104, an image display of 2 ^m gradation corresponding to the analog signal is performed.

[0004]

However, in a display device having such a configuration, the number of gradations of display data is determined by the number of processing bits of the horizontal drive circuit 102. It is necessary to increase the number of processing bits of the horizontal drive circuit 102. However, when the number of processing bits of the horizontal drive circuit 102 is increased, the area occupied by the horizontal drive circuit 102 (in particular, the area occupied by the DAC) increases at a rate exceeding the rate of increase in the number of processing bits. For example, when the number of processing bits of the horizontal drive circuit 102 is increased from 3 bits to 6 bits, the occupied area of the DAC 102c becomes 2 ^6-3
= 8 times increase. Therefore, the device cost increases, and when peripheral circuits such as the horizontal drive circuit 102 and the vertical drive circuit 103 are mounted on the same substrate as the display area 101, the frame in which these peripheral circuits are formed increases.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a display device capable of increasing the number of gradations while suppressing an increase in device cost and an area occupied by peripheral circuits, and a driving method thereof.

[0006]

According to the present invention, there is provided a display apparatus for supplying n × m bits (n and m are integers of 2 or more) per pixel. Source, horizontal drive means having a digital-to-analog converter for converting display data input from this data source into an analog signal of 2 ^m gradation in m bits, and the display area ratio is 2 ^{(n-1) * m} : 2 ^{(n-2) * m} : ...: 2
^{(nn) * m} a display area having pixels consisting of n display elements, and a selection signal for assigning and writing an analog signal output from the digital-to-analog converter to n display elements in units of n. It is characterized by having vertical driving means for outputting.

In the display device having such a configuration, the display data of n × m bits supplied from the data source is converted into an analog signal of 2 ^m gradation in m bits by a digital-to-analog converter. Then, the converted analog signals are respectively assigned to n display elements by the vertical driving means and written. Therefore, an analog signal corresponding to nxm bits is displayed on one pixel composed of n display elements. Here, the n display elements to which each analog signal is written have a display area ratio of 2 ^{(n-1) * m} : 2 ^{(n-2) * m} : ...: 2 ^{(nn) * m.} I have. Therefore, the display data of n × m bits is divided into n by m bits and converted into analog signals, and the analog signals corresponding to m bits are allocated to display elements having a large display area in order from the upper side and displayed, whereby n data are displayed. In one pixel constituted by the display elements described above, a display of 2 ^{n * m} gradation weighted according to the display characteristics of the pixel is performed.

[0008] The method of driving a display device according to the present invention comprises the steps of:
A digital-to-analog converter that converts display data in bit units to an analog signal of 2 ^m gradation and a pixel including n (n is an integer of 2 or more) display elements, and the display area of each of these display elements Is 2 ^{(n-1) * m} : 2 ^{(n-2) * m} :
...: 2 ^{(nn) * m} is a driving method of the display device, and is characterized in that it is performed as follows. First, the display data of n × m bits is divided into n units of m bits, and each of the divided display data is converted into an analog signal of 2 ^m gradation by a digital / analog converter. Then
With respect to n display elements constituting a pixel, display is performed by allocating the display signals having the larger display area in order from the upper side of these analog signals.

In such a driving method, the display data in n units each divided into n bits is converted into an analog signal of 2 ^m gradation and assigned to each of n display elements constituting a pixel to be displayed. . Therefore, one pixel has n
An analog signal corresponding to × m bits is displayed. Here, the n display elements have a display area ratio of 2 ^{(n
-1) * m} : 2 ^{(n-2) * m} : ...: 2 ^{(nn) * m} , and each analog signal is assigned to a display element having a larger display area in order from the upper side and displayed. , N display elements are displayed with 2 ^{n * m} gradations weighted according to the display characteristics of the pixels.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1A is a configuration diagram illustrating an example of an active matrix display device according to the first embodiment of the present invention. Further, FIG.
It is a principal part enlarged view of (1).

As shown in FIG. 1, the display device includes a data source 10, a display area 11, a horizontal drive circuit 12, and a vertical drive circuit 13, and the display area 11 has pixels 14 arranged in a matrix. . However, here, for simplicity of description, a case where pixels 14 of 4 rows × 4 columns are arranged in a matrix is illustrated.

The data source 10 supplies display data for each pixel 14 composed of n × m bits to the horizontal drive circuit 12 as original image data. Here, in particular, the data source 10 divides the display data of n × m bits into n units of m bits, rearranges them in a predetermined order, and supplies them to the horizontal drive circuit 12. Further, a processing circuit (not shown) for dividing and rearranging the display data is provided.

For example, when n = 2, each display data of 2 × m bits is divided into upper data H for upper m bits and lower data L for lower m bits. And
First, the upper data H1 for one horizontal line of the first line is arranged in the horizontal arrangement order of the pixels 14, and then the lower data L1 for the same one horizontal line is arranged in the horizontal arrangement order of the pixels 14. Hereinafter, the upper data H2
, Lower data L2, upper data H3, lower data H3
,... And the horizontal drive circuit 12
To supply.

The display area 11 has a plurality of columns (for example, four columns).
, And column lines c1, c2,... And first gate lines g1-1, g2-1 for a plurality of rows (for example, four rows) intersecting the column lines c1, c2,.
, G3-1, and g4-1. In the display area 11, each first gate line g1-1
, G2-1,..., Are arranged in parallel with the second to n-th gate lines. For example, when n = 2, the first gate line g1-1 and the second gate line g1-2 in the first row and the first gate line g1-2 in the second row are sequentially arranged in the display area 14 from the horizontal drive circuit 12 side. The gate lines g2-1, the second gate lines g2-2,... Are arranged in this order.

Each pixel 14 has n display elements 14a-1,.
, 14a-n (for the sake of simplicity, the case where n = 2 is illustrated). These n (= 2) display elements 14a-1, 14a
-2, the ratio of the display area of each display section b is 2
^{(n-1) * m} : 2 ^{(n-2) * m} : ...: 2 ^{(nn) * m}
That is, when n = 2, these display elements 14a
Display area -1,14A-2, the display device 14a-1: has a two ^0: display elements 14a-2 = 2 ^m. However, the number of display elements forming each pixel 14 is assumed to be equal to the number n of display data divisions.

These display elements 14a-1 and 14a-2 are:
It is composed of a liquid crystal element or an electroluminescence element provided with a thin film transistor (TFT) and a display section b. However, in the drawings, the TFT and the display portion b
Only shown. The display element 14 having a large display area
The gate electrode of the thin film transistor TFT a-1 is connected to the first gate line g1-1 (g2-1,...), and the gate electrode of the thin film transistor TFT of the display element 14-2 having a small display area is connected to the second gate line g1- 2 (g2-2,...), And the source electrodes of the display elements 14a-1, 14a-2 in each pixel 14 are connected to the same column line c1 (c2,...).

The horizontal drive circuit 12 includes a sampling latch 12a, a line memory 12b, and a digital-to-analog converter (hereinafter, referred to as DAC) 12c. The sampling latch 12a has a latch unit of m bits × horizontal pixels, and supplies display data in units of m bits supplied from the data source 10 to a horizontal clock (HST) by receiving a start pulse (hereinafter referred to as HST). In this case, sampling is performed sequentially for one horizontal line in synchronization with HCK) and latched for each column line c1, c2,. The line memory 12b stores the display data of m bits latched by the sampling latch 12a for one horizontal line in response to the latch pulse. The DAC 12c is provided for each of the column lines c1, c2,..., And converts display data input simultaneously for one horizontal line from the line memory 12b into an analog signal of 2 ^m gradation in m-bit units, and Input to the lines c1, c2,... The input / output characteristics of the DAC 12c are such that the non-linear characteristics of the two display elements 14a-1 and 14a-2 are corrected. From the DAC 12c, the display elements 14a-1 and 14a-2 are provided. It is assumed that an analog signal that corrects the nonlinear characteristic is output. As described above, the horizontal drive circuit 12 has one DAC 12c for each horizontal pixel, and outputs the corrected analog signal output from each DAC 12c through one column line c1 (c2,...) The data is supplied to each of the pixels in a time series.

FIG. 2 is a circuit diagram showing a configuration example of the vertical drive circuit 13. As shown in FIG.
Consists of a plurality of D-type flip-flop circuits (hereinafter, referred to as D-FF) 13a connected in series with each other, a clock line 13b connected to a clock input terminal (ck), and an enable line connected to an enable terminal (enb). 13
c is connected. Then, the first stage D-FF 13a
Is supplied with the vertical start pulse VST, each D-FF 13a sequentially performs a shift operation in synchronization with the vertical clock VCK supplied from the clock line 13b. Therefore, each gate line has a first gate line g1-1 in the first row.
, The second gate line g1-2, and the first gate line g2-1 in the second row.
, The second gate line g2-2,..., The Q output of each D-FF 13a is sequentially supplied as a selection signal via the buffer 13d. The above operation is performed only when the enable signal is supplied from the enable line 13c to the enable terminal (enb) of the D-FF 13a.

Next, the operation of the display device having the above configuration will be described with reference to FIG.
This will be described with reference to the timing chart of FIG.

First, from the data source 10, display data in units of m bits obtained by dividing display data of n.times.m bits into n (= 2) is divided into upper data H1, lower data L1, and upper data for each horizontal line. H2, lower data L2,... Are supplied to the horizontal drive circuit 12 in this order. Data source 10
The display data in m bits supplied from the clock ring (HST, HC) is supplied to the ramp ring latch 12a.
K), and each column line c
, C2,... Are latched. The latched display data is stored in the line memory 12b for one horizontal line. The stored display data is simultaneously input from the line memory 12b to the DAC 12c for one horizontal line, is converted to an analog signal of 2 ^m gradation, and is converted into each of the column lines c1, c2,.
Entered in ... That is, in the DAC 12c,
The display data is converted into an analog signal in the order of upper data H1, lower data L1, upper data H2, lower data L2,...
, C2,... Are sequentially input.

On the other hand, from the vertical drive circuit 13, the first gate line g1-1 and the second gate line g1-2 in the first row, the first gate line g2-1 in the second row, and the second gate line The selection signals are given in the order of g2-2,. As a result, the upper data H1 is written to the display elements 14a-1 connected to the first gate line g1-1 and the column lines c1, c2,... In the first row. Second gate line g1-2 and each column line c1
, C2,..., The lower data L1 is written to each display element 14a-2.

Hereinafter, similarly, the first row of the first row
The upper data H2 is written to the display element 14a-1 connected to the gate line g2-1, and the second gate line g2-2 in the second row is written.
The upper data L2 is written to the display element 14a-2 connected to. Then, the display element 14a-1, 1 of each pixel
.. Or lower data L1, L2,... Are assigned and written to 4a-2, respectively.

As described above, n = 2 display elements 1
One pixel 14 composed of 4a-1 and 14a-2 has nx
An analog signal corresponding to m bits is displayed.
At this time, the upper data H1, H2,... Are assigned and written to the display element 14a-1 having a large display area, and the lower data L1, L2,.
It will be assigned to -2 and written.

Here, n in which each analog signal is written
Each of the display elements 14a-1, 14a-2,..., 14a-n has a display area ratio of 2 ^{(n-1) * m} : 2 ^{(n-2) * m} :.
^{(nn) * m} . For this reason, it is possible for one pixel 14 composed of n display elements to display 2 ^{n * m} gradations weighted according to the display characteristics of the pixel 14.

For example, the display elements 14a-1, 14a-2,
, 14a-n are liquid crystal elements, the brightness of each of the display elements 14a-1, 14a-2,..., 14a-n constituting the pixel 14 is Y1, Y2,. Brightness Y
Is represented by the following equation (1).

(Equation 1)

The luminance per unit display area corresponding to the voltage x is represented by F (x), and each display element 14a-1, 14a-2,
.., 14a-n are written as x = Vi (i = 1 to
n), the expression (1) is expressed by the display elements 14a-1 and 14a.
−2,..., 14a-n is rewritten as the following equation (2) in consideration of the ratio of the display area. Where F (x) is
It is assumed that the function is a function corresponding to the voltage-transmittance (VT) characteristic of the liquid crystal.

(Equation 2)

Here, the voltage Vi (i = 1 to n) is represented by a function G indicating the input / output characteristics of the DAC as shown in the following equation (3).
(X). However, a in the formula is digital data of 1 or 0.

(Equation 3)

Hereinafter, for the sake of simplicity, taking the case of n = 2 as an example, the luminance Y of a pixel is rewritten from the equations (2) and (3) as the following equation (4). Can be done.

(Equation 4)

Also, as shown in the graph of FIG.
The pixel voltages (upper voltage VH, lower voltage VL) and luminance (upper luminance YH, lower luminance YL) have a non-linear relationship. Therefore, in the DAC 12c, as shown in the graph of FIG. 4B, F () is used to make the entire output (luminance: upper luminance YH, lower luminance YL) in gradation display linear. x) = α × G ⁻¹ (x), that is, correction is performed so that F (G (x)) = αx (α is a constant). Thus, equation (4) can be rewritten as equation (5) below. Here, α is an optical 1 LSB (Leas
t Significant bit).

(Equation 5)

From the above equation (5), D
By setting the input / output characteristics of the AC 12c to the inverse function of the VT characteristic of the liquid crystal, the luminance of the pixel 14 is n × m = 2 × m
It can be seen that the luminance becomes equal to the case where the bit display data is converted into an analog signal of 2 ^{n * m} = 22 ^{* m} gradation having linearity. The correction of the VT characteristic by the inverse function is as follows.
The correction is not necessarily performed in the DAC 12c, and the supplied data signal itself may be corrected. In such a case, the input / output characteristics of the DAC 12c may be a straight line.

As described above, in this display device,
Horizontal drive circuit 1 that outputs an analog signal corresponding to m bits
2, it is possible to perform gradation display corresponding to nxm bits. Therefore, it is possible to increase the number of gradations while suppressing an increase in the occupied area of the horizontal drive circuit 12.

In the first embodiment, in the data source 10, the upper data H1,.
Lower data L1, higher data H2, lower data L2,.
The case where the display data is rearranged in this order has been described. However, the rearrangement of the display data in the data source 10 can be appropriately changed together with the wiring state in the display region 11 so that the display data in the upper side is allocated in order from the display element having the larger display area in one pixel. Even when such a change is made, the same effect can be obtained.

FIG. 5 is a main part configuration diagram showing another example of the display device of the first embodiment. In the display device shown in this figure, each pixel 14 has three display elements 14a-1, 14a-2, 14a.
-3.

As described above, the three display elements 14a-1, 1a-1
If equipped with a 4a-2,14a-3, the ratio of the display area of each display element, 2 2 ^{* m:} 2 ^m: is set to 2 ^0. Each row includes a first gate line g1-1 (g2-1, g3-1,
g4-1) and the second gate line g1-2 (g2-2, g3-2, g4).
-2) and the third gate line g1-3 (g2-3, g3-3, g4
-3) is wired in order from the top. The display element 14a-1 having the largest area is connected to the first gate line g1-1 (g2-1, g3-1, g4-1), and the second gate line g1-2.
The display element 14a-2 having the next largest display area is connected to (g2-2, g3-2, g4-2), and the third gate line g1-3 is connected.
The display element 14a-3 having the smallest display area is connected to (g2-3, g3-3, g4-3). The display elements 14a-1, 14a-2, and 14a-3 forming one pixel are connected to the same column line c1 (c2, c3, c4).
Then, in a data source (not shown), n × m
= 3 × m bits of display data are divided into three in units of m bits, and input to the horizontal drive circuit in order from the higher display data.

In the display device having such a configuration, m
While a horizontal drive circuit that outputs analog signals corresponding to bits is provided, gradation display corresponding to 3 × m bits can be performed, and further multi-gradation can be achieved. In addition,
Each pixel may have a configuration including four or more display elements.

FIG. 6 is a block diagram showing an example of an active matrix type display device according to the second embodiment of the present invention. The difference between the display device of the second embodiment and the display device of the first embodiment shown in FIG.
The configuration of the display area 11 and the configuration of the vertical drive circuit 13 are the same as the configuration of the display area 11 and the configuration of the horizontal drive circuit 12 ′.

That is, the data source 10 ′ of the display device of the second embodiment horizontally drives display data of each pixel 14 composed of n × m bits in units of n × m bits as original data of an image. To the circuit 12 '.

The horizontal drive circuit 12 'includes a sampling latch 12a' and a line memory 1 similar to the first embodiment.
2b and a DAC 12c, and a selector circuit 12d is provided between the sampling latch 12a 'and the line memory 12b.

The sampling latch 12a 'has latch units for n.times.m bits.times.horizontal pixels, and the data source 1
The display data of n × m bits supplied from 0 ′ is sequentially sampled in units of m bits for one horizontal line in synchronization with a horizontal clock (hereinafter referred to as HCK) by receiving a start pulse (hereinafter referred to as HST). Then, n latches are performed for each of the column lines c1, c2,....

The selector circuit 12d selects display data for n × m bits × the number of horizontal pixels latched by the sampling latch 12a ′ in units of m bits for each horizontal pixel 14 and inputs the data to the line memory 12b. For example, n = 2
In the case of (2), among the display data of 2 × m bits × the number of horizontal pixels (four columns) of one horizontal line of the first line latched by the sampling latch 12a, first, the upper data H1 of the upper m bits is transferred. Each horizontal pixel 14 is selected and input to the line memory 12b. Next, lower m-bit lower data L1 for the same one horizontal line is selected for each horizontal pixel and input to the line memory 12b. Hereinafter, for each horizontal line, the line memory 12 sequentially stores the upper data H2, the lower data L2, the upper data H3, the lower data H3,.
Input to b.

The line memory 12b and the DAC 12
c has the same configuration as in the first embodiment.

Next, the operation of the display device having the above configuration will be described with reference to FIG.
This will be described with reference to the timing chart of FIG.

First, from the data source 10 ′, n × m
The bit display data is supplied to the horizontal drive circuit 12 '. The display data of n.times.m bits supplied from the data source 10 'is sampled for one horizontal line in units of m bits by the sampling latch 12a' of the horizontal drive circuit 12 'according to the clock (HST, HCK), and each column line is displayed. .. n are latched for each of c1, c2,. The latched display data is supplied to the selector circuit 12d.
Each of the column lines c1, c2,... Is selected in the order of the high-order data H and the low-order data L in the unit of m bits.
In b, data is stored for each horizontal line. The line memory 12b stores upper data H2, lower data L2, upper data H3, lower data H for each horizontal line.
Display data is sequentially stored in the order of 3,. The stored display data is simultaneously input to the DAC 12c for one horizontal line, converted into an analog signal of 2 ^m gradation, and input to each of the column lines c1, c2,. That is, as in the first embodiment, the display data includes upper data H1, lower data L1, and upper data H in m-bit units in the order of horizontal lines.
2, the lower-order data L2,... Are converted into analog signals in this order, and are sequentially input to the respective column lines c1, c2,.

On the other hand, the vertical drive circuit 13 applies the same timing as in the first embodiment to the first gate line g1-1 in the first row.
, The second gate line g1-2, and the first gate line g2-1 in the second column.
, The second gate line g2-2,...

Therefore, as in the first embodiment, n
= N in one pixel 14 composed of two display elements
An analog signal corresponding to × m = 2 × m bits is assigned and displayed. At this time, the upper data H1, H2,
Are assigned and written to display elements having a large display area, and the lower data L1, L2,... Are assigned and written to display elements having a small display area. Therefore, as in the first embodiment, one pixel composed of n = 2 display elements is weighted according to the display characteristics of the pixel.
^{n * m} = 2 ^{2 * m} gradation Can be displayed.

As described above, also in this display device,
Horizontal drive circuit 1 that outputs an analog signal corresponding to m bits
It is possible to perform gradation display corresponding to nxm bits while providing 2 '. Therefore, as in the first embodiment, it is possible to increase the number of gradations while suppressing an increase in the area occupied by the horizontal drive circuit 12 '.

In the second embodiment, the higher-order data H1 (or H2,
H3,...), Lower data L1 (or H2, H3,...)
The case where display data is selected in this order has been described. But,
The selection order of the display data in the selector circuit 12d is 1
It is possible to appropriately change the wiring state in the display area 11 so that the display data on the upper side is assigned in order from the display element having the larger display area in the pixel. Even when such a change is made, the same effect can be obtained.

FIG. 7 is a main part configuration diagram showing an example of an active matrix type display device according to a third embodiment of the present invention. The difference between the display device of the third embodiment shown in this figure and the display device of the first embodiment is in the configuration of the vertical drive circuit, and the configurations of the data source 10, the display area 11, and the horizontal drive circuit 12 are the same. It is assumed that

In the display device of the third embodiment, each pixel 14
, 1 of the n display elements 14a-1, 14a-2,.
4a-n are provided with n vertical drive circuits. That is, each pixel 14 has n = 2 display elements 14
In the case of the configuration of a-1 and 14a-2, two vertical drive circuits of a first vertical drive circuit 13-1 and a second vertical drive circuit 13-2 are provided. The configurations of the first vertical drive circuit 13-1 and the second vertical drive circuit 13-2 are the same as those of the first embodiment. However, the first vertical drive circuit 13
-1 are connected to the first gate lines g1-1, g2-1,.
The vertical drive circuit 13-2 includes second gate lines g1-2, g2-2,.
Connected to.

For example, the first vertical drive circuit 13-1 and the second vertical drive circuit 13-2 are used for the first row by the first vertical drive circuit 13-1 during the first half frame, for example. After the first gate lines g1-1, g2-1,... Are sequentially selected from the eyes, the second vertical drive circuit 1 is switched during the next 1/2 frame.
3-2, the second gate lines g1-2, g in order from the first row.
2-2,... Are sequentially selected.

The rearrangement of the display data in the data source 10 is set, for example, as follows. That is, when n = 2, each display data of 2 × m bits is divided into upper data H for upper m bits and lower data L for lower m bits. And
First, the upper data H1 for one horizontal line of the first line is arranged in the horizontal arrangement order of the pixels 14, and then the upper data H2 for the one horizontal line of the second line is arranged in the arrangement direction of the pixels 14 in the horizontal direction. ..,..., And then the lower data L1, L2,... For one horizontal line are similarly arranged in order from the first horizontal line. Then, the display data is supplied to the horizontal drive circuit 12 in the rearranged order.

Next, the operation of the display device will be described with reference to the timing chart of FIG.

First, from the data source 10, display data in units of m bits obtained by dividing display data of n.times.m bits by n (= 2) is divided into upper data H1, H2,... And lower data L1, L2,. The signals are sequentially supplied to the horizontal drive circuit 12.
The horizontal drive circuit 12 performs the same processing as in the first embodiment, whereby each display data corresponding to m bits is converted into 2 ^m gradation display data in the order of input to the horizontal drive circuit 12, Are input to the lines c1, c2,...

On the other hand, from the first vertical drive circuit 13-1 and the second vertical drive circuit 13-2, selection signals are applied to the first gate lines g1-1, g2-1,... In order from the first row. And then
The selection signals are sequentially applied to the second gate lines g1-2, g2-2,... From the first row. Therefore, first, the upper data H1
Are the first gate line g1-1 in the first row and each column line c.
Are written to the display element 14a-1 connected to 1, c2,..., And then the upper data H2 is connected to the first gate line g2-1 and the column lines c1, c2,. Is written to the display element 14a-1. Similarly, in the same manner,
The higher-order data H3, H
4 is allocated and written. After 1/2 frame period, the lower data L1 is written to the display element 14a-2 connected to the second gate line g1-2 of the first row and each of the column lines c1, c2,... , The display elements 14a connected to the second gate lines g2-2, g3-2,...
The lower data L2, L3, L4 are allocated and written to -2.

As described above, n = 2 display elements 1
In one pixel composed of 4a-1 and 14a-2, the first pixel
As in the embodiment and the second embodiment, the upper data H1,
Are assigned and written to the display element 14a-1 having a large display area, and the lower data L1 and L2 are assigned and written to the display element 14a-2 having a small display area. Therefore, as in the first embodiment and the second embodiment, the display of 2 ^{n * m} = 22 ^{* m} gray scale weighted according to the display characteristics of a pixel is applied to one pixel composed of n display elements. Can be performed.

As described above, also in this display device,
Horizontal drive circuit 1 that outputs an analog signal corresponding to m bits
2, it is possible to perform gradation display corresponding to nxm bits. Therefore, similarly to the first embodiment and the second embodiment, it is possible to increase the number of gradations while suppressing an increase in the occupied area of the horizontal drive circuit 12.

In the third embodiment, similarly to the first embodiment, the rearrangement of the display data by the data source 10 and the wiring state in the display area 11 can be changed as appropriate. Even if
Similar effects can be obtained.

In the display device according to the third embodiment, each of the display elements 14a-1 and 14a is driven by n-system vertical drive circuits.
,..., 14a-n are individually selected. Therefore, for example, the display data may be written only to the display element 14a-1 by operating only the first vertical drive circuit 13-1. When operated in this manner, 2 ^m gray scale display can be performed. At this time, the display data once written can be held in the other display elements 14a-2,.... In this case, 2
Display of ^{n * m-} bit gradation is performed. Then, by operating as described above, power saving of driving of the display device can be achieved.

FIG. 9 is a structural view showing an example of an active matrix type display device according to a fourth embodiment of the present invention, and FIG. 10 is an enlarged view of a main part of FIG.

The display device shown in these figures has a data source 10 ″ for supplying original data of an image, a display area 11 ′ in which a plurality of pixels 14 are arranged, and a plurality of horizontal drive circuits 1.
, 12-n, and a vertical drive circuit 13. However, here, for simplicity of description, a case where pixels 14 of 4 rows × 4 columns are arranged in a matrix is illustrated.

The data source 10 ″, like the data source of the first embodiment, converts n × m bits of display data into m
It is divided into n bits, and rearranged in a predetermined order. However, the display data divided into n is supplied to horizontal drive circuits 12-1, 12-2,..., 12-n of different systems.

For example, when n = 2, each display data of 2 × m bits is divided into upper data H for upper m bits and lower data L for lower m bits. And
First, the upper data H1 of one horizontal line of the first line is arranged in the horizontal arrangement order of the pixels 14, and then the lower data L1 of the same one horizontal line is arranged in the horizontal arrangement order of the pixels 14. Hereinafter, for each horizontal line, the upper data H2
, Lower data L2, upper data H3, lower data L3
,... Are rearranged in the order of the upper data H1,.
, And the lower data L1, L2,... Are separately supplied to horizontal drive circuits 12-1, 12-2 of different systems.

The display area 11 'includes a plurality of columns (for example, four columns) of first column lines c1-1, c2-1, c3-1, and c4-.
Pixels 14 are arranged at intersections of 1 and gate lines g1, g2, g3, and g4 for a plurality of rows (for example, four rows) intersecting them. In this display area 11 ', the second to n-th columns are arranged in parallel with the first column lines c1-1, c2-1, c3-1, c4-1.
Column lines are sequentially wired. For example, when n = 2, the display area 14 includes a first column line c1-1 in the first column.
, The second column line c1-2, the second column first column line c2-1
, The second column line c2-2,...

Each pixel 14 'is composed of n (for example, two) display elements 14a-1 and 14a-2 having the same display area as the first embodiment. However,
The number of display elements that make up one pixel 14 ′ depends on the data source 1
The display data 14a-1 and 14a-2 are the same as the liquid crystal element and the electroluminescence (Electroluminescence) element in the first embodiment. Pixel 14 '
, The gate electrodes of the thin film transistors TFT of the display elements 14a-1 and 14a-2 have the same gate line g1 (g2, g2,
..), And the source electrode of the thin film transistor TFT of the display element 14a-1 having a large display area is connected to the first column line c.
1-1 (c2-1,...), And the source electrode of the display element 14a-2 having a small display area is connected to the second column line c1-2 (c2-
2,…).

The horizontal drive circuits 12-1, 12-2,...
12-n is the same as the number of systems (n
= 2), for example, the first horizontal drive circuit 12-1
And a second horizontal drive circuit 12-2. The first horizontal drive circuit 12-1 and the second horizontal drive circuit 12-2 are configured in the same manner as the horizontal drive circuit of the first embodiment. The first horizontal drive circuit 12-1 is connected to first column lines c1-1, c2-1,..., And the second horizontal drive circuit 12-2 is connected to second column lines c1-2, c2-2,. The first horizontal drive circuit 12-1 is connected to the higher-order data H1, H2,.
Are sequentially sampled, and in synchronization with this, the second
.. Supplied from the data source 10 ″ are sequentially sampled by the horizontal drive circuit 12-2.

The vertical drive circuit 13 is the same as the vertical drive circuit of the first embodiment.

Next, the operation of the display device having the above configuration will be described with reference to FIG.
This will be described with reference to the timing chart of FIG.

First, from the data source 10 ″, n × m
Among the display data in m bits obtained by dividing the bit display data into n (= 2), the upper data H1, H2,... Are sequentially supplied to the first horizontal drive circuit 12-1 and the lower data L1, L2,.
Are sequentially sampled in synchronization with the second horizontal drive circuit 12-2. Then, the first horizontal drive circuit 12-1 and the second
In the horizontal drive circuit 12-2, through the same process as in the first embodiment, these display data are sequentially converted into analog signals of 2 ^m gradation, and the first column lines c1-1,
.. and the second column lines c1-2, c2-2,. That is, each pixel 14 arranged in the horizontal direction
Of the display data corresponding to 2 ^m gradation upper data H1
, H2, ... first column line c1-1, c2-1, are sequentially inputted ... in the lower data L1 synchronization to 2 ^m gradation thereto,
L2,... Are sequentially input to the second column lines c1-2, c2-2,.

On the other hand, selection signals are supplied from the vertical drive circuit 13 in the order of the gate line g1 in the first row, the gate line g2 in the second row, the gate line g3 in the third row, and so on.

For this reason, display data (first higher-order data H1) is input to the first column lines c1-1, c2-1,... From the first horizontal drive circuit 12-1, and at the same time, the second horizontal drive circuit 1
When the display data (first lower data L1) is input to the second column lines c1-2, c2-2,... From 2-2, the display element 14a-1 connected to the gate line g1 in the first row is input to the display element 14a-1. The upper data H1 is written, and the lower data L1 is written to the display element 14a-2 connected to the gate line g1 in the first row.
Next, the first horizontal drive circuit 12-1 and the second horizontal drive circuit 1
When the upper data H2 and the lower data L2 are simultaneously inputted from 2-2, the display element 14a of the pixel 14 'in the second row is input.
-1 is written with the upper data H2, and the pixels 14 'in the second row are written.
The lower data L2 is written to the display element 14a-2.
Thereafter, the upper data H3 and the lower data L3 are respectively assigned to the display elements 14a-1 and 14a-2 of the pixels 14 'in the third row and written, and then the upper data H4 and the lower data L4 are written in the fourth row. The display element 14a- of the pixel 14 'of the eye
1, 14a-2, and are respectively assigned and written.

Therefore, n = 2 display elements 14a-1,
In one pixel constituted by 14a-2, upper data H1, H2,... Are written and assigned to the display element 14a-1 having a large display area, as in the first to third embodiments.
The lower-order data L1, L2,... Are written by being allocated to the display element 14a-2 having a small display area. Therefore, as in the first to third embodiments, 2 ^{n * m} = 22 ^{* m} gray scale display weighted according to the display characteristics of a pixel is applied to one pixel composed of n display elements. Can be performed.

Here, a horizontal drive circuit that outputs an analog signal of 2 × m bits has an occupied area of about 2 times as compared with a horizontal drive circuit that outputs an analog signal of m bits.
^m times. Although this display device includes two horizontal drive circuits 12-1 and 12-2, these horizontal drive circuits output m-bit equivalent analog signals. The area occupied by is reduced to about twice. As a result, it can be said that it is possible to increase the number of gradations while suppressing an increase in the area occupied by the horizontal drive circuit 12.

In the fourth embodiment, the display elements 14a-1 and 14a-2 of the pixels 14 'arranged in the horizontal direction are simultaneously selected by the vertical drive circuit 13. For this reason, it is possible to simultaneously display an analog signal corresponding to nxm bits for one pixel. Therefore, the operation speed of the horizontal drive circuit can be kept low. For example, when n = 2, 1 / １ ／ of the horizontal drive circuit of the first embodiment.
An operation speed of 2 is good.

In the fourth embodiment, upper data H1, H2,... Are sequentially supplied to the first horizontal drive circuit 12-1 and lower data L1, L2 are sequentially supplied to the second horizontal drive circuit 12-2. ,... Are sequentially supplied. However, the supply of display data by the data source 10 ″ is 1
It is possible to appropriately change the wiring state in the display area 11 so that the display data on the upper side is assigned in order from the display element having the larger display area in the pixel. Even when such a change is made, the same effect can be obtained.

[0075]

As described above, according to the present invention,
The display data of n × m bits is divided into n and sequentially converted into analog signals in units of m bits, and the display area is 2 ^{(n−1) * m} : 2
^{(n−2) * m} :...: 2 ^{(n) * m} The display characteristics of the pixel are assigned to one of the n display elements by allocating the display elements to each of the display elements. Can be displayed with 2 ^{n * m} gradations weighted according to. For this reason, it is possible to display 2 ^{n * m} gradations without increasing the number of corresponding bits of the digital-to-analog converter from m bits to n × m bits. It is possible to increase the number of gradations of the display device while keeping the level low. Further, in a display device in which peripheral circuits such as horizontal driving means are mounted on the same substrate as the display area, multi-gradation is achieved while suppressing an increase in a frame in which these peripheral circuits are formed. It becomes possible.

[Brief description of the drawings]

FIG. 1A is a configuration diagram of an active matrix type display device according to a first embodiment of the present invention, and FIG.
FIG. 2 is an enlarged view of a main part of (1).

FIG. 2 is a configuration diagram of a vertical drive circuit of the display device of the first embodiment.

FIG. 3 is a timing chart for explaining the operation of the display device of the first embodiment.

FIG. 4 is a graph illustrating voltage correction by a DAC.

FIG. 5 is a main part configuration diagram showing another example of the first embodiment.

FIG. 6 is a configuration diagram of an active matrix type display device according to a second embodiment of the present invention.

FIG. 7 is a main part configuration diagram of an active matrix type display device according to a third embodiment of the present invention.

FIG. 8 is a timing chart for explaining the operation of the display device of the third embodiment.

FIG. 9 is a configuration diagram of an active matrix type display device according to a fourth embodiment of the present invention.

FIG. 10 is an enlarged view of a main part of FIG. 7;

FIG. 11 is a timing chart for explaining the operation of the display device of the fourth embodiment.

FIG. 12 is a configuration diagram of a conventional active matrix type display device.

[Explanation of symbols]

10, 10 ', 10 "... data source, 11, 11' ...
Display area, 12, 12 '... horizontal drive circuit, 12-1 ... first
Horizontal drive circuit, 12-2 ... second horizontal drive circuit, 12c ... D
AC (digital-to-analog converter), 12d: selector circuit, 13: vertical drive circuit, 13-1: first vertical drive circuit,
13-2: second second vertical drive circuit, 14, 14 ': pixel,
14a-1, 14a-2, 14a-3 ... display elements

 ──────────────────────────────────────────────────続 き Continued on front page F term (reference) 2H093 NA16 NA53 NA54 NA55 NA59 NC21 NC26 NC34 NC49 ND06 ND43 ND49 NE03 5C006 AA12 AA16 AA17 AC24 AF42 AF45 AF83 BB16 BC03 BC06 BC12 BF04 BF05 BF25 FA56 5C080 AA10 BB29 DD03 DD03 JJ02 JJ04 JJ05 JJ06

Claims (31)

[Claims] (1) n × m bits per pixel (n and m are 2
Horizontal drive means having a data source for supplying display data of the above integer), a digital-to-analog converter for converting display data input from the data source into an analog signal of 2 ^m gradation in m-bit units, Area ratio is 2 ^{(n-1) * m} : 2 ^{(n-2) * m} : ...: 2
^{(nn) * m} a display area having pixels consisting of n display elements, and an analog signal output from the digital-to-analog converter for each of the n display elements in units of n for writing. A vertical drive unit for outputting a selection signal. 2. The display device according to claim 1, wherein the analog signal is a signal for correcting a non-linear characteristic of the n-element display element. 3. The display device according to claim 2, wherein the digital-to-analog converter has an input / output characteristic for correcting a non-linear characteristic of the n-element display element. 4. The display device according to claim 1, wherein said horizontal drive means has one digital-to-analog converter for each horizontal pixel, and outputs one analog signal from each digital-to-analog converter. A display device characterized in that the pixel is supplied to each of the pixels in time series n times through the column lines. 5. The display device according to claim 4, wherein said data source inputs said n × m-bit display data to said horizontal drive means in m-bit units. 6. The display device according to claim 4, wherein said horizontal drive means includes a sampling latch having latch units for n × m bits × horizontal pixels, and displays the display data latched by said sampling latch in each horizontal direction. M per pixel
A selector circuit for selecting a bit unit and sequentially inputting to each of the digital-to-analog converters. 7. The display device according to claim 4, wherein said vertical drive means sequentially selects said n display elements in time series. 8. The display device according to claim 4, wherein said vertical drive means is provided in n systems corresponding to said n display elements. 9. The display device according to claim 1, wherein the horizontal driving means is provided in n systems corresponding to the n display elements, and the data source is configured to convert the display data of n × m bits into m. The display device according to claim 1, wherein the data is input to each of the n horizontal driving units in bit units, and the vertical driving unit simultaneously selects the n display elements. 10. The display device according to claim 1, wherein the display element is a liquid crystal element. 11. The display device according to claim 10, wherein the analog signal is a signal for correcting a non-linear characteristic of the n-element display element. 12. The display device according to claim 11, wherein the digital-to-analog converter has an input / output characteristic for correcting a nonlinear characteristic of the n-element display element. 13. The display device according to claim 10, wherein said horizontal drive means includes one digital-to-analog converter for each horizontal pixel, and outputs one analog signal from each digital-to-analog converter. A display device characterized in that the pixel is supplied to each of the pixels in time series n times through the column lines. 14. The display device according to claim 13, wherein said data source inputs said n × m-bit display data to said horizontal drive means in m-bit units. 15. The display device according to claim 13, wherein said horizontal driving means includes a sampling latch having latch units for n × m bits × horizontal pixels, and displays data latched by said sampling latch in each horizontal direction. M per pixel
A selector circuit for selecting a bit unit and sequentially inputting to each of the digital-to-analog converters. 16. The display device according to claim 13, wherein said vertical drive means sequentially selects said n display elements in time series. 17. The display device according to claim 13, wherein said vertical drive means is provided in n systems corresponding to said n display elements. 18. The display device according to claim 10, wherein said horizontal drive means is provided in n systems in correspondence with said n display elements, and said data source is configured to convert said n × m-bit display data into m. A display device, wherein the data is input to each of the n horizontal drive units in bit units, and the vertical drive unit simultaneously selects the n display elements. 19. The display device according to claim 1, wherein the display element is an electroluminescence element. 20. The display device according to claim 19, wherein the analog signal is a signal for correcting a non-linear characteristic of the n-element display element. 21. The display device according to claim 20, wherein the digital-to-analog converter has an input / output characteristic for correcting a nonlinear characteristic of the n-element display element. 22. The display device according to claim 19, wherein said horizontal drive means has one digital-to-analog converter for each horizontal pixel, and outputs one analog signal from each digital-to-analog converter. A display device characterized in that the pixel is supplied to each of the pixels in time series n times through the column lines. 23. The display device according to claim 22, wherein the data source inputs the nxm-bit display data to the horizontal drive unit in m-bit units. 24. The display device according to claim 22, wherein said horizontal drive means includes a sampling latch having latch units for n × m bits × horizontal pixels, and displays data latched by said sampling latch in each horizontal direction. M per pixel
A selector circuit for selecting a bit unit and sequentially inputting to each of the digital-to-analog converters. 25. The display device according to claim 22, wherein said vertical driving means sequentially selects said n display elements in time series. 26. The display device according to claim 22, wherein said vertical drive means is provided in n systems corresponding to said n display elements. 27. The display device according to claim 19, wherein said horizontal drive means is provided in n systems corresponding to said n display elements, and said data source is configured to convert said n × m-bit display data into m. A display device, wherein the data is input to each of the n horizontal drive units in bit units, and the vertical drive unit simultaneously selects the n display elements. 28. A digital-to-analog converter for converting m-bit display data into 2 ^m-level analog signals,
pixels each including n (n is an integer of 2 or more) display elements, and the ratio of the display area of each of the display elements is 2 ^{(n-1) * m} :
2 ^{(n−2) * m} :...: 2 ^{(nn) * m} , a display device driving method, wherein display data of n × m bits is divided into n units of m bits, and Each of the n-divided display data is converted into an analog signal of 2 ^m gradation by the digital-to-analog converter, and n display elements constituting the pixel are transmitted from the upper side of the analog signal to the n display elements. A method for driving a display device, wherein a display element is sequentially allocated to display elements having larger display areas and displayed. 29. The display device driving method according to claim 28, wherein the display data is converted into an analog signal for correcting nonlinear characteristics of the n display elements. Drive method. 30. The display device driving method according to claim 28, wherein the input of analog signals to the n display elements is sequentially performed in a time series through a single column line. Drive method. 31. The method of driving a display device according to claim 28, wherein the input of the analog signal to the n display elements is performed simultaneously through a plurality of column lines.