JP4542633B2

JP4542633B2 - Load drive circuit and liquid crystal display device

Info

Publication number: JP4542633B2
Application number: JP12751298A
Authority: JP
Inventors: 木良朗青
Original assignee: Toshiba Mobile Display Co Ltd
Current assignee: Japan Display Central Inc
Priority date: 1998-05-11
Filing date: 1998-05-11
Publication date: 2010-09-15
Anticipated expiration: 2018-05-11
Also published as: JPH11327515A

Description

【０００１】
【発明の属する技術分野】
外部からの入力信号を駆動負荷に供給する回路に関し、例えば、駆動回路一体型の液晶表示装置の信号線駆動回路などを対象とする。
【０００２】
【従来の技術】
液晶表示装置は、信号線および走査線がマトリクス状に配設された画素アレイ部と、信号線および走査線を駆動する駆動回路とを有する。従来は、画素アレイ部と駆動回路とを別個の基板に形成していたため、液晶表示装置のコストダウンを図ることが困難で、また、液晶表示装置の外形寸法に対する実画面サイズの比率を高めることも難しかった。
【０００３】
【発明が解決しようとする課題】
最近、ガラス基板上にポリシリコンを材料としてＴＦＴ(Thin Film Transistor)を形成する製造技術が進歩してきたため、この技術を利用することにより、画素アレイ部と駆動回路とを同一基板上に形成することも可能になった。
【０００４】
しかしながら、ガラス基板上に均一な特性のポリシリコンＴＦＴを形成することは現状では困難であり、しきい値電圧や移動度などがばらついてしまう。したがって、仮に画素アレイ部と駆動回路を同一基板上に形成したとしても、ＴＦＴの特性のばらつきにより輝度むら等の表示品質の低下が起きるおそれがあり、また、消費電力も増えてしまう。
【０００５】
本発明は、このような点に鑑みてなされたものであり、その目的は、駆動負荷に供給される電圧が、トランジスタの特性のばらつきの影響により変動しないようにした負荷駆動回路を提供することにある。
【０００６】
本発明の一態様によれば、第１および第２の切換手段と、
キャパシタと、
入力電圧が所定のしきい値電圧を越えると出力論理が反転する論理回路と、
前記第１の切換手段のオン・オフを制御する切換制御手段と、を備えた負荷駆動回路であって、
前記第１の切換手段の第１端に駆動負荷が接続され、
前記第１の切換手段がオフのときに前記第１の切換手段の第２端と前記キャパシタの第１端とに入力信号が供給され、
前記キャパシタの第２端は前記論理回路の入力端子に接続され、
前記切換制御手段は前記第１の切換手段を所定期間オフし、その後、前記第１の切換手段をオンし、
前記第２の切換手段は前記論理回路の出力に応じて前記駆動負荷と基準電圧端子とを接続するか否かを切換制御することを特徴とする負荷駆動回路が提供される。
【０００７】
本発明の一態様によれば、第１および第２の切換手段と、
キャパシタと、
入力電圧が所定のしきい値電圧を越えると出力論理が反転する論理回路と、
前記第１の切換手段のオン・オフを制御する切換制御手段と、を備えた負荷駆動回路であって、
前記第１の切換手段の第１端に駆動負荷が接続され、
前記第１の切換手段がオフのときに前記第１の切換手段の第２端と前記キャパシタの第１端とに入力信号が供給され、
前記キャパシタの第２端は前記論理回路の入力端子に接続され、
前記切換制御手段は前記第１の切換手段を、前記キャパシタの第２端の電圧が安定するまでの所定期間オフし、その後、前記第１の切換手段をオンし、
前記第２の切換手段は前記論理回路の出力に応じて前記駆動負荷と基準電圧端子とを接続するか否かを切換制御することを特徴とする負荷駆動回路が提供される。
【０００８】
本発明の一態様によれば、第１、第２、第３、第４、第５および第６の切換手段と、
第１および第２のキャパシタと、
入力電圧が所定のしきい値電圧を越えると出力論理が反転する論理回路と、
前記第１、第３および第４の切換手段のオン・オフを制御する切換制御手段と、を備えた負荷駆動回路であって、
前記第１の切換手段の第１端に駆動負荷が接続され、
前記第１の切換手段がオフのときに前記第１の切換手段の第２端、前記第１のキャパシタの第１端、および前記第２のキャパシタの第１端のそれぞれに入力信号が供給され、
前記第１のキャパシタの第２端は、前記第３の切換手段の第１端と前記論理回路の入力端子とに接続され、
前記第３の切換手段の第２端は、第１の電圧端子に接続され、
前記第２のキャパシタの第２端は、前記第４の切換手段の第１端に接続され、
前記第４の切換手段の第２端は、第２の電圧端子に接続され、
前記切換制御手段は、前記入力信号に応じた電荷が前記第１および第２のキャパシタに蓄積されるように前記第１の切換手段をオフして前記第３および第４の切換手段をオンする第１の切換制御を行い、その後、前記第１、第３および第４の切換手段をオフする第２の切換制御を行い、その後、前記第１のキャパシタの第２端の電圧が安定した後に前記第１の切換手段をオンして前記第３および第４の切換手段をオフする第３の切換制御を行い、
前記第５および第６の切換手段は前記論理回路の出力に応じて前記第１および第２のキャパシタを相反的に充放電させ、
前記第２の切換手段は前記論理回路の出力に応じて前記駆動負荷と基準電圧端子とを接続するか否かを切換制御することを特徴とする負荷駆動回路が提供される。
【０００９】
本発明の一態様によれば、第１、第２、第３、第４および第５の切換手段と、
第１および第２のキャパシタと、
入力電圧が所定のしきい値電圧を越えると出力論理が反転する論理回路と、
前記第１、第３および第４の切換手段のオン・オフを制御する切換制御手段と、を備えた負荷駆動回路であって、
前記第１の切換手段の第１端に駆動負荷が接続され、
前記第１の切換手段がオフのときに前記第１の切換手段の第２端、前記第１のキャパシタの第１端、および前記第２のキャパシタの第１端のそれぞれに入力信号が供給され、
前記第１のキャパシタの第２端は、前記第３の切換手段の第１端と前記論理回路の入力端子とに接続され、
前記第３の切換手段の第２端は、第１の電圧端子に接続され、
前記第２のキャパシタの第２端は、前記第４の切換手段の第１端に接続され、
前記第４の切換手段の第２端は、第２の電圧端子に接続され、
前記切換制御手段は、前記入力電圧に応じた電荷が前記第１および第２のキャパシタに蓄積されるように前記第１の切換手段をオフして前記第３および第４の切換手段をオンする第１の切換制御を行い、その後、前記第１、第３および第４の切換手段をオフする第２の切換制御を行い、その後、前記第１のキャパシタの第２端の電圧が安定した後に前記第１の切換手段をオンして前記第３および第４の切換手段をオフする第３の切換制御を行い、
前記第５の切換手段は前記論理回路の出力に応じて前記第１および第２のキャパシタの各第２端を互いに短絡するか否かを切換制御し、
前記第２の切換手段は前記論理回路の出力に応じて前記駆動負荷と基準電圧端子とを接続するか否かを切換制御することを特徴とする負荷駆動回路が提供される。
【００１０】
請求項１の発明を、例えば図１，２に対応づけて説明すると、「第１の切換手段」は図１のスイッチSW１に、「第２の切換手段」はアナログスイッチＱ１に、「キャパシタ」はキャパシタＣ１に、「論理回路」は論理回路１３に、「切換制御手段」は図２のスイッチ切換制御回路１２に、「駆動負荷」は信号線Ｓに、それぞれ対応する。
【００１１】
請求項２の発明を、例えば図２，６に対応づけて説明すると、「第１の切換手段」は図６のスイッチSW１に、「第２の切換手段」はアナログスイッチＱ１に、「第３の切換手段」はスイッチSW５に、「第４の切換手段」はスイッチSW６に、「第５の切換手段」はトランジスタＱ２に、「第６の切換手段」はトランジスタＱ３に、「第１のキャパシタ」はキャパシタＣ１に、「第２のキャパシタ」はキャパシタＣ３に、「論理回路」は論理回路１３に、「第１の電圧端子」は０Ｖの端子に、「第２の電圧端子」は10Ｖの端子に、それぞれ対応する。
【００１２】
請求項３の発明を、例えば図８に対応づけて説明すると、「第１の切換手段」は図８のスイッチSW１に、「第２の切換手段」はアナログスイッチＱ１に、「第３の切換手段」はスイッチSW５に、「第４の切換手段」はスイッチSW６に、「第５の切換手段」はトランジスタＱ４に、「第１のキャパシタ」はキャパシタＣ１に、「第２のキャパシタ」はキャパシタＣ３に、「論理回路」は論理回路１３に、「第１の電圧端子」は０Ｖの端子に、「第２の電圧端子」は10Ｖの端子に、それぞれ対応する。
【００１３】
請求項４の「第７の切換手段」は、図１，６，８のスイッチSW３に対応する。
【００１４】
請求項５の「第８の切換手段」は、図１，６，８のスイッチSW２に対応する。
【００１５】
請求項６の「第９の切換手段」は、図１，６，８のスイッチSW４に対応する。
【００１６】
請求項９の発明を、例えば図２，３に対応づけて説明すると、「画素アレイ部」は図３の画素アレイ部２に、「走査線駆動回路」は走査線駆動回路４に、「信号線駆動回路」は信号線駆動回路３に、「第１の負荷駆動回路」は負荷駆動部１１ａに、「第２の負荷駆動回路」は負荷駆動部１１ｂに、それぞれ対応する。
【００１７】
【発明の実施の形態】
以下、本発明に係る負荷駆動回路について、図面を参照しながら具体的に説明する。以下では、本発明に係る負荷駆動回路を、液晶表示装置の信号線駆動回路に適用した例を説明する。
【００１８】
（第１の実施形態）
図１は本発明に係る負荷駆動回路の主要部の構成を示す第１の実施形態の回路図、図２は負荷駆動回路全体の構成を示す概略ブロック図、図３は図２の負荷駆動回路を信号線駆動回路として用いた液晶表示装置の概略ブロック図である。
【００１９】
図３に示す液晶表示装置は、信号線Ｓ1〜Ｓnおよび走査線Ｇ1〜Ｇnが縦横に形成されこれらの交点付近に画素表示用のＴＦＴ１が列設された画素アレイ部２と、各信号線Ｓ1〜Ｓnを駆動する信号線駆動回路３と、各走査線Ｇ1〜Ｇnを駆動する走査線駆動回路４とを備える。
【００２０】
図３の液晶表示装置を構成する各部は、同一基板上に形成され、信号線駆動回路３や走査線駆動回路４を構成するトランジスタは、画素表示用のＴＦＴ１と同じ製造プロセスで形成される。
【００２１】
信号線駆動回路３は、図２に示す負荷駆動回路を用いて構成される。図２の負荷駆動回路は、信号線のそれぞれに対応して設けられる正極性および負極性用の負荷駆動部１１ａ，１１ｂと、各負荷駆動部１１ａ，１１ｂ内の各種スイッチを切換制御するスイッチ切換制御回路１２とを有する。
【００２２】
正極性用の負荷駆動部１１ａと負極性用の負荷駆動部１１ｂを別々に設ける理由は、１画素単位、または１水平ライン単位、または１フレーム単位で信号線の駆動電圧の極性を切り換えるようにするためである。
【００２３】
図１は正極性用の負荷駆動部１１ａの回路図である。負荷駆動部１１ａのそれぞれは、図１に示すように、スイッチSW１〜SW４と、PMOSトランジスタからなるアナログスイッチＱ１と、インバータを２段縦続接続した論理回路１３と、キャパシタＣ１とを有する。負荷駆動部１１ａ，１１ｂにより駆動される信号線Ｓには、図３に示すように、画素表示用のＴＦＴ、液晶容量および補助容量等が接続されており、図１では簡略化のため、信号線Ｓの負荷を等価的に抵抗ＲとキャパシタＣ２とで表している。
【００２４】
スイッチSW１，SW２の一端は信号線Ｓに接続され、スイッチSW１の他端はスイッチSW３の一端とキャパシタＣ１の一端に接続され、スイッチSW３の他端には入力映像信号Ｖinが供給される。キャパシタＣ１の他端は論理回路１３の入力端子に接続され、論理回路１３の出力端子はアナログスイッチＱ１のゲート端子に接続される。アナログスイッチＱ１のソース端子には第１の電圧ＶDD（例えば、10Ｖ）が印加され、そのドレイン端子にはスイッチSW２の他端が接続される。スイッチSW４の一端には信号線Ｓが接続され、スイッチSW４の他端には第２の電圧ＶD（例えば、５Ｖ）が印加される。スイッチSW１〜SW４は、図２に示したスイッチ切換制御回路１２により切換制御される。
【００２５】
図１では、スイッチSW１とキャパシタＣ１との接続点をａ、キャパシタＣ１と論理回路１３との接続点をｂ、論理回路１３とアナログスイッチＱ１との接続点をｃ、スイッチSW１，SW２の接続点をｄとしている。
【００２６】
図４は図１の負荷駆動回路１１ａ内の各部のタイミング図であり、以下、このタイミング図を用いて図１の回路の動作を説明する。まず、時刻Ｔ１〜Ｔ２の期間内に、スイッチ切換制御回路１２は、スイッチSW１〜SW３をオフにしてスイッチSW４をオンする。これにより、信号線Ｓの電圧（図１のｄ点）は、第２の電圧ＶDと同じ電圧（例えば５Ｖ）になる。
【００２７】
次に、時刻Ｔ２〜Ｔ３の期間内に、スイッチ切換制御回路１２は、スイッチSW３のみをオンする。これにより、図１のａ点の電圧は入力映像信号Ｖinの電圧に等しくなる。図４では、入力映像信号Ｖinの電圧が7.5Ｖである例を示している。この期間内は、信号線Ｓ（図１のｄ点）の電圧は５Ｖになる。
【００２８】
ここで、論理回路１３の入力端子（図１のｂ点）の電圧が、論理回路１３のしきい値電圧より若干高い電圧（例えば、５Ｖ）であると仮定すると、論理回路１３の出力端子（図１のｃ点）の電圧は電源電圧とほぼ等しい10Ｖになる。したがって、この期間内はアナログスイッチＱ１はオフになる。
【００２９】
次に、時刻Ｔ３以降は、スイッチ切換制御回路１２は、スイッチSW１，SW２をオンして、スイッチSW３，SW４をオフする。時刻Ｔ３の時点では、図１のａ点は7.5Ｖであるのに対し、ｄ点は５Ｖであるため、スイッチSW１がオンすると、ａ点の電圧がｄ点に引きづられて低下する。これに応じて、キャパシタＣ１の他端側である図１のｂ点の電圧も低下し、論理回路１３の出力が反転してローレベル（例えば、０Ｖ）になる。これにより、アナログスイッチＱ１がオンし、第１の電圧ＶDDがアナログスイッチＱ１とスイッチSW２を介して信号線Ｓに供給され、信号線Ｓ（図１のｄ点）の電圧が徐々に上昇する。
【００３０】
信号線Ｓの電圧が上昇すると、それに応じて図１のａ点、ｂ点の電圧も上昇する。やがて、時刻Ｔ４になると、信号線Ｓの電圧が入力映像信号Ｖinの電圧である7.5Ｖに等しくなり、また、論理回路１３の入力電圧が論理回路１３のしきい値電圧（５Ｖ）を越え、論理回路１３の出力が再び反転してハイレベル（例えば、10Ｖ）になる。これにより、アナログスイッチＱ１がオフする。
【００３１】
アナログスイッチＱ１がオフすると、信号線Ｓ上の容量Ｃ２は徐々に放電して図１のｄ点の電圧は下がるが、論理回路１３の入力端子（図１のｂ点）の電圧が論理回路１３のしきい値電圧を下回った時点で再びアナログスイッチＱ１がオンして、図１のｄ点の電圧は再び上昇する。このような動作を繰り返すことにより、信号線Ｓ（図１のｄ点）の電圧は入力映像信号Ｖinの電圧である7.5Ｖに保持される。
【００３２】
図５は負極性用の負荷駆動部１１ｂの詳細構成を示す回路図である。図５に示すように、負荷駆動部１１ｂは、アナログスイッチＱ１がｎ型である点と、アナログスイッチＱ１のソース電極が接地されている点とが図１の負荷駆動部１１ａと異なり、その他の構成は同じである。
【００３３】
このように、第１の実施形態は、図１に示すスイッチSW１，SW2と、キャパシタＣ１と、論理回路１３と、アナログスイッチＱ１とで帰還ループを構成し、信号線Ｓの電圧が入力映像信号Ｖinの電圧よりも低くなれば、アナログスイッチＱ１をオンして信号線Ｓの電圧を引き上げる制御を行い、信号線Ｓの電圧が入力映像信号Ｖinの電圧よりも高くなれば、アナログスイッチＱ１をオフして信号線Ｓの電圧を引き下げる制御を行う。これにより、信号線Ｓの電圧は入力映像信号Ｖinの電圧と略等しい電圧に設定される。
【００３４】
また、第１の実施形態では、信号線駆動回路３内の論理回路１３の入力電圧を論理回路１３のしきい値電圧に略等しい電圧に予め設定した後に、信号線駆動回路３内に入力映像信号Ｖinを供給するため、信号線駆動回路３を構成するトランジスタの特性にばらつきがあっても、信号線Ｓの電圧はその影響を受けなくなる。
【００３５】
（第２の実施形態）
図１に示す論理回路１３は、トランジスタを組み合わせて構成されるため、トランジスタのしきい値や移動度のばらつきにより、論理回路１３の出力レベルが変化して回路が正常動作しなくなるおそれがある。
【００３６】
そこで、以下に示す第２の実施形態は、論理回路１３の特性のばらつきを相殺することを特徴とする。
【００３７】
図６は負荷駆動回路の第２の実施形態の回路図であり、第１の実施形態と同様に、液晶表示装置の信号線駆動回路３として用いられるものである。図６の回路は、図１と同様に、スイッチSW１〜SW４と、PMOSトランジスタからなるアナログスイッチＱ１と、インバータを２段縦続接続した論理回路１３と、キャパシタＣ１とを有する。この他、図６の回路は、キャパシタＣ３とスイッチSW５〜SW７とPMOSトランジスタＱ２，Ｑ３とを有する。
【００３８】
キャパシタＣ１，Ｃ３の各一端とスイッチSW１，SW３の各一端は互いに接続される。キャパシタＣ１の他端には、論理回路１３の入力端子とスイッチSW５の一端が接続され、スイッチSW５の他端は第３の電圧（例えば、0Ｖ）に設定される。キャパシタＣ３の他端にはスイッチSW６の一端が接続され、スイッチSW６の他端には第４の電圧（例えば、10Ｖ）が印加される。
【００３９】
論理回路１３の出力端子にはスイッチSW７の一端とアナログスイッチＱ１のゲート端子が接続され、スイッチSW７の他端にはトランジスタＱ２，Ｑ３の各ゲート端子が接続される。トランジスタＱ２のソース／ドレイン電極のうち一方はキャパシタＣ１とスイッチSW５との間に接続され、他方はＣＮ端子に接続される。
トランジスタＱ３のソース／ドレイン電極のうち一方はキャパシタＣ３とスイッチSW６との間に接続され、他方はＣＮＲ端子に接続される。
【００４０】
図６では、スイッチSW１，SW３とキャパシタＣ１，Ｃ３との接続点をａ、キャパシタＣ１と論理回路１３との接続点をｂ、論理回路１３とアナログスイッチＱ１との接続点をｃ、スイッチSW１，SW２の接続点をｄ、キャパシタＣ３とスイッチSW６との接続点をｅとしている。
【００４１】
図７は図６の負荷駆動回路内の各部のタイミング図であり、以下、このタイミング図を用いて図６の回路の動作を説明する。
【００４２】
まず、時刻Ｔ11〜Ｔ12の期間内に、スイッチ切換制御回路１２は、スイッチSW４のみをオンする。これにより、信号線Ｓの電圧は第２の電圧ＶDと同じ電圧（例えば５Ｖ）になる。
【００４３】
次に、時刻Ｔ12〜Ｔ13の期間内に、スイッチ切換制御回路１２は、スイッチSW１，SW２，SW４をオフしてスイッチSW３，SW５〜SW７をオンする。これにより、図６のａ点の電圧は入力映像信号Ｖinの電圧になる。図７では、入力映像信号Ｖinの電圧が7.5Ｖである例を示している。スイッチSW１がオフであるため、信号線（図６のｄ点）の電圧は５Ｖになる。また、スイッチSW５，SW６がオンであるため、キャパシタＣ１とスイッチSW５との接続点（図６のｂ点）は０Ｖに、キャパシタＣ２とスイッチSW６との接続点（図６のｅ点）は10Ｖになる。したがって、論理回路１３の出力もローレベル（約０Ｖ）になり、アナログスイッチＱ１とトランジスタＱ２，Ｑ３がいずれもオンする。
【００４４】
次に、時刻Ｔ13〜Ｔ15の期間内に、スイッチ切換制御回路１２は、スイッチSW７のみをオンする。また、時刻Ｔ13以降は、ＣＮ端子を10Ｖに、ＣＮＲ端子は０Ｖに設定する。なお、ＣＮ端子とＣＮＲ端子の電圧設定は、スイッチ切換制御回路１２か、あるいは他の回路ブロックで行われる。
【００４５】
時刻Ｔ13の時点では論理回路１３の出力はローレベルであるため、トランジスタＱ２，Ｑ３はともにオンし、キャパシタＣ１とスイッチSW５の接続点（図６のｂ点）の電圧は徐々に上昇し、キャパシタＣ３とスイッチSW６の接続点（図６のｅ点）の電圧は徐々に低下する。
【００４６】
時刻Ｔ14になると、図６のｂ点の電圧が論理回路１３のしきい値電圧（例えば、5.5Ｖ）を越え、論理回路１３の出力はハイレベル（約10Ｖ）になり、アナログスイッチＱ１とトランジスタＱ２，Ｑ３はともにオフする。このため、時刻Ｔ14〜Ｔ15の期間内は、図６のｂ点の電圧は論理回路１３のしきい値電圧（例えば、5.5Ｖ）になり、図６のｅ点の電圧は所定電圧（例えば、4.5Ｖ）になる。
【００４７】
すなわち、論理回路１３の入力電圧が論理回路１３のしきい値電圧よりも高くなればトランジスタＱ２がオフして論理回路１３の入力電圧が下がり、逆に、論理回路１３の入力電圧が論理回路１３のしきい値電圧より低くなればトランジスタＱ２がオンして論理回路１３の入力電圧が上がる。このような制御により、論理回路１３の入力端子（図６のｂ点）の電圧は、論理回路１３のしきい値電圧に等しくなるように制御される。
【００４８】
次に、時刻Ｔ15になると、スイッチ切換制御回路１２は、スイッチSW１，SW２，SW７をオンし、スイッチSW３，SW４，SW５，SW６をオフする。時刻Ｔ15の時点では、信号線Ｓの電圧は５Ｖで、図６のａ点の電圧は7.5Ｖであるため、信号線Ｓの電圧の影響を受けて図６のａ点の電圧が低下する。これにより、論理回路１３の入力端子（図６のｂ点）の電圧も低下して論理回路１３のしきい値電圧以下になり、論理回路１３の出力はローレベル（約０Ｖ）になる。よって、アナログスイッチＱ１がオンし、信号線Ｓ（図６のｄ点）の電圧が上昇し、それに応じて、図６のａ点、ｂ点およびｅ点の電圧も上昇する。
【００４９】
次に、時刻Ｔ16になると、論理回路１３の入力端子（図６のｂ点）の電圧が論理回路１３のしきい値電圧を越え、論理回路１３の出力端子はハイレベル（約10Ｖ）になる。これにより、アナログスイッチＱ１がオフして信号線Ｓ（図６のｄ点）の電圧は容量Ｃ２の放電により徐々に低下するが、ある程度まで低下すると、再びアナログスイッチＱ１がオンして信号線Ｓの電圧は再び上昇する。
【００５０】
このような動作を繰り返すことにより、信号線Ｓ（図６のｄ点）は入力映像信号Ｖinの電圧（約7.5Ｖ）に保持される。
【００５１】
なお、信号線Ｓの電圧が略一定になった以降（時刻Ｔ18以降）は、スイッチSW７をオフしてもよい。
【００５２】
このように、図６の回路は、互いに逆方向に充放電を行う２個のキャパシタＣ１，Ｃ３を設け、論理回路１３のしきい値電圧がばらついても、これらキャパシタＣ１，Ｃ３の接続点ａの電圧が変動しないようにしたため、入力映像信号Ｖinを信号線Ｓに供給する前に、論理回路１３の入力電圧を論理回路１３のしきい値電圧に略等しくすることができる。
【００５３】
また、第１の実施形態と同様に、信号線Ｓの電圧が入力映像信号Ｖinの電圧よりも高くなると、アナログスイッチＱ１をオフして信号線Ｓの電圧を引き下げ、信号線Ｓの電圧が入力映像信号Ｖinの電圧よりも低くなると、アナログスイッチＱ１をオンして信号線Ｓの電圧を引き上げるような制御を行うため、信号線Ｓの電圧を入力映像信号Ｖinの電圧に略等しくすることができる。
【００５４】
（第３の実施形態）
第３の実施形態は、第２の実施形態（図６）の回路を簡略化したものである。
図８は負荷駆動回路の第３の実施形態の回路図であり、第１および第２の実施形態と同様に、例えば図３に示す液晶表示装置の信号線駆動回路３として用いられるものである。
【００５５】
図８の回路は、図６の回路のトランジスタＱ２，Ｑ３の代わりに、トランジスタＱ４を設けたことを特徴とする。トランジスタＱ４のソース／ドレイン電極のうち一方はキャパシタＣ１とスイッチSW５との間に接続され、他方はキャパシタＣ３とスイッチSW６との間に接続される。また、トランジスタＱ４のゲート端子はスイッチSW７の一端に接続される。
【００５６】
図８では、スイッチSW１，SW３とキャパシタＣ１，Ｃ３との接続点をａ、キャパシタＣ１と論理回路１３との接続点をｂ、論理回路１３とアナログスイッチＱ１との接続点をｃ、スイッチSW１，SW２の接続点をｄ、キャパシタＣ３とスイッチSW６との接続点をｅとしている。
【００５７】
図９は図８の負荷駆動回路内の各部のタイミング図であり、以下、このタイミング図を用いて図８の回路の動作を説明する。
【００５８】
まず、時刻Ｔ21〜Ｔ22の期間内に、スイッチ切換制御回路１２はスイッチSW４のみをオンする。これにより、信号線Ｓの電圧は第２の電圧ＶDと同じ電圧（例えば５Ｖ）になる。
【００５９】
次に、時刻Ｔ22〜23の期間内に、スイッチ切換制御回路１３はスイッチSW１，SW２，SW４をオフしてスイッチSW３，SW５〜SW７をオンする。これにより、図８のａ点の電圧は入力映像信号Ｖinの電圧（例えば、7.5Ｖ）になる。この期間内は、スイッチSW１がオフであるため、信号線Ｓ（図８のｄ点）の電圧は５Ｖになる。また、スイッチSW６，SW７がオンであるため、図８のｂ点は０Ｖに、ｅ点は10Ｖになる。したがって、論理回路１３の出力もローレベル（約０Ｖ）になり、トランジスタＱ４はオン状態になる。
【００６０】
次に、時刻Ｔ23〜Ｔ25の期間内に、スイッチ切換制御回路１３はスイッチSW７のみをオンする。このとき、トランジスタＱ４はオン状態であるため、図８のｂ点とｅ点が短絡し、両電圧は一致する方向に変化する。具体的には、ｂ点の電圧は０Ｖから徐々に上昇し、ｅ点の電圧は10Ｖから徐々に低下する。
【００６１】
時刻Ｔ24になると、論理回路１３の入力端子（図８のｂ点）の電圧が論理回路１３のしきい値電圧を越え、論理回路１３の出力電圧がハイレベル（例えば、10Ｖ）に変化する。これにより、トランジスタＱ４がオフし、ｂ点の電圧はそれ以上には上昇しなくなる。
【００６２】
その後、キャパシタＣ１の放電によりｂ点の電圧が低下し、やがて論理回路１３のしきい値電圧以下になると、再び論理回路１３の出力がローレベル（例えば、０Ｖ）に変化し、トランジスタＱ４が再度オンして図８のｂ点の電圧が上昇する。このような動作を繰り返すことにより、論理回路１３の入力端子（図８のｂ点）の電圧は論理回路１３のしきい値電圧に略等しくなる。
【００６３】
次に、時刻Ｔ25になると、スイッチ切換制御回路１３はスイッチSW１，SW２，SW７をオンし、スイッチSW３，SW４，SW５，SW６をオフする。これにより、図８のａ点，ｂ点の電圧がいったん下がってアナログスイッチＱ１がオンし、信号線Ｓの電圧は徐々に上昇する。その後、時刻Ｔ26になると、ｂ点の電圧が論理回路１３のしきい値電圧を越えて論理回路１３の出力が反転してハイレベル（例えば、10Ｖ）になる。これにより、アナログスイッチＱ１がオフして信号線Ｓの電圧はそれ以上には上昇しなくなる。
【００６４】
このように、第３の実施形態は、キャパシタＣ１，Ｃ３の各一端をトランジスタＱ４のソース／ドレイン電極にそれぞれ接続し、トランジスタＱ４のゲート電極を論理回路１３の出力電圧に応じて制御するようにしたため、図８のｂ点の電圧とｅ点の電圧を相反的に制御でき、第２の実施形態と同様に、論理回路１３の入力端子（図８のｂ点）の電圧を論理回路１３のしきい値電圧に略等しくすることができる。
【００６５】
上述した第１〜第３の実施形態では、本発明に係る負荷駆動回路を液晶表示装置内の信号線駆動回路３に適用した例を説明したが、本発明は信号線駆動回路３以外にも幅広く適用することができる。
【００６６】
また、図１等に示す各種スイッチは、トランスファーゲートやアナログスイッチを用いて構成することができる。また、図１等に示すスイッチSW２やSW４は、必ずしも必要ではなく、省略しても構わない。
【００６７】
また、図１等では、インバータを２段縦続接続して論理回路１３を構成する例を説明したが、トランジスタを組み合わせて構成されるものであれば、論理回路１３の内部構成に特に制限はない。
【００６８】
【発明の効果】
以上詳細に説明したように、本発明によれば、論理回路の入力端子の電圧を論理回路のしきい値電圧に略等しく設定した後に、外部からの入力信号を駆動負荷に供給するため、論理回路のしきい値がばらついても、駆動負荷に供給される電圧がその影響を受けなくなる。したがって、本発明を例えば液晶表示装置の信号線駆動回路に適用した場合には、輝度むらのない表示品質に優れた駆動回路一体型の液晶表示装置が得られる。
【図面の簡単な説明】
【図１】負荷駆動回路の主要部の構成を示す第１の実施形態の回路図。
【図２】負荷駆動回路全体の構成を示す概略ブロック図。
【図３】図２の負荷駆動回路を信号線駆動回路として用いた液晶表示装置の概略ブロック図。
【図４】図１の負荷駆動回路内の各部のタイミング図。
【図５】負極性用の負荷駆動部の詳細構成を示す回路図。
【図６】負荷駆動回路の第２の実施形態の回路図。
【図７】図６の負荷駆動回路の各部のタイミング図。
【図８】負荷駆動回路の第３の実施形態の回路図。
【図９】図８の負荷駆動回路内の各部のタイミング図。
【符号の説明】
１ＴＦＴ
２画素アレイ部
３信号線駆動回路
４走査線駆動回路
１１ａ，１１ｂ負荷駆動部
１２スイッチ切換制御回路
１３論理回路
Ｑ１アナログスイッチ
Ｑ２，Ｑ３トランジスタ
SW１〜SW４スイッチ[0001]
BACKGROUND OF THE INVENTION
The circuit for supplying an input signal from the outside to the driving load is, for example, a signal line driving circuit of a liquid crystal display device integrated with a driving circuit.
[0002]
[Prior art]
The liquid crystal display device includes a pixel array portion in which signal lines and scanning lines are arranged in a matrix, and a drive circuit that drives the signal lines and the scanning lines. Conventionally, since the pixel array portion and the drive circuit are formed on separate substrates, it is difficult to reduce the cost of the liquid crystal display device, and the ratio of the actual screen size to the external dimensions of the liquid crystal display device is increased. It was also difficult.
[0003]
[Problems to be solved by the invention]
Recently, manufacturing technology for forming TFT (Thin Film Transistor) using polysilicon as a material on a glass substrate has advanced. By using this technology, the pixel array part and the drive circuit can be formed on the same substrate. Also became possible.
[0004]
However, it is difficult to form polysilicon TFTs with uniform characteristics on a glass substrate at present, and the threshold voltage and mobility vary. Therefore, even if the pixel array portion and the drive circuit are formed on the same substrate, there is a risk that display quality such as luminance unevenness may be deteriorated due to variations in TFT characteristics, and power consumption also increases.
[0005]
The present invention has been made in view of these points, and an object of the present invention is to provide a load drive circuit in which the voltage supplied to the drive load does not fluctuate due to the influence of variations in transistor characteristics. It is in.
[0006]
According to one aspect of the invention, first and second switching means;
A capacitor;
A logic circuit in which the output logic is inverted when the input voltage exceeds a predetermined threshold voltage;
A load driving circuit comprising: a switching control means for controlling on / off of the first switching means;
A driving load is connected to the first end of the first switching means;
When the first switching means is off, an input signal is supplied to the second end of the first switching means and the first end of the capacitor;
A second end of the capacitor is connected to an input terminal of the logic circuit;
The switching control means turns off the first switching means for a predetermined period, and then turns on the first switching means,
A load driving circuit is provided, wherein the second switching means performs switching control as to whether or not to connect the driving load and a reference voltage terminal according to the output of the logic circuit.
[0007]
According to one aspect of the invention, first and second switching means;
A capacitor;
A logic circuit in which the output logic is inverted when the input voltage exceeds a predetermined threshold voltage;
A load driving circuit comprising: a switching control means for controlling on / off of the first switching means;
A driving load is connected to the first end of the first switching means;
When the first switching means is off, an input signal is supplied to the second end of the first switching means and the first end of the capacitor;
A second end of the capacitor is connected to an input terminal of the logic circuit;
The switching control means switches the first switching means, Until the voltage at the second end of the capacitor is stabilized. Turn off for a predetermined period, then turn on the first switching means,
A load driving circuit is provided, wherein the second switching means performs switching control as to whether or not to connect the driving load and a reference voltage terminal according to the output of the logic circuit.
[0008]
According to one aspect of the invention, first, second, third, fourth, fifth and sixth switching means;
First and second capacitors;
A logic circuit in which the output logic is inverted when the input voltage exceeds a predetermined threshold voltage;
A switching control means for controlling on / off of the first, third and fourth switching means, and a load driving circuit comprising:
A driving load is connected to the first end of the first switching means;
When the first switching means is off, input signals are supplied to the second end of the first switching means, the first end of the first capacitor, and the first end of the second capacitor, respectively. ,
A second end of the first capacitor is connected to a first end of the third switching means and an input terminal of the logic circuit;
A second end of the third switching means is connected to the first voltage terminal;
A second end of the second capacitor is connected to a first end of the fourth switching means;
A second end of the fourth switching means is connected to a second voltage terminal;
The switching control means turns off the first switching means and turns on the third and fourth switching means so that a charge corresponding to the input signal is accumulated in the first and second capacitors. Performing a first switching control, and then performing a second switching control to turn off the first, third and fourth switching means, and then After the voltage at the second end of the first capacitor is stabilized Performing a third switching control for turning on the first switching means and turning off the third and fourth switching means;
The fifth and sixth switching means charge and discharge the first and second capacitors reciprocally according to the output of the logic circuit,
A load driving circuit is provided, wherein the second switching means performs switching control as to whether or not to connect the driving load and a reference voltage terminal according to the output of the logic circuit.
[0009]
According to one aspect of the present invention, first, second, third, fourth and fifth switching means;
First and second capacitors;
A logic circuit in which the output logic is inverted when the input voltage exceeds a predetermined threshold voltage;
A switching control means for controlling on / off of the first, third and fourth switching means, and a load driving circuit comprising:
A driving load is connected to the first end of the first switching means;
When the first switching means is off, input signals are supplied to the second end of the first switching means, the first end of the first capacitor, and the first end of the second capacitor, respectively. ,
A second end of the first capacitor is connected to a first end of the third switching means and an input terminal of the logic circuit;
A second end of the third switching means is connected to the first voltage terminal;
A second end of the second capacitor is connected to a first end of the fourth switching means;
A second end of the fourth switching means is connected to a second voltage terminal;
The switching control means turns off the first switching means and turns on the third and fourth switching means so that electric charges according to the input voltage are accumulated in the first and second capacitors. Performing a first switching control, and then performing a second switching control to turn off the first, third and fourth switching means, and then After the voltage at the second end of the first capacitor is stabilized Performing a third switching control for turning on the first switching means and turning off the third and fourth switching means;
The fifth switching means performs switching control as to whether or not the second ends of the first and second capacitors are short-circuited according to the output of the logic circuit,
A load driving circuit is provided, wherein the second switching means performs switching control as to whether or not to connect the driving load and a reference voltage terminal according to the output of the logic circuit.
[0010]
The invention of claim 1 will be described with reference to FIGS. 1 and 2, for example. The “first switching means” is the switch SW1 in FIG. 1, the “second switching means” is the analog switch Q1, and the “capacitor”. 2 corresponds to the capacitor C1, “logic circuit” corresponds to the logic circuit 13, “switching control means” corresponds to the switch switching control circuit 12 in FIG. 2, and “drive load” corresponds to the signal line S.
[0011]
The invention of claim 2 will be described with reference to FIGS. 2 and 6, for example. The “first switching means” is the switch SW1 in FIG. 6, the “second switching means” is the analog switch Q1, and the “third switching means”. "Switching means" for switch SW5, "fourth switching means" for switch SW6, "fifth switching means" for transistor Q2, "sixth switching means" for transistor Q3, "first capacitor""Is a capacitor C1," second capacitor "is a capacitor C3," logic circuit "is a logic circuit 13," first voltage terminal "is a 0V terminal, and" second voltage terminal "is 10V. Each corresponds to a terminal.
[0012]
The invention of claim 3 will be described with reference to FIG. 8, for example. The “first switching means” is the switch SW1 in FIG. 8, the “second switching means” is the analog switch Q1, and the “third switching means”. "Means" is switch SW5, "fourth switching means" is switch SW6, "fifth switching means" is transistor Q4, "first capacitor" is capacitor C1, and "second capacitor" is capacitor In C3, the “logic circuit” corresponds to the logic circuit 13, the “first voltage terminal” corresponds to the 0V terminal, and the “second voltage terminal” corresponds to the 10V terminal.
[0013]
The “seventh switching means” in claim 4 corresponds to the switch SW3 in FIGS.
[0014]
The “eighth switching means” of claim 5 corresponds to the switch SW2 of FIGS.
[0015]
The “ninth switching means” in claim 6 corresponds to the switch SW4 in FIGS.
[0016]
The invention of claim 9 will be described with reference to FIGS. 2 and 3, for example. The “pixel array section” is the pixel array section 2 in FIG. 3, the “scan line drive circuit” is the scan line drive circuit 4, and the “signal The “line drive circuit” corresponds to the signal line drive circuit 3, the “first load drive circuit” corresponds to the load drive unit 11a, and the “second load drive circuit” corresponds to the load drive unit 11b.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a load driving circuit according to the present invention will be specifically described with reference to the drawings. Hereinafter, an example in which the load driving circuit according to the present invention is applied to a signal line driving circuit of a liquid crystal display device will be described.
[0018]
(First embodiment)
FIG. 1 is a circuit diagram of a first embodiment showing a configuration of a main part of a load drive circuit according to the present invention, FIG. 2 is a schematic block diagram showing the configuration of the entire load drive circuit, and FIG. 3 is a load drive circuit of FIG. 1 is a schematic block diagram of a liquid crystal display device using a signal line driving circuit as a signal line driving circuit.
[0019]
The liquid crystal display device shown in FIG. 3 includes a pixel array section 2 in which signal lines S1 to Sn and scanning lines G1 to Gn are formed vertically and horizontally and pixel display TFTs 1 are arranged in the vicinity of their intersections, and each signal line S1. ˜Sn, and a scanning line driving circuit 4 for driving each of the scanning lines G1˜Gn.
[0020]
3 are formed on the same substrate, and the transistors forming the signal line driving circuit 3 and the scanning line driving circuit 4 are formed by the same manufacturing process as that of the pixel display TFT 1.
[0021]
The signal line drive circuit 3 is configured using the load drive circuit shown in FIG. The load drive circuit of FIG. 2 switches the positive and negative load drive units 11a and 11b provided corresponding to each signal line, and various switches in the load drive units 11a and 11b. And a control circuit 12.
[0022]
The reason why the load driver 11a for positive polarity and the load driver 11b for negative polarity are separately provided is that the polarity of the drive voltage of the signal line is switched in units of one pixel, one horizontal line, or one frame. It is to do.
[0023]
FIG. 1 is a circuit diagram of the load driving unit 11a for positive polarity. As shown in FIG. 1, each of the load driving units 11a includes switches SW1 to SW4, an analog switch Q1 made of a PMOS transistor, a logic circuit 13 in which inverters are connected in two stages, and a capacitor C1. As shown in FIG. 3, a pixel display TFT, a liquid crystal capacitor, an auxiliary capacitor, and the like are connected to the signal line S driven by the load driving units 11a and 11b. In FIG. The load of the line S is equivalently represented by a resistor R and a capacitor C2.
[0024]
One ends of the switches SW1 and SW2 are connected to the signal line S, the other end of the switch SW1 is connected to one end of the switch SW3 and one end of the capacitor C1, and the input video signal Vin is supplied to the other end of the switch SW3. The other end of the capacitor C1 is connected to the input terminal of the logic circuit 13, and the output terminal of the logic circuit 13 is connected to the gate terminal of the analog switch Q1. A first voltage VDD (for example, 10V) is applied to the source terminal of the analog switch Q1, and the other end of the switch SW2 is connected to its drain terminal. A signal line S is connected to one end of the switch SW4, and a second voltage VD (for example, 5V) is applied to the other end of the switch SW4. The switches SW1 to SW4 are controlled to be switched by the switch switching control circuit 12 shown in FIG.
[0025]
In FIG. 1, the connection point between the switch SW1 and the capacitor C1 is a, the connection point between the capacitor C1 and the logic circuit 13 is b, the connection point between the logic circuit 13 and the analog switch Q1 is c, and the connection point between the switches SW1 and SW2. Is d.
[0026]
FIG. 4 is a timing chart of each part in the load drive circuit 11a of FIG. 1, and the operation of the circuit of FIG. 1 will be described below using this timing chart. First, within the period of time T1 to T2, the switch switching control circuit 12 turns off the switches SW1 to SW3 and turns on the switch SW4. As a result, the voltage of the signal line S (point d in FIG. 1) becomes the same voltage (for example, 5 V) as the second voltage VD.
[0027]
Next, within the period of time T2 to T3, the switch switching control circuit 12 turns on only the switch SW3. As a result, the voltage at point a in FIG. 1 becomes equal to the voltage of the input video signal Vin. FIG. 4 shows an example in which the voltage of the input video signal Vin is 7.5V. During this period, the voltage of the signal line S (point d in FIG. 1) is 5V.
[0028]
Here, assuming that the voltage of the input terminal (point b in FIG. 1) of the logic circuit 13 is slightly higher than the threshold voltage of the logic circuit 13 (for example, 5V), the output terminal ( The voltage at point c) in FIG. 1 is 10 V, which is substantially equal to the power supply voltage. Therefore, the analog switch Q1 is turned off during this period.
[0029]
Next, after time T3, the switch switching control circuit 12 turns on the switches SW1 and SW2 and turns off the switches SW3 and SW4. At the time T3, the point a in FIG. 1 is 7.5V, whereas the point d is 5V. Therefore, when the switch SW1 is turned on, the voltage at the point a is lowered due to the point d. In response to this, the voltage at the point b in FIG. 1 which is the other end side of the capacitor C1 is also lowered, and the output of the logic circuit 13 is inverted and becomes low level (for example, 0 V). As a result, the analog switch Q1 is turned on, the first voltage VDD is supplied to the signal line S via the analog switch Q1 and the switch SW2, and the voltage of the signal line S (point d in FIG. 1) gradually increases.
[0030]
When the voltage of the signal line S increases, the voltages at points a and b in FIG. 1 also increase accordingly. Eventually, at time T4, the voltage of the signal line S becomes equal to 7.5V that is the voltage of the input video signal Vin, and the input voltage of the logic circuit 13 exceeds the threshold voltage (5V) of the logic circuit 13, The output of the logic circuit 13 is inverted again to a high level (for example, 10V). As a result, the analog switch Q1 is turned off.
[0031]
When the analog switch Q1 is turned off, the capacitor C2 on the signal line S is gradually discharged and the voltage at the point d in FIG. 1 decreases, but the voltage at the input terminal (point b in FIG. 1) of the logic circuit 13 is reduced. When the voltage falls below the threshold voltage, the analog switch Q1 is turned on again, and the voltage at point d in FIG. 1 rises again. By repeating such an operation, the voltage of the signal line S (point d in FIG. 1) is held at 7.5 V, which is the voltage of the input video signal Vin.
[0032]
FIG. 5 is a circuit diagram showing a detailed configuration of the negative polarity load driving section 11b. As shown in FIG. 5, the load driving unit 11b is different from the load driving unit 11a of FIG. 1 in that the analog switch Q1 is n-type and the source electrode of the analog switch Q1 is grounded. The configuration is the same.
[0033]
As described above, in the first embodiment, the switches SW1 and SW2, the capacitor C1, the logic circuit 13, and the analog switch Q1 shown in FIG. 1 form a feedback loop, and the voltage of the signal line S is the input video signal. If the voltage is lower than the voltage Vin, the analog switch Q1 is turned on to raise the voltage of the signal line S. If the voltage of the signal line S becomes higher than the voltage of the input video signal Vin, the analog switch Q1 is turned off. Then, control for lowering the voltage of the signal line S is performed. Thereby, the voltage of the signal line S is set to a voltage substantially equal to the voltage of the input video signal Vin.
[0034]
In the first embodiment, the input voltage of the logic circuit 13 in the signal line drive circuit 3 is set in advance to a voltage substantially equal to the threshold voltage of the logic circuit 13, and then the input video is input to the signal line drive circuit 3. Since the signal Vin is supplied, the voltage of the signal line S is not affected even if the characteristics of the transistors constituting the signal line driver circuit 3 vary.
[0035]
(Second Embodiment)
Since the logic circuit 13 illustrated in FIG. 1 is configured by combining transistors, the output level of the logic circuit 13 may change due to variations in threshold values or mobility of the transistors and the circuit may not operate normally.
[0036]
Therefore, the second embodiment described below is characterized in that the variation in the characteristics of the logic circuit 13 is canceled out.
[0037]
FIG. 6 is a circuit diagram of the second embodiment of the load driving circuit, and is used as the signal line driving circuit 3 of the liquid crystal display device, as in the first embodiment. As in FIG. 1, the circuit of FIG. 6 includes switches SW1 to SW4, an analog switch Q1 composed of a PMOS transistor, a logic circuit 13 in which inverters are cascaded in two stages, and a capacitor C1. In addition, the circuit of FIG. 6 includes a capacitor C3, switches SW5 to SW7, and PMOS transistors Q2 and Q3.
[0038]
One end of each of the capacitors C1 and C3 and one end of each of the switches SW1 and SW3 are connected to each other. The other end of the capacitor C1 is connected to the input terminal of the logic circuit 13 and one end of the switch SW5, and the other end of the switch SW5 is set to a third voltage (for example, 0V). One end of a switch SW6 is connected to the other end of the capacitor C3, and a fourth voltage (for example, 10V) is applied to the other end of the switch SW6.
[0039]
The output terminal of the logic circuit 13 is connected to one end of the switch SW7 and the gate terminal of the analog switch Q1, and the other end of the switch SW7 is connected to the gate terminals of the transistors Q2 and Q3. One of the source / drain electrodes of the transistor Q2 is connected between the capacitor C1 and the switch SW5, and the other is connected to the CN terminal.
One of the source / drain electrodes of the transistor Q3 is connected between the capacitor C3 and the switch SW6, and the other is connected to the CNR terminal.
[0040]
In FIG. 6, the connection point between the switches SW1, SW3 and the capacitors C1, C3 is a, the connection point between the capacitor C1 and the logic circuit 13 is b, the connection point between the logic circuit 13 and the analog switch Q1 is c, and the switch SW1, The connection point of SW2 is d, and the connection point of capacitor C3 and switch SW6 is e.
[0041]
FIG. 7 is a timing chart of each part in the load drive circuit of FIG. 6, and the operation of the circuit of FIG. 6 will be described below using this timing chart.
[0042]
First, within the period of time T11 to T12, the switch switching control circuit 12 turns on only the switch SW4. As a result, the voltage of the signal line S becomes the same voltage (for example, 5 V) as the second voltage VD.
[0043]
Next, during the period of time T12 to T13, the switch switching control circuit 12 turns off the switches SW1, SW2, and SW4 and turns on the switches SW3, SW5 to SW7. As a result, the voltage at point a in FIG. 6 becomes the voltage of the input video signal Vin. FIG. 7 shows an example in which the voltage of the input video signal Vin is 7.5V. Since the switch SW1 is off, the voltage of the signal line (point d in FIG. 6) is 5V. Since the switches SW5 and SW6 are on, the connection point between the capacitor C1 and the switch SW5 (point b in FIG. 6) is 0V, and the connection point between the capacitor C2 and the switch SW6 (point e in FIG. 6) is 10V. become. Therefore, the output of the logic circuit 13 is also at a low level (about 0 V), and the analog switch Q1 and the transistors Q2 and Q3 are both turned on.
[0044]
Next, within the period of time T13 to T15, the switch switching control circuit 12 turns on only the switch SW7. After time T13, the CN terminal is set to 10V and the CNR terminal is set to 0V. Note that the voltage setting of the CN terminal and the CNR terminal is performed by the switch switching control circuit 12 or another circuit block.
[0045]
Since the output of the logic circuit 13 is at the low level at the time T13, both the transistors Q2 and Q3 are turned on, and the voltage at the connection point between the capacitor C1 and the switch SW5 (point b in FIG. 6) gradually increases. The voltage at the connection point (point e in FIG. 6) between C3 and the switch SW6 gradually decreases.
[0046]
At time T14, the voltage at point b in FIG. 6 exceeds the threshold voltage (for example, 5.5V) of the logic circuit 13, the output of the logic circuit 13 becomes high level (about 10V), the analog switch Q1 and the transistor Q2 and Q3 are both turned off. Therefore, during the period of time T14 to T15, the voltage at the point b in FIG. 6 becomes the threshold voltage (for example, 5.5V) of the logic circuit 13, and the voltage at the point e in FIG. 4.5V).
[0047]
That is, when the input voltage of the logic circuit 13 becomes higher than the threshold voltage of the logic circuit 13, the transistor Q2 is turned off and the input voltage of the logic circuit 13 is lowered. The transistor Q2 is turned on and the input voltage of the logic circuit 13 is increased. By such control, the voltage at the input terminal (point b in FIG. 6) of the logic circuit 13 is controlled to be equal to the threshold voltage of the logic circuit 13.
[0048]
Next, at time T15, the switch switching control circuit 12 turns on the switches SW1, SW2, and SW7 and turns off the switches SW3, SW4, SW5, and SW6. At time T15, the voltage of the signal line S is 5V, and the voltage at point a in FIG. 6 is 7.5V. Therefore, the voltage at point a in FIG. As a result, the voltage at the input terminal (point b in FIG. 6) of the logic circuit 13 is also lowered to be equal to or lower than the threshold voltage of the logic circuit 13, and the output of the logic circuit 13 becomes low level (about 0V). Therefore, the analog switch Q1 is turned on, the voltage of the signal line S (point d in FIG. 6) increases, and the voltages at points a, b, and e in FIG. 6 also increase accordingly.
[0049]
Next, at time T16, the voltage of the input terminal (point b in FIG. 6) of the logic circuit 13 exceeds the threshold voltage of the logic circuit 13, and the output terminal of the logic circuit 13 becomes high level (about 10V). . As a result, the analog switch Q1 is turned off and the voltage of the signal line S (point d in FIG. 6) gradually decreases due to the discharge of the capacitor C2. However, when the voltage drops to a certain extent, the analog switch Q1 is turned on again and the signal line S The voltage rises again.
[0050]
By repeating such an operation, the signal line S (point d in FIG. 6) is held at the voltage (approximately 7.5 V) of the input video signal Vin.
[0051]
Note that the switch SW7 may be turned off after the voltage of the signal line S becomes substantially constant (after time T18).
[0052]
Thus, the circuit of FIG. 6 is provided with two capacitors C1 and C3 that charge and discharge in opposite directions, and even if the threshold voltage of the logic circuit 13 varies, the connection point a between these capacitors C1 and C3. Therefore, before the input video signal Vin is supplied to the signal line S, the input voltage of the logic circuit 13 can be made substantially equal to the threshold voltage of the logic circuit 13.
[0053]
Similarly to the first embodiment, when the voltage of the signal line S becomes higher than the voltage of the input video signal Vin, the analog switch Q1 is turned off to lower the voltage of the signal line S, and the voltage of the signal line S is input. When the voltage is lower than the voltage of the video signal Vin, control is performed such that the analog switch Q1 is turned on to raise the voltage of the signal line S, so that the voltage of the signal line S can be made substantially equal to the voltage of the input video signal Vin. .
[0054]
(Third embodiment)
In the third embodiment, the circuit of the second embodiment (FIG. 6) is simplified.
FIG. 8 is a circuit diagram of a third embodiment of the load driving circuit, which is used as the signal line driving circuit 3 of the liquid crystal display device shown in FIG. 3, for example, as in the first and second embodiments. .
[0055]
The circuit of FIG. 8 is characterized in that a transistor Q4 is provided instead of the transistors Q2 and Q3 of the circuit of FIG. One of the source / drain electrodes of the transistor Q4 is connected between the capacitor C1 and the switch SW5, and the other is connected between the capacitor C3 and the switch SW6. The gate terminal of the transistor Q4 is connected to one end of the switch SW7.
[0056]
In FIG. 8, the connection point between the switches SW1, SW3 and the capacitors C1, C3 is a, the connection point between the capacitor C1 and the logic circuit 13 is b, the connection point between the logic circuit 13 and the analog switch Q1 is c, and the switch SW1, The connection point of SW2 is d, and the connection point of capacitor C3 and switch SW6 is e.
[0057]
FIG. 9 is a timing chart of each part in the load drive circuit of FIG. 8, and the operation of the circuit of FIG. 8 will be described below using this timing chart.
[0058]
First, during the period from time T21 to T22, the switch switching control circuit 12 turns on only the switch SW4. As a result, the voltage of the signal line S becomes the same voltage (for example, 5 V) as the second voltage VD.
[0059]
Next, within the period of time T22-23, the switch switching control circuit 13 turns off the switches SW1, SW2, SW4 and turns on the switches SW3, SW5-SW7. As a result, the voltage at the point a in FIG. 8 becomes the voltage (for example, 7.5 V) of the input video signal Vin. During this period, since the switch SW1 is off, the voltage of the signal line S (point d in FIG. 8) is 5V. Since the switches SW6 and SW7 are on, the point b in FIG. 8 is 0V and the point e is 10V. Therefore, the output of the logic circuit 13 is also at a low level (about 0 V), and the transistor Q4 is turned on.
[0060]
Next, within the period of time T23 to T25, the switch switching control circuit 13 turns on only the switch SW7. At this time, since the transistor Q4 is in the ON state, the points b and e in FIG. 8 are short-circuited, and both voltages change in the direction in which they coincide. Specifically, the voltage at the point b gradually increases from 0V, and the voltage at the point e gradually decreases from 10V.
[0061]
At time T24, the voltage of the input terminal (point b in FIG. 8) of the logic circuit 13 exceeds the threshold voltage of the logic circuit 13, and the output voltage of the logic circuit 13 changes to a high level (for example, 10V). As a result, the transistor Q4 is turned off, and the voltage at the point b does not rise any further.
[0062]
After that, when the voltage at the point b decreases due to the discharge of the capacitor C1 and eventually becomes equal to or lower than the threshold voltage of the logic circuit 13, the output of the logic circuit 13 changes to a low level (for example, 0V) again, and the transistor Q4 again Turns on and the voltage at point b in FIG. 8 rises. By repeating such an operation, the voltage at the input terminal (point b in FIG. 8) of the logic circuit 13 becomes substantially equal to the threshold voltage of the logic circuit 13.
[0063]
Next, at time T25, the switch switching control circuit 13 turns on the switches SW1, SW2, and SW7 and turns off the switches SW3, SW4, SW5, and SW6. As a result, the voltages at points a and b in FIG. 8 are once lowered, the analog switch Q1 is turned on, and the voltage of the signal line S is gradually increased. Thereafter, at time T26, the voltage at the point b exceeds the threshold voltage of the logic circuit 13, and the output of the logic circuit 13 is inverted to become a high level (for example, 10V). As a result, the analog switch Q1 is turned off and the voltage of the signal line S does not rise any further.
[0064]
Thus, in the third embodiment, one end of each of the capacitors C1 and C3 is connected to the source / drain electrode of the transistor Q4, and the gate electrode of the transistor Q4 is controlled according to the output voltage of the logic circuit 13. Therefore, the voltage at the point b and the voltage at the point e in FIG. 8 can be reciprocally controlled, and the voltage at the input terminal (the point b in FIG. 8) of the logic circuit 13 can be controlled by the logic circuit 13 as in the second embodiment. It can be made approximately equal to the threshold voltage.
[0065]
In the above-described first to third embodiments, the example in which the load driving circuit according to the present invention is applied to the signal line driving circuit 3 in the liquid crystal display device has been described. However, the present invention is not limited to the signal line driving circuit 3. Can be widely applied.
[0066]
The various switches shown in FIG. 1 and the like can be configured using transfer gates or analog switches. Further, the switches SW2 and SW4 shown in FIG. 1 and the like are not necessarily required and may be omitted.
[0067]
Further, in FIG. 1 and the like, the example in which the logic circuit 13 is configured by cascading two stages of inverters has been described, but the internal configuration of the logic circuit 13 is not particularly limited as long as it is configured by combining transistors. .
[0068]
【The invention's effect】
As described above in detail, according to the present invention, the voltage of the input terminal of the logic circuit is set substantially equal to the threshold voltage of the logic circuit, and then the external input signal is supplied to the driving load. Even if the threshold value of the circuit varies, the voltage supplied to the driving load is not affected. Therefore, when the present invention is applied to, for example, a signal line drive circuit of a liquid crystal display device, a drive circuit integrated liquid crystal display device having excellent display quality without luminance unevenness can be obtained.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a first embodiment showing a configuration of a main part of a load driving circuit.
FIG. 2 is a schematic block diagram showing the configuration of the entire load drive circuit.
3 is a schematic block diagram of a liquid crystal display device using the load driving circuit of FIG. 2 as a signal line driving circuit.
FIG. 4 is a timing chart of each part in the load drive circuit of FIG. 1;
FIG. 5 is a circuit diagram showing a detailed configuration of a load driving unit for negative polarity.
FIG. 6 is a circuit diagram of a second embodiment of a load driving circuit.
7 is a timing chart of each part of the load drive circuit of FIG. 6;
FIG. 8 is a circuit diagram of a third embodiment of a load driving circuit.
FIG. 9 is a timing chart of each part in the load drive circuit of FIG. 8;
[Explanation of symbols]
1 TFT
2 Pixel array section
3 Signal line drive circuit
4 Scanning line drive circuit
11a, 11b Load drive unit
12 Switch control circuit
13 logic circuits
Q1 Analog switch
Q2, Q3 transistor
SW1 to SW4 switch

Claims

First and second switching means;
A capacitor;
A logic circuit in which the output logic is inverted when the input voltage exceeds a predetermined threshold voltage;
Switching control means for controlling on / off of the first switching means;
A threshold voltage setting circuit;
A load driving circuit comprising:
A driving load is connected to the first end of the first switching means;
When the first switching means is off, an input signal is supplied to the second end of the first switching means and the first end of the capacitor;
A second end of the capacitor is connected to an input terminal of the logic circuit;
The threshold voltage setting circuit controls a voltage at a second end of the capacitor based on an output logic of the logic circuit, and a voltage difference between the threshold voltage of the logic circuit and the input voltage is applied to the capacitor. To hold,
The switching control means turns off the first switching means for a predetermined period until the capacitor holds the differential voltage by the threshold voltage setting circuit , and then turns on the first switching means,
Thereafter, the second switching means performs switching control as to whether or not to connect the driving load and the first end of the first switching means and the reference voltage terminal according to the output of the logic circuit. A characteristic load drive circuit.

First, second, third, fourth, fifth and sixth switching means;
First and second capacitors;
A logic circuit in which the output logic is inverted when the input voltage exceeds a predetermined threshold voltage;
A switching control means for controlling on / off of the first, third and fourth switching means, and a load driving circuit comprising:
A driving load is connected to the first end of the first switching means;
Before Stories second end of the first switching means, the input signal to each of the first end of the first capacitor, and a first end of said second capacitor is connected to so that is supplied,
A second end of the first capacitor is connected to a first end of the third switching means and an input terminal of the logic circuit;
A second end of the third switching means is connected to the first voltage terminal;
A second end of the second capacitor is connected to a first end of the fourth switching means;
A second end of the fourth switching means is connected to a second voltage terminal;
The switching control means turns off the first switching means and turns on the third and fourth switching means so that a charge corresponding to the input signal is accumulated in the first and second capacitors. performing a first switching control, then, the first, second performs switching control for turning off the third and fourth switching means, then, the third and turns on the pre-Symbol first switching means Performing third switching control to turn off the fourth switching means;
While performing the second switching control, the fifth and sixth switching means charge and discharge the first and second capacitors in a reciprocal manner according to the output of the logic circuit . A capacitor of the logic circuit holds a differential voltage between the threshold voltage of the logic circuit and the input voltage ,
While performing the third switching control, the second switching means connects the driving load, the first end of the first switching means, and the reference voltage terminal according to the output of the logic circuit. A load drive circuit characterized by switching control whether to connect or not.

First, second, third, fourth and fifth switching means;
First and second capacitors;
A logic circuit in which the output logic is inverted when the input voltage exceeds a predetermined threshold voltage;
A switching control means for controlling on / off of the first, third and fourth switching means, and a load driving circuit comprising:
A driving load is connected to the first end of the first switching means;
Before Stories second end of the first switching means, the input signal to each of the first end of the first capacitor, and a first end of said second capacitor is connected to so that is supplied,
A second end of the first capacitor is connected to a first end of the third switching means and an input terminal of the logic circuit;
A second end of the third switching means is connected to the first voltage terminal;
A second end of the second capacitor is connected to a first end of the fourth switching means;
A second end of the fourth switching means is connected to a second voltage terminal;
The switching control means turns off the first switching means and turns on the third and fourth switching means so that electric charges according to the input voltage are accumulated in the first and second capacitors. performing a first switching control, then, the first, second performs switching control for turning off the third and fourth switching means, then, the third and turns on the pre-Symbol first switching means Performing third switching control to turn off the fourth switching means;
While performing the second switching control, the fifth switching means switches whether to short-circuit each second terminal of the first and second capacitors according to the output of the logic circuit. Controlling the first capacitor to hold a differential voltage between the threshold voltage of the logic circuit and the input voltage ;
While performing the third switching control, the second switching means connects the driving load, the first end of the first switching means, and the reference voltage terminal according to the output of the logic circuit. A load drive circuit characterized by switching control whether to connect or not.

A seventh switching means for supplying the input signal to the first end and connecting the second end of the first switching means to the second end;
4. The load drive circuit according to claim 2, wherein the switching control means turns on the seventh switching means only while the first switching means is off.

An eighth switching means connected between the drive load and the second switching means;
5. The load drive circuit according to claim 2 , wherein the switching control unit turns on the eighth switching unit after a predetermined period.

The drive load is connected to the first end, and a ninth switching means for applying a predetermined voltage to the second end,
The switching control means turns on the ninth switching means for a predetermined period and sets one end of the driving load to a predetermined voltage before turning on the first switching means . 6. The load driving circuit according to any one of 5 above.

7. The load driving circuit according to claim 2 , wherein the logic circuit is configured by cascading two or more inverting amplifier circuits whose output logic is inverted at a predetermined threshold voltage. .

The load driving circuit according to claim 2 , wherein the driving load is a signal line for supplying pixel data to a pixel electrode.

A pixel array section having signal electrodes and scanning lines formed vertically and horizontally and having pixel electrodes arranged in the vicinity of intersections of these lines;
A scanning line driving circuit for driving the scanning lines;
In a liquid crystal display device in which a signal line driving circuit for driving a signal line is formed on the same substrate,
The signal line driving circuit includes:
A polarity switching circuit for switching the polarity of the signal voltage supplied to the signal line;
A first load drive circuit having the same configuration as the load drive circuit according to any one of claims 1 to 7 ,
A second load drive circuit having the same configuration as the load drive circuit according to any one of claims 1 to 7 ,
The first and second load driving circuits output signal voltages having different voltage levels based on the input signal,
The liquid crystal display device, wherein the polarity switching circuit alternately selects one of outputs from the first and second load driving circuits at a predetermined timing and supplies the selected signal to a signal line.