JP4474138B2 - Pixel drive unit for display device, display circuit, and display device - Google Patents

Description

  The present invention generally relates to a display device such as a liquid crystal display device or an EL (Electro Luminescence) display device, and more particularly to a display device pixel drive unit, a display circuit, and a display device configured to hold data signals for pixels.

  In a liquid crystal display device, a plurality of pixels are arranged in a matrix in order to display an image corresponding to a video signal for one frame input from an external signal source such as a personal computer. The video signal is serial-parallel converted into a data signal for the pixels in each row. When the video signal is in a digital format, a DAC (Digital-Analog Converter) is used to obtain a data signal applied to the pixel as an analog drive voltage. These data signals are respectively supplied to the pixels in each row via a plurality of signal lines. The pixel capacity of each pixel is charged / discharged by the analog drive voltage of the data signal, and the drive voltage is held as a charge until the data signal is updated.

The data signal is normally updated every frame period and is supplied to the pixel via the signal line each time. If the data signal is frequently transmitted in this way, it is difficult to keep power consumption low.
For example, in still image display or moving image display in which the luminance of all pixels is maintained between adjacent frames, it is not always necessary to send all data signals to the pixels in units of frame periods. For this reason, it is necessary to add a pixel memory that holds the drive voltage for a long time to each pixel and change the brightness, or to reverse the polarity of the drive voltage without changing the brightness. There has been proposed a method of reducing the transmission frequency by updating the data signal only when it occurs. However, conventionally, the pixel memory is generally about 1 bit, which is insufficient to obtain an intermediate gradation for displaying a full-color image.

The intermediate gradation can be obtained by combining the pixel memory with the following configuration.
(1) The pixel memory of each pixel has a multi-bit configuration, and an ADC (Analog-Digital Converter) and a DAC are added to the pixel memory.
(2) Each pixel is composed of a plurality of sub-pixels to change the ratio of the white display area.
(3) Time division modulation is performed on each pixel to change the ratio of the white display period.
The configurations of (1) and (2) are difficult to realize with a small pixel size, and the configuration of (3) has many problems in increasing the number of gradations, such as flickering. In order to solve this, the pixel memory may have a function of holding an analog drive voltage.

In general, any analog driving voltage can be held using a capacitor.
When this capacitor is introduced into a pixel, a circuit configuration is required that outputs an analog drive voltage without canceling the charge in the capacitor. Further, in the liquid crystal display device, when a voltage having the same polarity is applied to the liquid crystal layer for a long time, a deterioration phenomenon of the liquid crystal material such as a decrease in resistivity occurs. Accordingly, polarity inversion driving is necessary from the viewpoint of the life of the liquid crystal, and the voltage (-Vdata) having a polarity opposite to the voltage (Vdata) of the data signal supplied via the signal line is also held, and the pixel electrode has a frame period. It is desirable to supply alternately every time.

The problem to be solved is that an analog drive voltage must be held in the pixel memory in order to obtain an intermediate gradation for displaying a full-color image.
In addition, the polarity inversion drive is necessary from the viewpoint of the life of the liquid crystal, and the voltage (-Vdata) having the opposite polarity to the voltage (Vdata) of the data signal is also held and supplied alternately to the pixel electrode every frame period. This is the point that must be done.

According to the first aspect of the present invention, positive and negative signal lines for supplying data signals;
Positive and negative scanning lines for supplying positive and negative scanning signals;
Positive and negative power lines for supplying positive and negative power supply voltages;
A display device pixel drive unit connected to the signal line for supplying the data signal to a pixel of the display device;
A first transistor having a gate connected to the signal line to input the data signal;
First and second switch circuits connected to the source and drain of the first transistor, respectively, and controlled to be turned on and off in the same period by positive and negative scanning signals from the positive and negative scanning lines;
Connected to the source and drain of the first transistor via the first and second switch circuits, respectively, to hold the data signal for the pixel as positive and negative analog drive voltages. First and second storage capacitors for charging a power supply voltage;
A positive voltage or a negative voltage that is connected between the first and second storage capacitors and the pixel and is charged in the first or second storage capacitor every frame period is alternately inverted. An output circuit for supplying the pixel with the polarity
A pixel drive unit for a display device is provided.

According to the second aspect of the present invention, a liquid crystal display element having a structure in which a liquid crystal material is sandwiched between a pair of electrodes that are pixels;
Positive and negative signal lines for supplying data signals;
Positive and negative scanning lines for supplying positive and negative scanning signals;
Positive and negative power lines for supplying positive and negative power supply voltages;
A display circuit connected to the signal line for supplying the data signal to a pixel of the liquid crystal display device;
A first transistor having a gate connected to the signal line to input the data signal;
First and second switch circuits connected to the source and drain of the first transistor, respectively, and controlled to be turned on and off in the same period by positive and negative scanning signals from the positive and negative scanning lines;
In addition, the positive and negative signals are connected to the source and drain of the first transistor via the first and second switch circuits, respectively, and hold the data signal for the pixel as positive and negative analog drive voltages. A memory circuit having first and second storage capacitors charged to the power supply voltage of
An output that is connected between the first and second holding capacitors and the pixel and alternately applies positive and negative analog drive voltages held in the first and second holding capacitors to the liquid crystal display element. And a display circuit comprising the circuit.

According to the third aspect of the present invention, a plurality of liquid crystal display elements arranged in a matrix,
A plurality of scanning lines arranged along a row of a plurality of liquid crystal display elements;
A plurality of signal lines arranged along a row of a plurality of liquid crystal display elements;
Each of these scanning lines and signal lines is arranged in the vicinity of the intersection position, and each of the data lines is fetched from one signal line by control from at least one scanning line,
A plurality of pixel drive units for outputting the data signal to one liquid crystal display element;
Each pixel driver is connected to a first transistor having a gate connected to one signal line, and to the source and drain of the first transistor via the first and second switch circuits, respectively, and to send a data signal to the pixel. A memory circuit having first and second holding capacitors (elements) for charging the positive and negative power supply voltages to hold them as positive and negative analog drive voltages;
A positive voltage or a negative voltage that is connected between the first and second storage capacitors and the pixel and is charged in the first or second storage capacitor every frame period is alternately inverted. And an output circuit for supplying the pixel with the polarity.

  In the display device pixel driver, the display circuit, and the display device of the present invention, when the source and drain of the transistor are connected to the first and second storage capacitors, respectively, The charge is redistributed, and the data signal can be obtained as positive and negative analog drive voltages. These positive and negative analog drive voltages are continuously held in the first and second holding capacitors while there is no need to update the data signal. Therefore, it is possible to obtain an intermediate gradation even if the update of the data signal is suspended in order to reduce power consumption.

Hereinafter, a liquid crystal display device according to an embodiment of the present invention will be described with reference to the accompanying drawings.
FIG. 1 shows a schematic circuit configuration of the liquid crystal display device 100, and FIG. 2 shows a schematic cross-sectional structure of the liquid crystal display device 100.
The liquid crystal display device 100 includes a liquid crystal display panel 101 and a liquid crystal controller 102 that controls the liquid crystal display panel 101. The liquid crystal display panel 101 has, for example, a structure in which the liquid crystal layer LQ is held between the array substrate AR and the counter substrate CT, and the liquid crystal controller 102 is disposed on the drive circuit substrate PCB independent of the liquid crystal display panel 101.

  The array substrate AR includes a plurality of pixel electrodes PE arranged in a matrix in the display region DP on the glass plate GL, a plurality of scanning lines 12 arranged along a row of the plurality of pixel electrodes PE, and a plurality of pixel electrodes PE. A data signal from the corresponding signal line 20 in response to a scanning signal from the corresponding scanning line 12 and arranged in the vicinity of the intersection position of the plurality of signal lines 20, the signal line 20 and the scanning line 12 arranged along the column The pixel drive unit PX that takes in the voltage Vdata of this and outputs the data signal voltage Vdata to the corresponding pixel electrode PE, the scan line drive circuit 103 that drives the plurality of scan lines 12, and the signal line drive circuit that drives the plurality of signal lines 20 104.

The counter substrate CT includes a single counter electrode CE that is disposed to face the plurality of pixel electrodes PE and is set to the ground potential GND, a color filter (not shown), and the like.
The liquid crystal controller 102 receives, for example, an externally supplied digital video signal VIDEO and a synchronization signal, and generates a vertical scanning control signal YCT, a horizontal scanning control signal XCT, a polarity control signal POL, and the like. The vertical scanning control signal YCT is supplied to the scanning line driving circuit 103.
The horizontal scanning control signal XCT is supplied to the signal line driver circuit 104 together with the video signal. The polarity control signal POL is supplied in common to the plurality of pixel driving units PX.

The scanning line driving circuit 103 is controlled by the vertical scanning control signal YCT, and sequentially supplies positive and negative scanning signals to the plurality of scanning lines 12 in one vertical scanning (frame) period.
The scanning signal is supplied to each scanning line 12 for one horizontal scanning period (1H).
The signal line driving circuit 104 is controlled by the horizontal scanning control signal XCT, and performs one-row conversion of the video signal VIDEO input in each horizontal scanning period in which one scanning line 12 is driven by the scanning signal and digital / analog conversion. Are supplied to the plurality of signal lines 20 respectively.

FIG. 3 shows an equivalent circuit of the pixel driver PX shown in FIG. In FIG. 3, P represents a liquid crystal display element constituted by a pixel electrode PE, a counter electrode CE, and a liquid crystal material of a liquid crystal layer LQ sandwiched between the electrodes PE and CE, that is, a liquid crystal pixel. Each pixel driving unit PX includes a pixel memory circuit that holds data signals for the pixels as positive and negative analog driving voltages.
On the array substrate AR, the scanning lines 12 are arranged so as to extend in the row direction in parallel with each other. The positive and negative first sub-scanning lines 11+, 11-, second sub-scanning lines 12+, 12 -Consists of. The polarity control line 13, the positive and negative power supply lines 14+, 14-, and the ground line 15 are arranged so as to extend in the row direction in parallel with each other.

  The memory circuit is configured by combining two positive and negative power supplies, transistors T1 to T9, and first and second holding capacitors C1 and C2, and is connected to a pixel electrode PE serving as a load. In FIG. 3, T1, T3, T5, T7, and T9 are P-channel transistors, and T2, T4, T6, and T8 are N-channel transistors. In this memory circuit, the transistors T2 to T5 connect the first and second holding capacitors C1 and C2 to the positive and negative power supply lines 14+ and 14- supplying the positive and negative power supply voltages, respectively. Thus, a switch circuit is configured to connect the first and second holding capacitors C1 and C2 to the source and drain of the transistor T1, respectively. The transistors T6 to T9 constitute an output circuit that outputs the positive and negative analog drive voltages held in the first and second holding capacitors C1 and C2.

  The gates of the transistors T1 to T5 are connected to the signal line 20, the positive and negative first sub-scanning lines 11+ and 11-, and the second sub-scanning lines 12+ and 12-, respectively. The source of the transistor T2 is connected to the positive power supply line 14+, and the drain of the transistor T2 is connected to the first storage capacitor C1 and the source of the transistor T4. The drain of the transistor T3 is connected to the negative power supply line 14-, and the source of the transistor T2 is connected to the second storage capacitor C2 and the drain of the transistor T5. The first and second storage capacitors C1 and C2 are connected to the ground line 15 and the ground line 15 in the adjacent row, respectively, at the ground side terminal. The source and drain of the transistor T1 are connected to the drain and source of the transistors T4 and T5, respectively. The gates of the transistors T6 to T9 are connected to the first and second holding capacitors C1 and C2 and the polarity control line 13, respectively. The source and drain of the transistor T6 are connected to the positive power supply line 14+ and the source of the transistor T8, respectively, and the drain of the transistor T8 is connected to the pixel electrode PE. The drain and source of the transistor T7 are connected to the negative power supply line 14- and the drain of the transistor T9, respectively, and the source of the transistor T9 is connected to the pixel electrode PE.

  Next, the operation of the pixel drive unit PX having the above-described configuration will be described with reference to the time chart shown in FIG. In the liquid crystal display panel 101, the positive and negative pulses P1 +, the positive and negative first sub-scan lines 11+ and 11− are first applied to the gates of the transistors T2 and T3 in the horizontal scanning period one row before. P1- is added to turn on the transistors T2 and T3. As a result, the first and second holding capacitors C1, C2 are connected to the positive and negative polarity power supply lines 14+, 14-, and the first and second holding capacitors C1, C2 are connected to the positive and negative polarity initial lines. Voltages + Vpi and -Vmi are maintained.

When the same voltage as the power supply voltages + VDD and -VDD is applied to the gates of the transistors T2 and T3, the voltage between the gate and the source becomes 0, and a saturation current flows through the drain. As a result, the initial voltages + Vpi and -Vmi of the first and second holding capacitors C1 and C2 are lowered by the threshold voltage of the transistors T2 and T3, and + Vpi = + VDD-VTn and -Vmi = -VDD + It becomes VTp. Therefore, in order to hold the same initial voltage + Vpi = + VDD and −Vmi = −VDD as the power supply voltage in the first and second holding capacitors C1 and C2, the voltage applied to the gate is equal to the threshold voltage from the power supply voltage. It must be larger than + VDD + VTn, -VDD-VTp.
Here, VTn is an N channel transistor and VTp is a threshold voltage of a P channel transistor. When the transistor is an N channel, the transistor is turned on when the gate potential is higher than the source. When the transistor is a P channel, the transistor is turned on when the gate potential is lower than the source. Therefore, when the gate voltage is set to + VDD + VTn, -VDD-VTp or higher, the transistors T2 and T3 are turned on. However, since the gate potential at this time is higher (or lower) than the source, the source potential of the transistors T2 and T3 Tries to be higher (or lower) than the gate potential, but does not exceed (or below) the power supply voltage, so the initial voltages at this time are + Vpi = + VDD and −Vmi = −VDD.

  Here, when the positive and negative pulses P1 + and P1- are set to 0, the transistors T2 and T3 are turned off, and the charge of the first and second holding capacitors C1 and C2 has no path for escaping anywhere. The second holding capacitors C1 and C2 hold initial voltages + Vpi and −Vmi at the moment when the positive and negative pulses P1 + and P1− become zero. Actually, the initial voltages + Vpi and -Vmi of the first and second holding capacitors C1 and C2 are gradually increased due to the leakage currents of the transistors T2 and T3 and the first and second holding capacitors C1 and C2. Will change.

  Next, in the horizontal scanning period for the row to be scanned this time, positive and negative pulses P2 + and P2- are applied to the gates of the transistors T4 and T5 via the positive and negative second sub-scanning lines 12+ and 12-, respectively. In addition, the transistors T4 and T5 are turned on. At the same time, the data signal voltage + Vdata is supplied to the gate of the transistor T1 through the signal line 20. As a result, the first and second holding capacitors C1 and C2 are connected to the source and drain of the transistor T1, and the initial voltages + Vpi and -Vmi are applied, and the first and second holding capacitors C1 and C2 have positive polarity. In addition, negative drive voltages + Vp and −Vm are maintained.

  When the data signal voltage + Vdata is applied to the gate while the initial voltages + Vpi and -Vmi are held at the source and drain of the transistor T1, the source potential becomes higher than the gate by the threshold voltage VTp, and the drain potential is Since the phase is opposite to that of the source, the drive voltages at this time are + Vp = + Vdata + VTp and −Vm = −Vdata−VTp + Vpi−Vmi. When the positive and negative pulses P2 + and P2- are set to 0, the transistors T4 and T5 are turned off, and the first and second holding capacitors C1 and C2 have positive and negative pulses P2 + and P2- The drive voltage + Vp, -Vm at the moment when it becomes 0 is held. At the same time, the transistor T1 is isolated and the subsequent data input from the signal line 20 is cut off.

When the initial voltage is lower than the power supply voltage + Vpi = + VDD-VTn, -Vmi = -VDD + VTp, the drive voltage is + Vp = + Vdata + VTp, -Vm = -Vdata-VTp + Vpi-Vmi = -Vdata -VTp + VDD-VTn-VDD + VTp = -Vdata-VTn. When the initial voltage is the same as the power supply voltage + Vpi = + VDD, -Vmi = -VDD, the drive voltage is + Vp = + Vdata + VTp, -Vm = -Vdata-VTp + Vpi-Vmi = -Vdata-VTp + VDD -VDD = -Vdata-VTp.
Therefore, there is no problem if the driving voltages + Vp and -Vm differ depending on the initial voltages + Vpi and -Vmi, and the absolute values of the threshold voltages VTn and VTp of the N-channel transistor and the P-channel transistor are equal. Needs to be coordinated. If the drive voltage held in the first and second holding capacitors C1 and C2 is to be the same as the data signal voltage + Vp = + Vdata and −Vm = −Vdata, the threshold value is applied to the gate of the transistor T1 from + Vdata. A voltage + Vdata-VTp that is smaller by the voltage VTp may be added. When an N-channel transistor is used as the transistor T1, a similar result can be obtained by applying a negative data signal voltage -Vdata to the gate.

  The driving voltages + Vp and -Vm held in the first and second holding capacitors C1 and C2 are input to the gates of the transistors T6 and T7, and are not destroyed during reading. Sent to the drain. At this time, the transistors T6 and T7 function as an amplifier having a voltage gain of 1, and the source potential follows the gate potential while maintaining a constant potential difference.

As described above, when the initial voltage is the same as the power supply voltage + Vpi = + VDD and −Vmi = −VDD, the drive voltage held in the first and second holding capacitors C1 and C2 is + Vp = + Vdata + VTp, -Vm = -Vdata-VTp.
This drive voltage drops by threshold voltages VTn and VTp at the subsequent stage of the transistors T6 and T7, and becomes + Vp = + Vdata + VTp−VTn, −Vm = −Vdata−VTp + VTp = −Vdata. . Therefore, if the threshold voltages VTn and VTp of the N-channel transistor and P-channel transistor are designed to be equal and VTn = VTp, the drive voltage + Vp = + Vdata, -Vm = -Vdata, and the data signal voltage and absolute value are Equal positive and negative drive voltages are obtained.

Next, positive and negative pulses P3 + and P3- are alternately applied to the gates of the transistors T8 and T9 via the polarity control line 13 for each frame. When a positive pulse P3 + is applied to the gates of the transistors T8 and T9, the transistor T8 is turned on and the transistor T9 is turned off. As a result, the first holding capacitor C1 and the transistor T6 are connected to the pixel electrode PE, and the positive drive voltage + Vp held in the first holding capacitor C1 is read by the transistor T6 and written to the pixel electrode PE. It is. When the negative pulse P3- is applied to the gates of the transistors T8 and T9, the transistor T8 is turned off and the transistor T9 is turned on. As a result, the second holding capacitor C2 and the transistor T7 are connected to the pixel electrode PE, and the negative drive voltage −Vm held in the second holding capacitor C2 is read by the transistor T7 and written to the pixel electrode PE. It is. As described above, the drive voltages + Vp and −Vm whose polarities are inverted every frame period are alternately sent, and the voltages supplied to the pixel electrode PE and the counter electrode CE are inverted and driven.
As a result, it is possible to prevent the liquid crystal material forming the liquid crystal layer LQ sandwiched between the pixel electrode PE and the counter electrode CE from being deteriorated.

  As described above, when the threshold voltages VTn and VTp of the N-channel transistor and the P-channel transistor are made equal, the positive and negative drive voltages having the same absolute value as the data signal voltage + Vp = + Vdata, −Vm = − Vdata is obtained.

First modification:
FIG. 5 shows an equivalent circuit of a first modification of the pixel driver PX shown in FIG. The same parts as those in FIG. 3 are denoted by the same reference numerals, and a detailed description thereof is omitted. When the threshold voltages VTn and VTp of the N channel transistor and the P channel transistor are different, as shown in FIG. 5, the circuit configuration of FIG. 3 includes the circuit of N channel transistors T10 and T12 and the circuit of P channel transistor T11. Similar results are obtained by connecting. The source of the transistor T10 is connected to the drain of the transistor T4, and the gate and drain of the transistor T10 are connected to the drain of the transistor T2. The source of the transistor T12 is connected to the drain of the transistor T7, and the gate and drain of the transistor T12 are connected to the drain of the transistor T9. The source of the transistor T11 is connected to the source of the transistor T6, and the gate and drain of the transistor T11 are connected to the source of the transistor T8.
That is, the initial voltages + Vpi = + VDD and −Vmi = −VDD are held in the first and second holding capacitors C1 and C2 by applying a voltage higher than the power supply voltage to the gates of the transistors T2 and T3. When the transistors T4 and T5 are turned on / off in this state, the voltage is boosted by the threshold voltage VTn after the N-channel transistor T10, and the drive voltage + Vp = + Vdata + VTp is applied to the first and second holding capacitors C1 and C2. + VTn, -Vm = -Vdata-VTp-VTn is retained.
Next, the drive voltages are stepped down by threshold voltages VTn and VTp at the subsequent stage of the N-channel transistor T6 and the P-channel transistor T7, and become + Vp = + Vdata + VTp and −Vm = −Vdata−VTn, respectively.
Next, the drive voltage is stepped down by the threshold voltages VTp and VTn at the subsequent stage of the P-channel transistor T11 and the N-channel transistor T12, and becomes + Vp = + Vdata and −Vm = −Vdata, respectively. As described above, positive and negative drive voltages having the same absolute value as the data signal voltage can be obtained.

  In the liquid crystal display panel 101, positive and negative first sub-scanning lines 11+, 11-, second sub-scanning lines 12+, 12-, polarity control lines 13, positive and negative power supplies in the horizontal scanning direction. A large number of wires such as the wires 14+, 14-, and the ground wire 15 are required. If these wires are difficult, the number of wires can be reduced by performing the following second to fourth modifications. it can.

Second modification:
FIG. 6 shows an equivalent circuit of a second modification of the pixel driver PX shown in FIG. The same parts as those in FIG. 3 are denoted by the same reference numerals, and a detailed description thereof is omitted. Since the timing of supplying positive and negative pulses P2 + and P2- to the row to be scanned this time is the same as the timing of supplying positive and negative pulses P1 + and P1- to the row to be scanned next, as shown in FIG. The positive and negative second sub-scanning lines 12+ and 12- connected to the gates of the transistors T4 and T5 are positive and negative first sub-scanning lines 11+ and 11- of the next scanning row. Can be omitted by substituting.

Third modification:
FIG. 7 shows an equivalent circuit of a third modification of the pixel driver PX shown in FIG. The same parts as those in FIG. 3 are denoted by the same reference numerals, and a detailed description thereof is omitted. Since the positive and negative first sub-scan lines 11+ and 11− in the previous row are not used until the next pixel data rewrite time comes, the first and The ground line 15 for grounding the second storage capacitors C1 and C2 can be omitted by substituting the positive and negative first sub-scan lines 11+ and 11- in the previous row.

Fourth modification:
FIG. 8 shows an equivalent circuit of a fourth modification of the pixel driver PX shown in FIG. The same parts as those in FIG. 3 are denoted by the same reference numerals, and detailed description thereof is omitted. As shown in FIG. 8, by providing a pulse shaping unit 30 composed of an inverter circuit that converts a positive pulse P1 + into a negative pulse P1- and a clamp circuit, a negative polarity first connected to the gate of the transistor T3 is provided. One sub-scanning line 11 − can be omitted by substituting the output side wiring 11 ′ − of the pulse shaping unit 30.

  As a result of inputting the circuit configuration of FIG. 3 to the circuit simulator, a drive voltage waveform as shown in FIG. 9 was obtained. From FIG. 9, even when the threshold voltages VTn and VTp of the N-channel transistor and the P-channel transistor are different from VTn = 1.0 and VTp = −2.0, the absolute value is equal to the data signal voltage + Vdata input to the gate of the transistor T1. It was confirmed that the positive and negative drive voltages + Vp = + Vdata and −Vm = −Vdata were alternately output every frame period.

By holding an analog drive voltage in the pixel memory, the pixel memory can be applied to a memory circuit, a display circuit, and a display device such as a low power consumption full-color liquid crystal display device.
Further, by holding the bipolar drive voltage in the pixel memory and alternately supplying it to the pixel electrode every frame period, it can be applied to memory circuits, display circuits, and display devices such as long-life liquid crystal display devices. .

It is a figure which shows the circuit structure of the liquid crystal display device which concerns on one Embodiment of this invention. It is a figure which shows roughly the cross-section of the liquid crystal display device shown in FIG. 2 is an equivalent circuit of the pixel driving unit shown in FIG. 4 is a time chart for explaining the operation of the pixel driving unit shown in FIG. 3. FIG. 4 is an equivalent circuit of a first modification in which a voltage drop transistor is added in the pixel driving section shown in FIG. 3. 4 is an equivalent circuit of a second modified example in which the second scanning line is omitted in the pixel driving unit shown in FIG. 3. FIG. 6 is an equivalent circuit of a third modification in which a ground line is omitted in the pixel driving unit shown in FIG. 3. FIG. 10 is an equivalent circuit of a fourth modification in which the negative first scanning line is omitted in the pixel driving section shown in FIG. 3. FIG. 4 is a drive voltage waveform diagram obtained from a circuit simulator that simulates the circuit configuration of the pixel drive section shown in FIG. 3.

11+, 11- first sub-scanning line 12+, 12- second sub-scanning line 12 scanning line 13 polarity control line 14 power supply line 15 ground line 20 signal line 30 pulse shaping unit 100 liquid crystal display device 101 liquid crystal display panel 102 liquid crystal Controller 103 Scan line drive circuit 104 Signal line drive circuit AR Array substrate C1, C2 Retention capacitance CE Counter electrode CT Counter substrate DP Display region GL Glass plate LQ Liquid crystal layer P Liquid crystal display element P1-P3 Pulse PCB Drive circuit substrate PE Pixel electrode PX Pixel driver T1-T12 Transistor

Claims (24)

A signal line for supplying positive and negative data signals ;
Positive and negative scanning lines for supplying positive and negative scanning signals;
Positive and negative power lines for supplying positive and negative power supply voltages;
A display device pixel drive unit connected to the signal line for supplying the data signal to a pixel of the display device;
A first transistor having a gate connected to the signal line to input the data signal;
First and second switch circuits connected to the source and drain of the first transistor, respectively, and controlled to be turned on and off in the same period by positive and negative scanning signals from the positive and negative scanning lines;
Connected to the source and drain of the first transistor via the first and second switch circuits, respectively, to hold the data signal for the pixel as positive and negative analog drive voltages. First and second storage capacitors for charging a power supply voltage;
A positive voltage or a negative voltage that is connected between the first and second storage capacitors and the pixel and is charged in the first or second storage capacitor every frame period is alternately inverted. An output circuit for supplying the pixel with the polarity
A pixel drive unit for a display device.   The first and second storage capacitors are connected to the positive and negative power supply lines that supply the positive and negative power supply voltages, respectively, and then the first and second storage capacitors are connected to the source and drain of the transistor. The display device pixel drive section according to claim 1, further comprising the switch circuit connected to each of the display device pixel circuits.   An output circuit for alternately outputting the positive and negative analog drive voltages held in the first and second holding capacitors to a pixel includes a transistor circuit controlled by a signal supplied to a polarity control line. The display device pixel driving unit according to claim 1.   The display device pixel driver according to claim 1, wherein the first transistor is either a P-channel transistor or an N-channel transistor. The switch circuit includes a second transistor connected between the positive power line and the first storage capacitor;
A third transistor connected between the negative power line and the second storage capacitor;
A fourth transistor connected between the source of the first transistor and the first storage capacitor;
A fifth transistor connected between the drain of the first transistor and the second storage capacitor;
The second and third transistors are controlled to conduct temporarily to set the positive and negative power supply voltages to the first and second holding capacitors, respectively;
The fourth and fifth transistors are controlled to be turned on in order to hold the data signals as positive and negative analog drive voltages in the first and second holding capacitors, respectively, and the gates of the first transistors The display device pixel drive unit according to claim 1, wherein the data signal voltage supplied via the signal line is controlled to be held in the first and second holding capacitors. The output circuit includes sixth and seventh transistors having gates connected to the first and second holding capacitors, respectively, one end connected to the positive power supply line via the sixth transistor, and the other end serving as a load. An eighth transistor connected, and a ninth transistor connected at one end to the negative power supply line via the seventh transistor and connected to the load at the other end,
The pixel driver for a display device according to claim 3, wherein conduction of the eighth and ninth transistors is controlled. The first, third and fifth transistors are P-channel transistors;
6. The pixel driver for a display device according to claim 5, wherein the second and fourth transistors are N-channel transistors. The seventh and ninth transistors are P-channel transistors;
The pixel driver for a display device according to claim 6, wherein the sixth and eighth transistors are N-channel transistors.   The threshold voltage of the P-channel transistor and the threshold voltage of the N-channel transistor are different in absolute value, and the switch circuit further includes a tenth transistor connected between the first storage capacitor and the fourth transistor, 8. The transistor according to claim 7, wherein the transistor is an N-channel transistor provided for voltage drop that compensates for a difference in absolute value of the threshold value so that the positive drive voltage and the negative drive voltage are equal in absolute value. The pixel drive part for display apparatuses of description.   The threshold voltage of the P-channel transistor and the threshold voltage of the N-channel transistor are different in absolute value, and the eleventh transistor, the seventh transistor, and the seventh transistor whose output circuits are connected between the sixth transistor and the eighth transistor. And the eleventh and twelfth transistors have an absolute value of the threshold value so that the positive drive voltage and the negative drive voltage are equal in absolute value. 9. The pixel driver for a display device according to claim 8, which is a P-channel transistor and an N-channel transistor, respectively, provided for a voltage drop that compensates for a difference in value.   The pixel driver for a display device according to claim 6, wherein the first and second loads are a common liquid crystal display element having a structure in which a liquid crystal material is sandwiched between a pair of electrodes. A liquid crystal display element having a structure in which a liquid crystal material is sandwiched between a pair of electrodes that are pixels;
A signal line for supplying positive and negative data signals ;
Positive and negative scanning lines for supplying positive and negative scanning signals;
Positive and negative power lines for supplying positive and negative power supply voltages;
A display circuit connected to the signal line for supplying the data signal to a pixel of the liquid crystal display device;
A first transistor having a gate connected to the signal line to input the data signal;
First and second switch circuits connected to the source and drain of the first transistor, respectively, and controlled to be turned on and off in the same period by positive and negative scanning signals from the positive and negative scanning lines;
In addition, the positive and negative signals are connected to the source and drain of the first transistor via the first and second switch circuits, respectively, and hold the data signal for the pixel as positive and negative analog drive voltages. A memory circuit having first and second storage capacitors charged to the power supply voltage of
A positive voltage or a negative voltage that is connected between the first and second storage capacitors and the pixel and is charged in the first or second storage capacitor every frame period is alternately inverted. An output circuit for supplying the liquid crystal display element with the polarity
A display circuit comprising:   The memory circuit connects the first and second storage capacitors to the positive and negative power supply lines that supply the positive and negative power supply voltages, respectively, and then connects the first and second storage capacitors to the first and second storage capacitors. The display circuit according to claim 12, further comprising a switch circuit connected to each of a source and a drain of one transistor. A plurality of liquid crystal display elements arranged in a matrix;
A plurality of scanning lines arranged along a row of a plurality of liquid crystal display elements;
A plurality of signal lines arranged along a row of a plurality of liquid crystal display elements;
Each of these scanning lines and signal lines is arranged in the vicinity of the intersection position, and each of the data lines is fetched from one signal line by control from at least one scanning line,
A plurality of pixel drive units for outputting the data signal to one liquid crystal display element;
Each pixel driver is connected to a first transistor having a gate connected to one signal line, and to the source and drain of the first transistor via the first and second switch circuits, respectively, and to send a data signal to the pixel. A memory circuit having first and second holding capacitors for charging the positive and negative power supply voltages to hold them as positive and negative analog drive voltages;
A positive voltage or a negative voltage that is connected between the first and second storage capacitors and the pixel and is charged in the first or second storage capacitor every frame period is alternately inverted. And an output circuit for supplying the pixel with a voltage of the same polarity.   The memory circuit connects the first and second storage capacitors to the positive and negative power supply lines that supply the positive and negative power supply voltages, respectively, and then connects the first and second storage capacitors to the first and second storage capacitors. The display device according to claim 14, further comprising a switch circuit connected to each of a source and a drain of one transistor.   The display device according to claim 14, wherein the memory circuit further includes an output circuit that outputs the positive and negative analog drive voltages held in the first and second holding capacitors. The switch circuit includes a second transistor connected between the positive power line and the first storage capacitor;
A third transistor connected between the negative power line and the second storage capacitor;
A fourth transistor connected between the source of the first transistor and the first storage capacitor;
A fifth transistor connected between the drain of the first transistor and the second storage capacitor;
The second and third transistors are controlled to conduct temporarily to set the positive and negative power supply voltages to the first and second holding capacitors, respectively;
The fourth and fifth transistors are controlled to be turned on in order to hold the data signals as positive and negative analog drive voltages in the first and second holding capacitors, respectively, and the gates of the first transistors The display device according to claim 15, wherein the display device is controlled so that the data signal voltage supplied via the signal line is held in the first and second holding capacitors.   Each of the scanning lines includes a positive and negative first sub-scanning line that supplies a positive pulse and a negative pulse that conduct the second and third transistors as a scanning signal in one horizontal scanning period, and the first horizontal 15. A positive and negative second sub-scanning line for supplying a positive pulse and a negative pulse for conducting the fourth and fifth transistors as scanning signals in one horizontal scanning period following a scanning period. The display device according to claim 17.   19. The display device according to claim 18, wherein the positive and negative second sub-scan lines are common to positive and negative first sub-scan lines for a liquid crystal display element in the next row.   19. The positive and negative first sub-scan lines are respectively connected as ground lines to the first and second storage capacitors of the memory circuits for the liquid crystal display elements in the next row. Display device.   The switch circuit includes a pulse shaping circuit that inverts the polarity of a gate pulse applied to one gate of each of the second and third transistors and applies it to the other gate of the second and third transistors. 18. The display device according to 17. The output circuit includes sixth and seventh transistors having gates connected to the first and second holding capacitors, respectively, one end connected to the positive power supply line via the sixth transistor, and the other end connected to the first transistor. An eighth transistor connected to the first load, and a ninth transistor connected at one end to the negative power supply line via the seventh transistor and connected to the second load at the other end, The display device according to claim 16, wherein conduction of the eighth and ninth transistors is controlled . Display the liquid crystal display element is a liquid crystal pixel having a structure in which liquid crystal material is sandwiched between a pair of electrodes according to 請 Motomeko 14.   The display device according to claim 22, wherein the first and second loads are common liquid crystal display elements.

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