TW476854B - Circuit for increasing signal amplitude, circuit for driving load and liquid crystal display apparatus - Google Patents

Circuit for increasing signal amplitude, circuit for driving load and liquid crystal display apparatus Download PDF

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Publication number
TW476854B
TW476854B TW88119492A TW88119492A TW476854B TW 476854 B TW476854 B TW 476854B TW 88119492 A TW88119492 A TW 88119492A TW 88119492 A TW88119492 A TW 88119492A TW 476854 B TW476854 B TW 476854B
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TW
Taiwan
Prior art keywords
voltage
circuit
signal
capacitor
aforementioned
Prior art date
Application number
TW88119492A
Other languages
Chinese (zh)
Inventor
Yoshiaki Aoki
Masao Karibe
Original Assignee
Toshiba Corp
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Publication date
Priority claimed from JP12751298A external-priority patent/JP4542633B2/en
Priority claimed from JP11031795A external-priority patent/JP2000231089A/en
Priority claimed from JP30595299A external-priority patent/JP4535537B2/en
Priority claimed from JP30594299A external-priority patent/JP4515563B2/en
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of TW476854B publication Critical patent/TW476854B/en

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Abstract

The present invention relates to circuit for increasing signal amplitude, circuit for driving load and liquid crystal display apparatus. The differential voltage between the base level voltage V1 and the threshold limit voltage of the logic circuit 20 used for increasing amplitude is stored in capacitor C1. When the input signal IS is inputted to the logic circuit 20 used for increasing amplitude, the voltage stored in capacitor C1 is added to voltage of the input signal IS so as to obtain the input signal. Thus, the voltage difference between the base level voltage and the threshold limit voltage of the logic circuit 20 used for increasing amplitude can be absorbed. Therefore, the circuit for increasing the signal amplitude can still operate normally even under the condition that the threshold limit voltage of the logic circuit 20 for increasing amplitude inside the circuit for increasing the signal amplitude is not uniform.

Description

476854 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（1 ) 本發明係有關信號增·幅電路及負荷驅動電路以及使用 此之液晶顯示裝置者。' ‘ —般而言，液晶顯示裝置係具備信號線及掃瞄線配設 呈矩陣狀之畫素陣列，和驅動信號線及掃瞄線的驅動電路 加以構成者。以往，將畫素陣列部和驅動電路形.成於各別 之基板之故，難以達到液晶顯示裝置之成本的下降，又， 難以提升對於液晶顯示裝置之外形尺寸的實際畫面尺寸之 比率。 - - 但是，就近年以來，由於在玻璃基板上，將多晶矽做 爲材料，形成T F T (薄膜電晶體）的製造技術逐漸進步 之故，利用此技術，可將畫素陣列部和驅動電路形成於同 一玻璃基板上。 然而，尤其做爲最近之驅動電路一體型液晶顯示裝置 之技術傾向，令將數位信號變換至類比之影像信號的機能 - 一 ，具備於液晶顯示裝置內之驅動電路之故，將數位信號直 接輸入於玻璃基板上之驅動電路的液晶顯示裝置之開發則 甚爲盛行。 但是，尤其之直視型之液晶顯示裝置中，自外部輸入 之數位輸入信號則透過、阻抗負荷及容量負荷大之玻蕲上之 配線，供乎信號線用之驅動電路。爲此，爲了將數位輸入 信號自外部向玻璃基板上之驅動電路直接供給，需以驅動 能力爲大之信號供給電路，供給數位輸入信號。是故，另 外需要此驅動能力大之數位輸入信號用之信號驅動電路。 又，就現在而言，於玻璃基板上，形成均勻特性良好 (請先閱讀背面之注意事項再填寫本頁) ·丨丨丨丨丨丨丨訂丨，— _丨丨丨- · 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） -4 - 476854 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（2) 之多晶矽T F T是爲困難的，因此，使用於外部電路之數 位輸入信號之掘幅的狀態下r無法直接動作玻璃基板上之 驅動電路，需另外之增幅數位輸入信號之振幅的信號增幅 電路。 心 即，需將信號增幅電路內藏於玻璃基板上之·驅動電路 。然後，於此信號增幅電路輸入數位輸入信號，增大該振 幅之上，做爲數位輸出信號，需使用該數位輸出信號，動 作驅動電路。 · 但是，於玻璃基板上，難·以形成均勻特性之多晶矽 T F T之故，亦難以使設於信號增幅電路的振幅增幅用邏 V輯電路之特性整齊化。爲此，振幅增幅用邏輯電路之臨限 値電壓則於每方塊或每製作有不同之情形。 例如，數位輸入信號爲以4 V〜6 V爲振幅的信號， 將此以信號增幅電路增幅爲以0 V〜1 〇 V爲振幅之信號 時，此信號增幅電路內之振幅增幅用邏輯電路之臨限値電 壓係設定呈5 V。但是，構成振幅增幅用邏輯電路之多晶 矽TFT之特性的參差不齊，臨限値電壓有呈4·5V或 5 · 5 V之情形。此時，數位輸入信號爲由4 V變化至 6 V的定時之時，於數位輸出信號自Ο V變化至1 士V的 定時之間，會產生偏移。 又，振幅增幅用邏輯電路之臨限値電壓則大爲偏移呈 6·5V之時，有輸入以4V〜6V爲振幅之數位輸入信 號時，數位輸出信號係不切換爲1 0 V，而產生不良品之 問題。 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 々 、 W I I-----I-----— — -----111^.---------------------- (請先閱讀背面之注意事項再填寫本頁) 476854 - .. -. -!.. . ... 7 ... A7 B7 五、發明說明（3) (請先閱讀背面之注意事項再填寫本頁) 更且，如上所述，於·玻璃基板上形成均句之特性的多 晶矽T F T在於現狀爲困難—使臨限値電壓或移動度等有 參差。因此，假使將畫素陣列部和驅動電路形成於同一基 板上時，由^於T F T之特性之參差，有產生亮度斑紋等之 顯示品質的下降之虞，而且消耗電力亦會增加。· ' 在此，本發明係有鑑於此點而進行者，該目的係提供 於信號增幅電路內之振幅增幅用邏輯電路之臨限値電壓有 參差的情形下，仍可得正常動作之信號增幅電路者。即本 發明之目的係提供構成振幅增幅用邏輯電路之多晶矽 丁 F 丁之特性不一定爲均勻的狀況下，仍可得正常動作之 信號增幅電路者。 本發明之並他目的係提供供給於驅動負荷的電壓則不 經由電晶體之特性之參差影響而變動的負荷驅動電路者。 經濟部智慧財產局員工消費合作社印$衣 有關本發明之信號增·幅電路係具備輸入以第1之寬度 爲振幅的數位輸入信號，增幅此數位輸入信號之振幅，輸 出做爲較前述第1之寬度爲大的第2之寬度的數位輸出信 號，信號振幅增幅電路中，將以第之寬度爲振幅的信號， 增幅至較前述第1之寬度爲大的前述第2之寬度爲振幅的 信號，做爲前述數位輸出信號加以輸出的振幅增幅甩邏輯 電路，和一端連接於前述振幅增幅用邏輯電路的差分電壓 保持電路中，前述數位輸入信號之高和低之切換電壓的基 準電壓，和將與略等於前述振幅增幅用邏輯電路之高和低 之邏輯切換的臨限値電壓的電壓之差分電壓暫時保持的差 分電壓保持電路，將欲保持前述差分電壓保持電路的前述 -6 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 476854 - - ；；；- : A7 __: B7 五、發明說明（4 .) 差分電壓，設定.於前述差分電壓保持電路之時，將前述差 分電壓保持電路之前述一端—設定呈略等於前述振福增幅 用邏輯電路之前述臨限値電壓的電壓的臨限値設定電路， 和將欲保持前述差分電壓保持電路的前述差分電壓，設定 於前述差分電壓保持電路之時，令前述差分電壓，保持電路 之另一端設定呈前述數位輸入信號之高和低之邏輯切換的 基準電壓的基準電壓設定電路，和於前述差分電壓保持電 路之前述另一端，輸入前述數位輸入信號的數位信號輸入 電路爲一個特徵。 - 又，有關本發明之液晶顯示裝置係形成於透明基板上 的畫素陣列部中，信號線及掃猫線形成呈縱橫，於此等之 各線交點附近，具有列設之畫素電極的畫素陣列部，和形 成於前述透明基板上，進行前述信號線和前述掃瞄線中之 至少一方驅動的驅動電路中，具有令數位元影像信號，變 換至類比影像信號之機能的驅動電路的液晶顯示裝置中， 前述驅動電路係複數具備輸入以第1之寬度爲振幅的數位 元易影像輸入信號，增幅此數位輸入信號之振幅，輸出做 爲較前述第1之寬度爲大的第2之寬度的數位元影像輸出 信號，信號振幅增幅電路中，將以第1之寬度爲振幡的信 號，增幅至較前述第1之寬度爲大的前述第2之寬度爲振 幅的信號，做爲前述數位元影像輸出信號加以輸出的振幅 增幅用邏輯電路，和一端連接於前述振幅增幅用邏輯電路 的差分電壓保持電路中，前述數位元影像輸入信號之高和 / 低之切換電壓的基準電壓，和將與略等於前述振幅增幅用 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） ----------I i I-----------11 (請先閱讀背面之注意事項再填寫本頁) 476854 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（5) 邏輯電路之高和低之邏輯·切換的臨限値電壓的電壓之差分 電壓暫時保持的差分電壓保持電路，將欲保持前述差分電 壓保持電路的前述差分電壓，設定於前述差分電壓保持電 路之時，將前述差分電壓保持電路之前述一端，設定呈略 等於前述振幅增幅用邏輯電路之前述臨限値電壓·的電壓的 臨限値設定電路，和將欲保持前述差分電壓保持電路的前 述差分電壓，設定於前述差分電壓保持電路之時，令前述 差分電壓保持電路之另一端設定.呈前述數位元影像輸入信 號之高和低之邏輯切換的基準電壓的基準電壓設定電路， 和於前述差分電壓保持電路之前述另一端，輸入前述數位 元影像輸入信號的數位信號輸入電路爲一個特徵。 更且，有關本發明之負荷驅動電路係輸入所定電壓振 幅之輸入信號，將此輸入信號之電壓供予連接負荷之信號 線的負荷驅動電路中，爲變更前述信號線之電壓之電壓變 更電路，和將前述電壓變更電路和前述信號線間之導通， 呈開啓/關閉的第1開關，和當輸入電壓呈所定臨限値電 壓之時，輸出邏輯則被反轉，控制前述第1之開關/關閉 的邏輯電路，和保持略等於前述邏輯電路之前述臨限値電 壓的電壓和前述輸入信號之電壓的差分電壓的差分鼇壓保 持電路，和將欲保持前述差分電壓保持電路的前述差分電 壓，設定於前述差分電壓保持電路之時，將前述差別電壓 保持電路之一端設定呈略等於前述邏輯電路之臨限値電壓 的臨限値電壓設定電路，和將欲保持前述差分電壓保持電 路的前述差分電壓，設定於前述差分電壓保持電路之前， 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） · 8 - --------------—----- 丨訂--------- (請先閱讀背面之注意事項再填寫本頁) 476854 一： Λ, B7 五、發明說明（6 ) 將前述差別電壓保持電路·之另一端設定呈在前述輸入信號 之電壓的輸入電壓設定電路爲一個特徵者。 又，有關本發明之液晶顯示裝置係具有形成於透明基 板上的畫素陣列部中’信號線及掃瞄線形成呈縱橫，於此 * 等之各線交點附近，具有列設之畫素電極的畫素.陣列部， 和形成於前述透明基板上，進行前述信號線之驅動的信號 線驅動電路，和形成於前述透明基板上，進行前述掃瞄線 之驅動的掃瞄線驅動電路的液晶顯示裝置中，前述信號線 驅動電路係複數具備包含輸入所定電壓振幅之輸入信號， 將此輸入信號之電壓供予連接畫素電極之信號線的負荷驅 動電路中，爲變更前述信號線之電壓之電壓變更供給電路 ，和將前述電壓變更電路和前述信號線間之導通，呈開啓 /關閉的第1開關，和當輸入電壓呈所定臨限値電壓之時 ，輸出邏輯則被反轉，控制前述第1之開關/關閉的邏輯 電路，和保持略等於前述邏輯電路之前述臨限値電壓的電 壓和前述輸入信號之電壓的差分電壓的差分電壓保持電路 ，和將欲保持前述差分電壓保持電路的前述差分電壓，設 定於前述差分電壓保持電路之時，·將前述差別電壓保持電 路之一端設定呈略等於前述邏輯電路之臨限値電壓的·臨限 値電壓設定電路，和將欲保持前述差分電壓保持電路的前 述差分電壓，設定於前述差分電壓保持電路之前，將前述 差別電壓保持電路之另一端設定呈在前述輸入信號之電壓 的輸入電壓設定電路的負荷驅動電路。 (請先閱讀背面之注意事項再填寫本頁) 'i 111 ---^ · I------. 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） -9- 476854 A7 B7 五、發明說明（7 ) 【圖示之簡單說明】 · (請先閱讀背面之注意事項再填寫本頁) 圖1係顯示有關本發明之第1實施形態的信號增幅® 路之電路構成圖。 圖2係圖3之各段之電路內部的槪略方塊圖。 圖3係顯示適用本發明之液晶顯示裝置之信·號線·驅_ 電路之內部構成。 圖4係顯示適用本發明之液晶顯示裝置之整體構成° 圖5係顯示爲說明示於圖1之有關第1實施形態之{§ 號增幅電路的動作的定時圖。 .圖6係顯示有關本發明之第2實施形態之信號增幅電 路之電路構成圖。 圖7係顯示爲說明圖6所示有關第2實施形態的信_ 增幅電路的動作之流程圖。 圖8係顯示有關本發明之第3實施形態之信號增幅® - 路之電路構成圖。 圖9係顯示爲說明圖6所示有關第2實施形態的信號 增幅電路的動作之流程圖。 經濟部智慧財產局員工消費合作社印製 圖1 0係顯示有關本發明之第4實施形態之信號增幅 電路之電路構成圖。 < 圖1 1係顯示有關本發明之第5實施形態之信號增幅 電路之電路構成圖。 _ 圖1 2係顯示爲說明圖1 1所示有關第5實施形態@ 信號增幅電路的動作之流程圖° 圖1 3係顯示有關本發明之第6實施形態之信號增幅 --------- 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 x 297公釐） -10 - 經濟部智慧財產局員工消費合作社印製 476854 -· - - - B7 五、發明說明（β) - . · ./.·' . -電路之電路構成圖。 圖1 4係顯示有關本發明之第7實施形態之信號增幅 電路之電路，構成圖。 圖1 5係顯示爲說明圖1 4所示有關第7實施形態的 信號增幅電路的動作之流程圖。，· 圖1 6係顯示有關本發明之第8實施形態之信號增幅 電路之電路構成圖。 圖1 7係顯示爲說明圖Ί 6所示有關第8實施形態的 信號增幅電路的動作之流程麗。 圖1 8係顯示有關本發明之第9實施形態之信號增幅 電路之電路構成圖。 圖1 9係顯示有關本發明之第1 0實施形態之信號增 幅電路之電路構成圖。 圖2 0係顯示爲說明圖1 9所示有關第1 0實施形態 — * .一 的信號增幅電路的動作之流程圖。 圖2 1係顯示本發明所使用之振幅增幅用邏輯電路之 電路構成之一例（第1 1實施形態） 圖2 2係顯示負荷驅動電路之主要部之構成的第1 2 實施形態之電路圖。 * - 圖2 3係顯示負荷驅動電路整體之構成的方塊圖。 圖2 4係爲說明正極性用之負荷驅動電路和負極性之 負荷驅動電路之動作區分圖。 圖2 5係第1 2實施形態之負荷驅動電路內之各部之 定時圖。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公餐） -11 . m V I--- ----I--I ----Ί I ---^--------I ------------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 476854 .: A7 B7 五、發明說明（9 ) 圖2 6係顯示第1 2‘實施形態之負極性用之負荷驅動 電路之詳細構成電路圖' 。 圖2 7係負荷驅動電路之第1 3實施形態之電路圖。 圖2 8係第1 3實施形態之負荷驅動電路內之各部之 一、- . . 定時圖。 * ' 圖2 9係顯示第1 3實施形態之負極性用之負荷驅動 電路之詳細構成電路圖。 圖3 0係顯示.第1 3賓施形態之正極性用之負荷驅動 電路之變形例之電路圖。 ^ \ 圖3 1係顯示第1 3實施形態之負極性用之負荷驅動 電路之變形例之電路圖。 圖3 2係負荷驅動電路之第1 4實施形態之電路圖。 圖3 3係第1 4實施形態之負荷驅動電路內之各部之 定時圖。 ·. ~ ' - - .. · 圖3 4係顯示第1 4實施形態之負極性用之負荷驅動 電路之詳細構成電路圖。 圖3 5係顯示第1 4實施形態之正極性用之負荷驅動 電路之變形例之電路圖。 圖3 6係顯示第1 4實施形態之負極性用之負荷驅動 電路之變形例之電路圖。 圖3 7係負荷驅動電路之第1 5實施形態之電路圖。 圖3 8係第1 5實施形態之.負荷驅動電路內之各部之 定時圖。 圖3 9係顯示第1 5實施形態之負極性用之負荷驅動 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -12- - --- % V I.---II----— 裝 ----I--- — 訂 .. : ;.· · (請先閱讀背面之注意事項再填寫本頁)476854 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the Invention (1) The present invention is related to signal amplifier circuits and load drive circuits, and those using this liquid crystal display device. '‘In general, a liquid crystal display device includes a pixel array in which signal lines and scanning lines are arranged in a matrix, and a driving circuit for driving the signal lines and scanning lines. In the past, it has been difficult to achieve a reduction in the cost of a liquid crystal display device by forming the pixel array portion and the driving circuit on separate substrates, and it has been difficult to increase the ratio of the actual screen size to the external dimensions of the liquid crystal display device. --However, in recent years, since polycrystalline silicon is used as a material on glass substrates to manufacture TFTs (thin-film transistors), the technology has gradually improved. Using this technology, the pixel array section and the driving circuit can be formed on On the same glass substrate. However, especially as the recent technical trend of the integrated circuit of the driving circuit type liquid crystal display device, the function of converting digital signals to analog video signals-First, because the driving circuit is provided in the liquid crystal display device, the digital signals are directly input The development of liquid crystal display devices with driving circuits on glass substrates is very popular. However, in the direct-view type liquid crystal display device, the digital input signal input from the outside passes through the wiring on the glass substrate with large impedance load and capacity load, and is used for the driving circuit of the signal line. For this reason, in order to directly supply the digital input signal to the driving circuit on the glass substrate from the outside, a signal supply circuit having a large driving capacity is required to supply the digital input signal. Therefore, in addition, a signal driving circuit for a digital input signal having a large driving capacity is needed. Also, for now, it has good uniformity on the glass substrate (please read the precautions on the back before filling this page) · 丨 丨 丨 丨 丨 丨 Order 丨, — _ 丨 丨 丨-· This paper size Applicable to China National Standard (CNS) A4 specification (210 X 297 public love) -4-476854 Printed by A7 B7, Consumer Cooperative of Intellectual Property Bureau, Ministry of Economic Affairs V. Description of the invention (2) Polycrystalline TFT is difficult, therefore, using In the state of the digital input signal of the external circuit, r cannot directly actuate the driving circuit on the glass substrate, and a separate signal amplifier circuit is needed to increase the amplitude of the digital input signal. The heart is that the signal amplifier circuit needs to be built in the glass substrate · drive circuit. Then, a digital input signal is input to this signal amplifier circuit, and the amplitude is increased to be a digital output signal. The digital output signal is required to operate the driving circuit. · However, it is difficult to form a polycrystalline silicon T F T with uniform characteristics on a glass substrate, and it is also difficult to trim the characteristics of a logic V circuit for an amplitude amplifier provided in a signal amplifier circuit. For this reason, the threshold and voltage of the logic circuit for amplitude increase are different for each block or production. For example, if the digital input signal is a signal with an amplitude of 4 V to 6 V, and the signal amplifier circuit is amplified to a signal with an amplitude of 0 V to 100 V, the amplitude of the logic circuit in the signal amplifier circuit The threshold voltage is set to 5 V. However, the characteristics of the polycrystalline silicon TFTs constituting the logic circuit for amplitude increase are uneven, and the threshold voltage may be 4 · 5V or 5 · 5 V. At this time, when the digital input signal changes from 4 V to 6 V timing, an offset occurs between the timing of the digital output signal changing from 0 V to 1 ± V. In addition, when the threshold voltage of the amplitude increase logic circuit is greatly deviated from 6 · 5V, when a digital input signal with an amplitude of 4V ~ 6V is input, the digital output signal is not switched to 10 V, and Problems with defective products. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 々, WI I ----- I -----— — ----- 111 ^ .----- ----------------- (Please read the notes on the back before filling out this page) 476854-..-.-! .. ... 7 ... A7 B7 V. Description of the invention (3) (Please read the precautions on the back before filling in this page) Moreover, as mentioned above, it is difficult to form polycrystalline silicon TFTs with uniform characteristics on a glass substrate. Or movement and so on. Therefore, if the pixel array portion and the driving circuit are formed on the same substrate, the difference in characteristics due to T F T may cause deterioration in display quality such as brightness streaks, and power consumption may increase. · 'Here, the present invention has been made in view of this point, and the purpose is to provide a normal operation signal increase in the case where the threshold voltage of the amplitude increase logic circuit in the signal increase circuit is uneven. Circuit person. That is, the object of the present invention is to provide a signal amplifier circuit that can obtain a normal operation even if the characteristics of the polycrystalline silicon D F constituting the logic circuit for amplitude boost are not necessarily uniform. Another object of the present invention is to provide a load driving circuit in which the voltage supplied to a driving load does not change through the influence of the characteristics of the transistor. The signal-amplifying circuit of the present invention is printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and the Consumer Cooperative. The signal-amplifying circuit is provided with a digital input signal having an amplitude of the first width, and the amplitude of the digital input signal is amplified. The digital output signal of the second width having a large width and the signal amplitude amplifying circuit will amplify the signal having the second width as the amplitude to the signal of the second width having the larger amplitude than the first width. , As the amplitude increase logic circuit for outputting the digital output signal, and a differential voltage holding circuit connected at one end to the logic circuit for amplitude increase, the reference voltage of the high and low switching voltage of the digital input signal, and A differential voltage holding circuit that temporarily holds a differential voltage that is slightly different from the threshold voltage of the logic circuit that switches the high and low logic of the amplitude increase, and will hold the aforementioned -6 of the differential voltage holding circuit. Applicable to China National Standard (CNS) A4 specification (210 X 297 mm) Employees' intellectual property bureau of the Ministry of Economic Affairs's consumer cooperation Printed 476854--;;--A7 __: B7 V. Description of the invention (4.) Differential voltage, setting. At the time of the aforementioned differential voltage holding circuit, set the aforementioned one end of the aforementioned differential voltage holding circuit—setting slightly equal to The threshold threshold voltage setting circuit of the threshold threshold voltage of the vibration boosting logic circuit, and when the differential voltage to be held in the differential voltage holding circuit is set in the differential voltage holding circuit, the differential voltage is set. The other end of the holding circuit sets a reference voltage setting circuit that sets a reference voltage that is a logic switch between high and low of the digital input signal, and a digital signal input circuit that inputs the digital input signal to the other end of the differential voltage holding circuit. As a feature. -In addition, the liquid crystal display device of the present invention is formed in a pixel array section on a transparent substrate, and signal lines and cat lines are formed vertically and horizontally. Near the intersections of these lines, there are pictures of pixel electrodes arranged in rows. A pixel array unit and a driving circuit formed on the transparent substrate and driving at least one of the signal line and the scanning line, and a liquid crystal driving circuit having a function of converting a digital image signal into an analog image signal In the display device, the driving circuit is provided with a plurality of digital easy-image input signals having the first width as the amplitude, and the amplitude of the digital input signal is amplified, and the output is the second width which is larger than the first width. Digital image output signal, in the signal amplitude amplifying circuit, the signal with the first width as the oscillating signal is amplified to the signal with the second width as the amplitude which is larger than the first width, as the aforementioned digital A logic circuit for amplitude amplification for outputting a meta-video output signal, and a differential voltage holding circuit connected at one end to the logic circuit for amplitude amplification The reference voltage of the high and low switching voltages of the aforementioned digital image input signal, and the same as the aforementioned amplitude increase. This paper scale applies the Chinese National Standard (CNS) A4 specification (210 X 297 public love) --- ------- I i I ----------- 11 (Please read the precautions on the back before filling out this page) 476854 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the Invention (5) A differential voltage holding circuit that temporarily holds a differential voltage of a high voltage and a low logic of a logic circuit and a switching threshold voltage. The differential voltage holding circuit that holds the differential voltage holding circuit is set to the differential. In the case of a voltage holding circuit, the first end of the differential voltage holding circuit is set to a threshold threshold setting circuit which is slightly equal to the threshold voltage and voltage of the amplitude increase logic circuit, and the differential voltage holding circuit is to be maintained. When the aforementioned differential voltage of the circuit is set in the aforementioned differential voltage holding circuit, the other end of the aforementioned differential voltage holding circuit is set. It shows the high and low of the aforementioned digital image input signal A reference voltage of the reference voltage setting circuit switching logic, and the other end of the differential in the voltage holding circuit, the input digital video input signals membered digital signal input circuit of a feature. Furthermore, the load driving circuit according to the present invention is a voltage changing circuit that changes the voltage of the signal line in a load driving circuit that inputs an input signal of a predetermined voltage amplitude and supplies the voltage of the input signal to a signal line connected to the load. The first switch that turns on / off the voltage change circuit and the signal line is on / off, and when the input voltage is a predetermined threshold voltage, the output logic is reversed to control the first switch / A closed logic circuit, and a differential voltage holding circuit that maintains a voltage slightly equal to the threshold voltage of the foregoing logic circuit and a differential voltage of the voltage of the input signal, and the differential voltage that is to hold the differential voltage holding circuit, When it is set in the differential voltage holding circuit, one end of the differential voltage holding circuit is set to a threshold threshold voltage setting circuit which is slightly equal to the threshold voltage of the logic circuit, and the differential terminal of the differential voltage holding circuit is to be maintained. The voltage is set before the differential voltage holding circuit. National Standard (CNS) A4 Specification (210 X 297 mm) · 8---------------------- 丨 Order --------- (Please Read the precautions on the back before filling in this page) 476854 One: Λ, B7 V. Description of the invention (6) The input voltage setting circuit that sets the other end of the aforementioned differential voltage holding circuit to the voltage of the aforementioned input signal is a feature By. In addition, the liquid crystal display device of the present invention is provided with a pixel line formed in a pixel array portion formed on a transparent substrate. The signal line and the scanning line are formed vertically and horizontally, and pixel electrodes are arranged near the intersection of the lines. A pixel array unit, and a liquid crystal display of a scanning line driving circuit formed on the transparent substrate and driving the signal line, and a scanning line driving circuit formed on the transparent substrate and driving the scanning line In the device, the aforementioned signal line driving circuit is a load driving circuit having a plurality of input signals including inputting a predetermined voltage amplitude, and supplying the voltage of this input signal to a signal line connected to a pixel electrode in order to change the voltage of the aforementioned signal line. When the supply circuit is changed, and the conduction between the voltage change circuit and the signal line is turned on / off as a first switch, and when the input voltage is at a predetermined threshold voltage, the output logic is inverted to control the first 1 on / off logic circuit, and a voltage that remains slightly equal to the aforementioned threshold voltage of the aforementioned logic circuit and the aforementioned input signal When the differential voltage holding circuit of the differential voltage of the voltage and the differential voltage to be held in the differential voltage holding circuit are set in the differential voltage holding circuit, one end of the differential voltage holding circuit is set to be slightly equal to the aforementioned logic. Threshold voltage and threshold voltage setting circuit of the circuit, and set the differential voltage of the differential voltage holding circuit to be set before the differential voltage holding circuit, and set the other end of the differential voltage holding circuit to The load driving circuit of the input voltage setting circuit of the aforementioned input signal voltage. (Please read the precautions on the back before filling out this page) 'i 111 --- ^ · I ------. Printed on paper scales of the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economic Affairs, China National Standard (CNS) A4 Specifications (210 X 297 public love) -9- 476854 A7 B7 V. Description of the invention (7) [Simplified description of the picture] · (Please read the notes on the back before filling this page) Figure 1 shows the details of the invention The circuit configuration diagram of the signal amplifier circuit of the first embodiment. FIG. 2 is a schematic block diagram of the circuit inside each section of FIG. 3. FIG. FIG. 3 shows the internal structure of a signal, signal line, and driver circuit of a liquid crystal display device to which the present invention is applied. Fig. 4 is a timing chart showing the overall configuration of a liquid crystal display device to which the present invention is applied. Fig. 5 is a timing chart illustrating the operation of the {§ number amplifier circuit of the first embodiment shown in Fig. 1. Fig. 6 is a diagram showing a circuit configuration of a signal amplification circuit according to a second embodiment of the present invention. FIG. 7 is a flowchart showing the operation of the signal amplifier circuit according to the second embodiment shown in FIG. 6. FIG. FIG. 8 is a circuit configuration diagram showing a signal amplifier ®-circuit according to a third embodiment of the present invention. Fig. 9 is a flowchart showing the operation of the signal amplifier circuit according to the second embodiment shown in Fig. 6; Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 10 is a circuit diagram showing a signal amplifier circuit related to the fourth embodiment of the present invention. < FIG. 11 is a diagram showing a circuit configuration of a signal amplification circuit according to a fifth embodiment of the present invention. _ Fig. 1 2 shows a flowchart for explaining the operation of the fifth embodiment @ signal amplifier circuit shown in Fig. 1 ° Fig. 1 3 shows the signal amplifier related to the sixth embodiment of the present invention ------ --- This paper size applies the Chinese National Standard (CNS) A4 specification (21 × 297 mm) -10-Printed by the Consumers' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 476854-·---B7 V. Description of the invention (β) -. · ./.· '.-Circuit configuration diagram of the circuit. Fig. 14 is a diagram showing a circuit configuration of a signal amplifier circuit according to a seventh embodiment of the present invention. Fig. 15 is a flowchart showing the operation of the signal amplifier circuit according to the seventh embodiment shown in Fig. 14; Fig. 16 is a circuit diagram showing a signal amplifier circuit according to an eighth embodiment of the present invention. Fig. 17 is a flowchart for explaining the operation of the signal amplifier circuit of the eighth embodiment shown in Fig. 6; Fig. 18 is a circuit diagram showing a signal amplifier circuit according to a ninth embodiment of the present invention. Fig. 19 is a circuit diagram showing a signal amplifier circuit according to the tenth embodiment of the present invention. Fig. 20 is a flowchart showing the operation of the signal amplification circuit of the tenth embodiment-* .1 shown in Fig. 19. Fig. 2 is a circuit diagram showing an example of a circuit configuration of a logic circuit for amplitude increase used in the present invention (the 11th embodiment). Fig. 2 is a circuit diagram of the 12th embodiment showing the structure of a main part of a load driving circuit. *-Figure 2 3 is a block diagram showing the overall structure of a load drive circuit. Fig. 24 is a diagram for explaining the operation of a load driving circuit for a positive polarity and a load driving circuit for a negative polarity. Fig. 25 is a timing chart of each part in the load driving circuit of the 12th embodiment. This paper size applies to China National Standard (CNS) A4 specification (210 X 297 meals) -11. M V I --- ---- I--I ---- Ί I --- ^ ---- ---- I ------------- (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 476854.: A7 B7 V. Description of the Invention (9) Fig. 26 is a detailed circuit diagram showing the load driving circuit for the negative polarity of the 12th embodiment. Fig. 2 is a circuit diagram of the 13th embodiment of the load driving circuit. Fig. 28 is a timing chart of one of the parts in the load driving circuit of the 13th embodiment. * 'Fig. 29 is a circuit diagram showing the detailed structure of the load driving circuit for the negative polarity of the 13th embodiment. Fig. 30 is a circuit diagram showing a modification of the load driving circuit for the positive polarity of the 13th Binsch form. ^ \ Fig. 31 is a circuit diagram showing a modification of the load driving circuit for the negative polarity of the thirteenth embodiment. Fig. 3 is a circuit diagram of the 14th embodiment of the load driving circuit. Fig. 3 is a timing chart of each part in the load driving circuit of the fourteenth embodiment. ·. ~ '--.. · Fig. 34 is a circuit diagram showing the detailed structure of the load driving circuit for the negative polarity of the 14th embodiment. Fig. 35 is a circuit diagram showing a modified example of the load driving circuit for the positive polarity of the fourteenth embodiment. Fig. 36 is a circuit diagram showing a modified example of the load driving circuit for the negative polarity of the fourteenth embodiment. Fig. 37 is a circuit diagram of the 15th embodiment of the load driving circuit. Fig. 38 is a timing chart of each part in the load driving circuit of the 15th embodiment. Figure 3 9 shows the load driven by the negative polarity of the 15th embodiment. The paper size applies the Chinese National Standard (CNS) A4 (210 X 297 mm) -12-----% V I .--- II ----— Install ---- I --- — Order ..::;. · (Please read the notes on the back before filling this page)

476854 A7 •_ B7 _____ 五、發明說明（1〇 ) 電路之詳細構成電路圖。· (請先閱讀背面之注意事項再填寫本頁) 圖4 0係顯示第1 5實施形態之正極性用之負荷驅動 電路之變形例之電路圖。 ： 圖4 1係顯示第1 5賓施形態之負極性用之負荷驅動 電路之變形例之電路圖。/ 圖4 2係負荷驅動電路之第1 6實施形態之電路圖。 圖4 3係第1 6實施形態之負荷驅動電路內之各部之 定時圖。 ' 圖4 4係顯示第1 6實施形態之負極性用之負荷驅動 電路之詳細構成電路圖。 圖4 5係顯示第1 6實施形態之正極性用之負荷驅動 電路之變形例之電路圖。 圖4 6係顯示第1 6實施形態之負極性用之負荷驅動 電路之變形例之電路圖。 一 圖4 7係顯示負荷驅動電路之主要部之構成的第1 7 實施形態之電路圖。 圖4 8係顯示負荷驅動電路整體之構成的方塊圖。 經濟部智慧財產局員工消費合作社印製 圖4 9係爲說明正極性用之負荷驅動電路和負極性之 負荷驅動電路之動作區分圖。 < 圖5 0係第1 7實施形態之負荷驅動電路內之各部之 定時圖。 圖5 1係顯示第1 7實施形態之負極性用之負荷驅動 電路之詳細構成電路圖。 圖5 2係負荷驅動電路之第1 8實施形態之電路圖。 -13 - 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐） 476854 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（11) 圖5 3係第1 8實施形態之負荷驅動電路內之各部之 定時圖。 · ; 圖5 4係顯示第1 8實施形態之負極性用之負荷驅動 電路之詳細，成電路圖。 【符號說明】 1 薄 膜 電 晶 體 2 畫 素 陣 列部 - 3 * 信 號 線 驅 動 電 路 4 掃 猫 線 驅 動 電 路 1 〇 定 時 控 制 電 路 1 2 數 位 資 料取 樣 部 1 2 a 信 號 增 幅 電 路 1 2 b 取 樣 閂 鎖 電 路 1 4 •數 位 資 料 載 入 部 1 4 a 載 入 閂 鎖 電 路 1 6 數 位 類 比 變 換 部 1 6 a 數 位 類 比 變 換 電 路 1 8 數 位 資 料 匯 流排 線 2 0 振 幅 增 幅 用 邏 輯 電路 2 0 a 反相 器 2 0 b 反 相 器 3 0 信 號 增 幅 電 路 3 2 信 號 增 幅 電 路 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐） -14- — .11 ^ I---- ----I--訂--------- (請先閱讀背面之注意事項再填寫本頁) 476854 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（12) 34 信號增幅電路 36 信號增幅電路‘ 3 8 信號增幅電路 40 信號增幅電路 4 2 信號增幅電路 4 4 信號增幅電路 46 信號增幅電路 1 1 1 a負荷驅動電路·（正極性） 1 1 1七負荷驅動電路(·負極性） 112 開關切換控制電路 113 邏輯電路· 2 1 1 a負荷驅動電路（正極性） 2 1 1 b負荷驅動電路（負極性） 2 1 2 開關 切 換 控制電 路 2 1 3 邏輯 電 路 2 1 4 前段 反 相 器 2 1 5 後段 反 相 器 S 1 S η 信 號 線 G 1 G m掃瞄線 E C S 外部 輸 入 影像信 號 C S 控制 信 號 S W 1 S W 6 · 開關 C 1 C 3 電 容 器 I S 輸入 信 號 <請先閱讀背面之注意事項再填寫本頁) i—丨丨丨訂---------· 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐） -15- 476854 A7 B7 五、發明說明（13) 0 S 輸出信號· V 1 基準電壓 ；- T 1〜T 5 時刻 a〜b 節點 經濟部智慧財產局員工消費合作社印製 Q 1 Q 1 0 電晶 體 C N 取消端子 T 1 1 丁 1 7 時刻 C N R 反轉取消 端子 T 2 1 T 2 7 時刻 T 3 1 T 3 7 時刻 T G 1 T G 3 轉換閘 丁 4 1 丁 4 7 時刻 丁 5 1 T 2 7 時刻 T 6 1 丁 6 7 時刻 Q 2 0 Q 2 6 電晶體 Q 3 0 Q 3 6 電晶體^ V i η 輸入 .影像信號 S 信號線 S W 1 0 1 S W 10 7 開 Q 1 〇 1 Q 10 4 電晶 am 體 C 1 0 1 C 10 4 電容 器 R 阻抗 V D D 第1 之電壓 V D 第2 之電壓 ---- I-------裝 il • - (請先閱讀背面之注意事項本頁) 訂·· --線- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -16- 4 5 8 6 7476854 A7 • _ B7 _____ V. Description of the Invention (10) The detailed circuit diagram of the circuit. · (Please read the precautions on the back before filling out this page) Figure 40 is a circuit diagram showing a modified example of the load driving circuit for the positive polarity of the 15th embodiment. : Figure 41 is a circuit diagram showing a modified example of the load driving circuit for the negative polarity of the 15th Binsch form. / Fig. 4 2 is a circuit diagram of the 16th embodiment of the load driving circuit. Fig. 4 is a timing chart of each part in the load driving circuit of the sixteenth embodiment. 'Fig. 4 is a circuit diagram showing a detailed configuration of a load driving circuit for a negative polarity according to the sixteenth embodiment. Fig. 45 is a circuit diagram showing a modified example of the load driving circuit for the positive polarity of the sixteenth embodiment. Fig. 46 is a circuit diagram showing a modified example of the load driving circuit for the negative polarity of the sixteenth embodiment. Fig. 4 is a circuit diagram of the 17th embodiment showing the structure of the main part of the load driving circuit. Fig. 48 is a block diagram showing the overall structure of the load driving circuit. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 4 9 is a diagram illustrating the operation of a positive load driver circuit and a negative load driver circuit. < Fig. 50 is a timing chart of each part in the load driving circuit of the seventeenth embodiment. Fig. 51 is a circuit diagram showing the detailed structure of a load driving circuit for a negative polarity of the 17th embodiment. Fig. 5 is a circuit diagram of the eighteenth embodiment of the load driving circuit. -13-This paper size is in accordance with Chinese National Standard (CNS) A4 (210x297 mm) 476854 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (11) Figure 5 3 is the 18th embodiment Timing chart of each part in the load driving circuit. Fig. 54 is a detailed circuit diagram showing the load driving circuit for the negative polarity of the eighteenth embodiment. [Symbol description] 1 Thin film transistor 2 Pixel array section-3 * Signal line driver circuit 4 Cat line driver circuit 1 〇 Timing control circuit 1 2 Digital data sampling section 1 2 a Signal amplifier circuit 1 2 b Sampling latch circuit 1 4 • Digital data loading section 1 4 a Loading latch circuit 1 6 Digital analog conversion section 1 6 a Digital analog conversion circuit 1 8 Digital data bus line 2 0 Logic circuit for amplitude increase 2 0 a Inverter 2 0 b Inverter 3 0 Signal Amplifier Circuit 3 2 Signal Amplifier Circuit This paper size applies to China National Standard (CNS) A4 (210x297 mm) -14- — .11 ^ I ---- ---- I- -Order --------- (Please read the notes on the back before filling out this page) 476854 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (12) 34 Signal amplifier circuit 36 Signal Amplifier circuit '3 8 signal amplifier circuit 40 signal amplifier circuit 4 2 signal amplifier circuit 4 4 signal amplifier circuit 46 Signal amplifier circuit 1 1 1 a load drive circuit (positive polarity) 1 1 1 seven load drive circuit (negative polarity) 112 switch control circuit 113 logic circuit 2 1 1 a load drive circuit (positive polarity) 2 1 1 b Load driving circuit (negative polarity) 2 1 2 Switching control circuit 2 1 3 Logic circuit 2 1 4 Front-stage inverter 2 1 5 Rear-stage inverter S 1 S η Signal line G 1 G m Scan line ECS External Input image signal CS control signal SW 1 SW 6 · Switch C 1 C 3 Capacitor IS input signal < Please read the precautions on the back before filling this page) i— 丨 丨 丨 Order --------- · This paper size applies the Chinese National Standard (CNS) A4 specification (210x297 mm) -15- 476854 A7 B7 V. Description of the invention (13) 0 S output signal · V 1 reference voltage;-T 1 ~ T 5 time a ~ b Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Node Economy Q 1 Q 1 0 Transistor CN Cancel Terminal T 1 1 ding 1 7 Time CNR Reverse Cancel Terminal T 2 1 T 2 7 Time T 3 1 T 3 7 Time T G 1 TG 3 Switching gate 4 1 Ding 4 7 Time D 5 1 T 2 7 Time T 6 1 D 6 7 Time Q 2 0 Q 2 6 Transistor Q 3 0 Q 3 6 Transistor ^ V i η Input. Image Signal S Signal line SW 1 0 1 SW 10 7 Open Q 1 〇1 Q 10 4 transistor am C 1 0 1 C 10 4 capacitor R impedance VDD first voltage VD second voltage ---- I-- ----- Installation il •-(Please read the note on the back page first) Order ·· ----This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) -16- 4 5 8 6 7

五、發明說明（14 ) - Τ 1 〇 1 〜丁 1 0. 6 時刻 丁 1 1 1、丁 1 1 6 時刻 丁 G 轉換閘 Q 1 3 1 〜Q 1 3 2 電晶體 IV 反相器.. 經濟部智慧財產局員工消費合作社印V. Description of the invention (14)-T 1 〇1 ~ Ding 1 0. 6 time Ding 1 1 1, Ding 1 1 6 Ding G switch Q 1 3 1 ~ Q 1 3 2 transistor IV inverter .. Printed by Consumers Cooperative of Intellectual Property Bureau, Ministry of Economic Affairs

【第1實施形態】 本發明之第1實施形態係將信號增幅電路內之振幅增 幅用邏輯電路之臨限値電壓的參差，經由以電蓉器加以吸 收地，於振幅增幅用邏輯電路之臨限値電壓有參差之時， 可使信號增幅電路正常地加以動作者。以下，根據圖面加 以詳細說明。 首先，根據圖4，說明有關本實施形態之驅動電路一 體型之液晶顯不裝置之榻體性電路構成。如示於此圖4， - —- 液晶顯示裝置係具備畫素陣列部2，和信號線驅動電路3 ，和掃瞄線驅動電路4所構成。於畫素陣列部2中，信號 線S 1〜S η和掃瞄線G 1〜G m形成呈縱橫，於此等交 點附近，設置畫素顯示用之T F T 1。信號線驅動電路3 係驅動信號線S 1〜S η之電路。於本實施形態|，於此 信號線驅動電路3，直接地輸入保持數位元信號之影像信 號。掃瞄線驅動電路4係驅動各掃瞄線G 1〜G m的電路 〇 接著，根據圖2及圖3，說明有關本實施形態之信號 線驅動電路3之構成。圖3係顯示有關本實施形態之N段 .張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱^""" - 17-" in II — — — — — — 1— ^ · I I * ...... (請先閱讀背面之注意事項本頁) -.線- 476854 A7 B7 經濟部智慧財產局員工消費合作社印制衣 五、發明說明（15) 之信號線驅動電路}之本體性構成的槪略方塊圖，圖2係 各段之電路內部之槪略方塊檲。 如圖3所示，信號線驅動電路3係具備定時控制電路 1 0和數位資料取樣部1 2和數位資料載入部1 4和數位 類比變換部1 6加以構成，於此定時控制電辑'1 0和數位 資料取樣部1 2和數位資料載入部1 4和數位類比變換部 1 6中，於此等之間輸入爲控制傳送資料之定時的外部輸 入控制信號E C S。 …… 定時控制電路1 0係爲控制凡段之方塊中之何者方塊 爲自外部輸入數位資料匯流排線1 8取樣數位資料的電路 。自定時控制電路1 0係控制此定時之控制信號C S，輸 出至數位資料取樣部1 2。數位資料取樣部1 2係根據此 控制信號C S，自外部輸入數位資料匯流排線1 8，取樣 數位信號。即，有N段之數位資料取樣部1 2之各段根據 控制信號C S，順序地自外部輸入數位資料匯流^線1 8 ，將做爲影像信號之數位元信號做爲數位資料加以取樣。 數位資料載入部1 4係具有自數位資料取樣部1 2置 入數位資料’暫時加以收容的功能。即，於各段順序置入 數位資料取樣部1 2之影像信號的數位元資料係|所定之 定時，一齊地傳送至數位資料載入部1 4加以收容。收容 於此數位資料載入部1 4之數位資料係將來自數位資料載 入部1 4置入的數位資料，變換呈類比資料9 即，於圖3所示之信號線驅動電路3中，做爲自外部 輸入之影像信號的數位元信號係在於資料取樣部1 2被增 請 先 閱 讀 背 面 之 注 意 事 項 裝 頁 訂 線 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 18- 4 5 8 ir^·· 47 κι — Β7___ 五、發明說明（16 ) *7! — — ! Ji t ·1 {請先閱讀背面之注意事項本頁) 幅之下，做爲數位資料一時性地加以保存，·之後，於每所 定之時間，此數位資料係移動至資料載入部1 4。然後， 以數位類比變換部1 6，於每所定之時間，將數位資料變 換爲類比資料之影像信號，輸出至信號線s 1〜S η ◊ .如圖2所示，.對此液晶顯示裝’置之1信線，於外部 輸入數位資料匯流排線1 8，設置1對之數位信號線。此 等之數位信號線係連接於1對之數位信號線。此等之數位 信號線係連接於數位資料取樣部12，〜數位資料取樣部 1 2係於各信號線具備信號增幅電路1 2 a和取樣閂鎖電 路1 2 b。於此等信號增幅電路1 2 a和取樣問鎖電路 1 2 b中，自定時控制電路1 〇輸入控制信號C S。又， 數位資料載入部1 4係於各信號線具備載入閂鎖電路 1 4 a ，數位類比變換部1 6係於各信號線具備數位類比 變換電路1 6 a。 --線- 經濟部智慧財產局員工消費合作社印製 示於圖2及圖3之各部係形成於示於圖4之^晶顯示 裝置之同一玻璃基板上。又，構^示於圖4之信號驅動電 路3或掃瞄線驅動電路4的電晶體係經由與畫素驅動用之 T F T 1同樣之製造步驟加以形成。 接著，根據圖1 ，說明有關本實施形態之信增幅電 路1 2 a之構成。此圖1係說明本發明之基本槪念，顯示 信號增幅電路1 2 a之主要部分構成的電路圖。 如圖1所示，有關本實施形態之信號增幅電路1 2 a 係具備開關SW1、和開關SW2、和電容器Cl、和振 幅增幅用邏輯電路2 0加以構成。振幅增幅用邏輯電路 -19 - 本紙張尺度適用中國國家標準（CNtS)a4規格（21〇 X 297公釐） 476854 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（17 ) - 2 0係經由直列地連接反相器2 0 a V 2 0 b加以構成。 信號增幅電路1· 2 a係增先振幅小之數位信號的輸入信號 I S的振幅，做爲數位信號之輸出信號〇 s加以輸出之電 路。 . 更詳細而言，開關S W 1之一端側係連接_於輸入端子 ，輸入輸入信號I S。此輸入信號I s係自數位資料匯流 排線1 8之振幅小的數位信號。本實施形態中，輸入信號 I S係以4 V〜6 V之寬度振幅之數位信號。開關SW 1 之另端側係連接於開關S W 2之一端側。於此開關S W 2 之另端側輸入基準電壓V 1。本實施形態之中，將此基準 電壓VI設定呈5 V。即，輸入信號I S之振幅爲4V〜 6 V之故，將該中4 V〜5 V呈高和低之切換基準的電壓[First Embodiment] The first embodiment of the present invention is a method of dividing the threshold voltage of a logic circuit for amplitude amplification in a signal amplifier circuit and the voltage difference through the electric circuit to absorb the ground. When there is a difference in the threshold voltage, it can make the signal amplifier circuit operate normally. Hereinafter, it will be described in detail based on the drawings. First, the circuit configuration of the liquid crystal display device of the integral type of the driving circuit of this embodiment will be described with reference to FIG. As shown in FIG. 4, the liquid crystal display device includes a pixel array unit 2, a signal line driving circuit 3, and a scanning line driving circuit 4. In the pixel array section 2, the signal lines S 1 to S η and the scanning lines G 1 to G m form a vertical and horizontal direction, and T F T 1 for pixel display is set near these intersections. The signal line driving circuit 3 is a circuit that drives the signal lines S 1 to S η. In this embodiment, the signal line driver circuit 3 directly inputs an image signal holding a digital signal. The scanning line driving circuit 4 is a circuit that drives each of the scanning lines G1 to Gm. Next, the configuration of the signal line driving circuit 3 according to this embodiment will be described with reference to Figs. 2 and 3. Figure 3 shows the N segment of this embodiment. The Zhang scale is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 public love ^ " " "-17- " in II — — — — — — 1 — ^ · II * ...... (Please read the note on the back page first)-. Thread-476854 A7 B7 Printed clothing by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Signal line of invention description (15) Figure 2 is a schematic block diagram of the main structure of the driving circuit}. Figure 2 is a schematic block diagram of the internal circuit of each segment. As shown in Figure 3, the signal line driving circuit 3 is provided with a timing control circuit 10 and a digital data sampling section. 12 and the digital data loading unit 14 and the digital analog conversion unit 16 are configured, and here the timing control album '1 0 and the digital data sampling unit 1 2 and the digital data loading unit 1 4 and the digital analog conversion unit 1 In 6, among them, an external input control signal ECS for controlling the timing of transmitting data is inputted .... The timing control circuit 1 0 is for controlling which of the blocks in each segment is a digital data bus 1 for external input. 8-sampling digital data circuit. Self-timing control circuit 10 series The control signal CS for producing this timing is output to the digital data sampling section 12. The digital data sampling section 12 is based on the control signal CS, and the digital data bus line 18 is externally input to sample the digital signal. That is, there are N segments Each segment of the digital data sampling section 12 sequentially inputs a digital data bus ^ 8 from the outside according to the control signal CS, and samples the digital signal as an image signal as digital data. Digital data loading section 1 Series 4 has the function of temporarily inserting digital data from the digital data sampling section 12 and storing it temporarily. That is, the digital data of the video signal of the digital data sampling section 12 is sequentially placed in each section. Sent to the digital data loading section 14 for containment. The digital data contained in this digital data loading section 14 is the digital data placed from the digital data loading section 14 and converted into analog data 9 ie, as shown in the figure In the signal line driving circuit 3 shown in 3, the digital signal as the image signal input from the outside is in the data sampling section 1 2 is added, please read the precautions on the back first. The size of the paper is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) 18- 4 5 8 ir ^ ·· 47 κι — Β7 ___ V. Description of the invention (16) * 7! — —! Ji t · 1 {Please read the note on the back page first), save it as digital data for a while, and then, at each set time, this digital data is moved to the data loading section 14. Then, the digital analog conversion unit 16 converts the digital data into the video signal of the analog data at a predetermined time, and outputs the digital signal to the signal lines s 1 to S η 如图. As shown in FIG. 'Set a 1-line, input the digital data bus line 18 to the outside, and set up a pair of digital signal lines. These digital signal lines are connected to a pair of digital signal lines. These digital signal lines are connected to the digital data sampling section 12, and the digital data sampling section 12 is provided with a signal amplifier circuit 12a and a sampling latch circuit 12b for each signal line. In these signal amplifying circuits 12a and sampling interlocking circuits 12b, the self-timing control circuit 10 inputs a control signal CS. The digital data loading unit 14 includes a loading latch circuit 14a on each signal line, and the digital analog conversion unit 16 includes a digital analog conversion circuit 16a on each signal line. --Line- Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Each department shown in Figs. The transistor system of the signal driving circuit 3 or the scanning line driving circuit 4 shown in Fig. 4 is formed through the same manufacturing steps as the pixel driving T F T 1. Next, the configuration of the letter-amplifying circuit 12a according to this embodiment will be described with reference to FIG. This FIG. 1 is a circuit diagram illustrating the basic idea of the present invention, and the main part of a display signal amplifier circuit 12a is constructed. As shown in FIG. 1, the signal amplification circuit 12a according to this embodiment is configured by including switches SW1, SW2, and capacitors Cl, and a logic circuit 20 for amplitude amplification. Logic circuit for amplitude increase-19-This paper size applies Chinese National Standard (CNtS) a4 specification (21 × 297 mm) 476854 Printed by A7 B7, Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of invention (17)-2 0 is configured by connecting the inverters 20 a V 2 0 b in series. The signal amplification circuit 1 · 2a is a circuit for increasing the amplitude of an input signal IS of a digital signal having a small amplitude first, and outputting the digital signal as an output signal 0 s. In more detail, one end of the switch S W 1 is connected to the input terminal and an input signal I S is input. This input signal Is is a digital signal with a small amplitude from the digital data bus line 18. In this embodiment, the input signal I S is a digital signal having a width of 4 V to 6 V. The other end side of the switch SW 1 is connected to one end side of the switch SW 2. A reference voltage V 1 is input to the other end of the switch S W 2. In this embodiment, the reference voltage VI is set to 5 V. That is, the amplitude of the input signal I S is 4V to 6 V, so that 4 V to 5 V is a reference voltage for switching between high and low.

G 於開關s w 2和開關s W 1之間，連接電容器C 1之 一端側。此電容器C 1係於節點a和節點b間，i保持振 幅增幅用邏輯電路2 0之臨限値電壓和基準電壓V 1的差 分電壓的元件者。即，經由電容器C1 ，構成有關本實施 形態之基準電壓保持電路。.電容器C 1之共他端側係連接 於反相器2 0 a之輸入側。此反相器2 0 a之輸取側係連 接於反相器2 0 b之輸入側。此反相器2 0 b之輸出側係 連接於輸出端子，自此輸出端子輸出輸出信號〇 S。輸出 信號0 S係增大輸入信號I S之振幅的數位信號。本實施 形態中，此輸出信號〇S係以0 V〜1 〇 V之寬度加以振 幅的數位信號者。. 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -20 - -------------! ^ Ί — W 、請先Μ讀背面之注意事項本頁) 訂： .線· 476854 A7 ____— B7 __ 五、煢明說明（18 ) 本實施形態之中，·振幅增幅用邏輯電路2 〇係絕緣閘 極型邏輯電路，經由多結晶矽型之薄膜電晶體加以構成。 接著，根據圖5，說明示於圖丨之信號增幅電路 1 2 a之動作的定時圖。 .如圖5所示，時刻T 1〜時刻τ 2之間，·呈，重置期間 。即，此時刻T 1〜時刻T 2之期間，對於圖3之信號線 驅動電路3內之某一段方塊而言，自定時控制電路1〇送 出控制信號C S。由此，示於圖】之僧號增幅電路1 2 a 之開關S W 1呈開啓狀態，開關S W 2則呈關閉狀態。於 此時刻Τ 1〜時刻T 2間，於節點a做爲基準電壓V 1， 輸出5 V。又，與此同時，經由某種手段，令節點b設定 呈振幅增幅用邏輯電路2 0之臨限値電壓。例如，振幅增 幅用邏輯電路2 0之臨限値電壓呈4 · 5 V之時，將節點 b設定呈4 · 5V。因此，電容器C1中，蓄存 —0 · 5 V之電壓。此振幅增幅用邏輯電路2 01臨限値 電壓係於每方塊產生參差，又，k每製品亦產生參差。於 如此各不同之臨限値電壓中，設定節點b之手段則述於後 者。 、 經濟部智慧財產局員工消費合作社印制取 接著，時刻T 2〜時刻T 4之間，呈資料取期間。 即，此時刻T 2〜時刻T 4之期間，定時控制電路1 0係 將開關S W 1呈關閉狀態，開關S W 2則呈開啓狀態。爲 此，輸入信號I S則輸入至節點a。例如，輸入信號I S 自4 V變化6 V時，節點a則自5 V變化至6 V。此時， 電容器C1中，蓄存一0·5V之電壓之故，節點b則自 -21 - illj-lll — — — — — — ^ rll· {請先閱讀背面之注辛ί事項本I) •線· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 476854 A7 B7 五、發明說明（19 ) ----------------裝 i — *· (請先閱讀背面之注意事項本頁) 4 · 5 V變化至5 · 5。在此振幅增幅用邏輯電路2 〇 之臨限値電壓係爲4 . 5 Υ之故，振幅增幅用邏輯電路 2 0之輸出信號0 S係於時刻Τ 3，自Ο V變化至1 〇 V 。即，於超過輸入信號I S做爲基準電壓1 V設定之，5 V 的時劑Τ 3的時點，振幅增幅用邏輯電路2 0Γ之輸出信號 〇S則自〇 V向1 0 V變化。 接著，時刻T 4〜時刻T 5之間，呈資料保持期間。 即，此時刻丁 4〜時刻丁 5之期間，定時控制電路1 〇係 將開關S W 1和開關S W 2之兩者開關呈關閉狀態者。由 此，於先前之貪料取樣期間（時刻T 2〜時刻T 4 )之間 ，將輸入振幅2 V之數位信號的輸入信號I S，做爲振幅 1 0 V之數位信號的輸出信號〇 S加以保持輸出。 •線· 然而，通常做爲暫時資料保持之方法，倂用圖所示之 取樣閂鎖電路1 2 b。於此時之取樣閂鎖電路1 2 b中， 使用例如觸發電路、或資料保持用之容量元件。~ 經濟部智慧財產局員工消費合作社印製 經由重覆上述之動作，輸入信號I S之數位信號係於 圖3所示之每方塊之1段，至N段之方段加以取樣《於此 後之所定期間，此等取樣之數位信號係於數位資料載入部 1 4 一齊地加以移動，再度根據定時控制電路1 之控制 信號控制信號C S，以數位資料取樣部1 2順序進行數位 資料之取樣。 向數位資料載入部1 4移動之數位資料係平行於上述 資料取樣期間（時刻T 2〜時刻T 4之期間），於數位類 比變換部1 6 —齊娛換呈類比之影像信號，輸出信號線 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） .22- 476854 A7 B7 經濟部智慧財產局員工消費合作社印製G is connected between one end of the capacitor C 1 between the switch sw 2 and the switch s W 1. The capacitor C 1 is a component between the node a and the node b, and i maintains the differential voltage between the threshold voltage of the logic circuit 20 for the amplitude increase and the reference voltage V 1. That is, the reference voltage holding circuit according to this embodiment is constituted via the capacitor C1. The common side of the capacitor C 1 is connected to the input side of the inverter 20 a. The input side of this inverter 20a is connected to the input side of inverter 20b. The output side of this inverter 2 0 b is connected to an output terminal, and an output signal is outputted from this output terminal. The output signal 0 S is a digital signal that increases the amplitude of the input signal IS. In this embodiment, the output signal 0S is a digital signal having an amplitude of 0 V to 10 V. . This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) -20--------------! ^ Ί — W, please read the notes on the back first (This page) Order:. 476854 A7 ____— B7 __ V. Explanation (18) In this embodiment, the logic circuit for amplitude increase is a 〇 series insulated gate logic circuit. Thin film transistor is constructed. Next, a timing chart showing the operation of the signal amplification circuit 1 2 a shown in FIG. 5 will be described with reference to FIG. 5. As shown in FIG. 5, between the time T 1 and the time τ 2, a reset period is displayed. That is, from this time T1 to time T2, for a certain block in the signal line driving circuit 3 of Fig. 3, the self-timing control circuit 10 sends a control signal CS. Therefore, the switch SW 1 of the monk number amplifier circuit 1 2 a shown in the figure is on, and the switch SW 2 is off. At this time T1 to T2, the node a is used as the reference voltage V1, and 5V is output. At the same time, the threshold b of the logic circuit 20 for amplitude increase is set to the node b by some means. For example, when the threshold voltage of the logic circuit 20 for amplitude amplification is 4 · 5 V, the node b is set to 4 · 5V. Therefore, a voltage of -0.5 V is stored in the capacitor C1. This amplitude increase uses the logic circuit 2 01 threshold. The voltage is uneven for each square, and k is also uneven for each product. In such different threshold voltages, the method of setting node b is described in the latter. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Then, from time T 2 to time T 4, the period of data retrieval is presented. That is, during this time T 2 to time T 4, the timing control circuit 10 turns the switch SW 1 off, and the switch SW 2 turns on. To this end, the input signal I S is input to the node a. For example, when the input signal I S changes from 4 V to 6 V, node a changes from 5 V to 6 V. At this time, a voltage of 0.5V is stored in the capacitor C1, and the node b is from -21-illj-lll — — — — — — ^ rll · {Please read the note on the back first. Note I) • Line · This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 476854 A7 B7 V. Description of the invention (19) ---------------- 装 i — * · (Please read the caution page on the back first) 4 · 5 V changes to 5 · 5. Here, the threshold voltage of the logic circuit 20 for amplitude increase is 4.5 V. Therefore, the output signal 0 S of the logic circuit 20 for amplitude increase is changed from 0 V to 10 V at time T 3. That is, when the input signal IS is set as the reference voltage 1 V, and the time signal T 3 of 5 V is set, the output signal 0S of the amplitude increase logic circuit 20 0Γ changes from 0 V to 10 V. Next, a data retention period is shown between time T 4 and time T 5. That is, during this time T4 to T5, the timing control circuit 10 is one in which both the switches SW 1 and SW 2 are turned off. Therefore, during the previous sampling period (time T 2 to time T 4), the input signal IS of the digital signal having an amplitude of 2 V is used as the output signal of the digital signal having an amplitude of 10 V. Keep the output. • Line · However, as a temporary data retention method, the sampling latch circuit 1 2 b shown in the figure is not used. In the sampling latch circuit 12 b at this time, a capacity element such as a trigger circuit or data retention is used. ~ Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. By repeating the above actions, the digital signal of the input signal IS is sampled in the first segment of each block shown in Figure 3 to the N segment to be sampled. In the meantime, these sampled digital signals are moved together in the digital data loading section 1 4, and the digital data sampling is sequentially performed by the digital data sampling section 12 in accordance with the control signal control signal CS of the timing control circuit 1. The digital data moving to the digital data loading unit 14 is parallel to the above data sampling period (time T 2 to time T 4), and the digital analog conversion unit 1 6-Qi Yu exchanges the analog image signal and outputs the signal The paper size of the paper is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm). 22- 476854 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

五、發明說明（20) S 1〜信號S η之各列。將以上之動作，重覆自信號線驅 動電路3內之1段至η段的方塊，更且重覆掃瞄線G 1〜 掃瞄線G m行分，.而可顯示影像/ 如以上所述，根據有關本實施形態之液晶顯示裝置時 ，將信號增幅電路1 2 a設於數位資料取樣部2之故， 爲僅些微資位資料之變化的輸入信號I S，亦可加以取樣 。爲此，尤其是大型之液晶顯不裝置，或顯示色數多之數 位信號之規模大的液晶顯示裝置中.，可抑制外部電路之電 路規模，而達低消耗電力化。即，無需增大外部電路之規 模及消耗電力地，可將數位信號所動作之信號線驅動電路 3，內勘於液晶顯示裝置。 而且，將振幅增幅用邏輯電路2 0之臨限値電壓的參 差，以電容器C 1加以吸收之故，以輸入信號I s之基準 電壓VI95v)爲界境，，可將輸出信號〇s切換呈 0 V和1 ο V。β卩，於重置期間（時刻丁 1〜時T 2 ) 中，將基準電壓V 1各和振幅增幅用邏輯電路2 0之臨限 値電壓的差分電壓，經由蓄存於電容器C 1 ，將節點b設 定於振幅增幅用邏輯電路2 0之臨限値電壓。 如此地，經由設定節點b之電壓，輸入信號s自低 切換爲高之時，於輸入信號I S超過基準電壓V 1之時點 ，可將輸出信號OS自0V向10 V切換。即，於輸入信 號IS超過VI之時點，可將輸出信號os自0V向 1 0V切換。又，與此相反地，輸入信號自高向低切換之 時，輸入信號I S較V 1爲低之時點，可將輸出信號〇S (請七閱讀背面之注 意事項 本頁) 裝： -•線· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） • 23 - 54 8 6 7 A7 ____ B7 ___ 五、發明說明（21 ) 一 • — — — — — — — — — · ^ » I 1 * (請先閱讀背面之注意事項本頁) --線· 自10 V向0 V切換。·.即，輸入信號I S低於基準電壓 V 1之時點，可將輸出信號O S自1 〇 V向0 V切換。„ 又，振幅增幅用邏輯電路2 0之臨限値電壓大爲參差 不齊之時，亦可令此振幅增幅用邏輯電路2 0正常地加以 動作。即，振幅增幅用邏輯電路2 0之臨限鋒.電壓的偏移 有超過1 V之情形。例如振幅增幅用邏輯電路2 0之臨限 値呈6 . 5 V之時，例如振幅增幅用邏輯電路2 0之臨限 値電壓呈6 · 5 V之時，於以往之信號增幅電路中，於以 往之信號增幅電路中，無法以使甩4 V〜6 V之寬度振幅 的輸入信號I S，將輸出信號〇S切換爲高（1 〇 V )。 對此，有關本實施形態之信號增幅電潞1 2 a中，於重置 期間在於電容器C 1蓄存1 . 5 V，節點b之電壓設定呈 6 · 5 V之故，於資料取樣期間輸入信號I S超過5 V之 時點，節點b之電壓則超過6 · 5 V。因此，於如此之情 形時，令輸出信號0 S切換呈高（1 0 V ) 〇 ^ 【第2實施形態】 經濟部智慧財產局員工消費合作社印？衣 本發明之第2實施形態係顯示於上述第1實施形態之 電容器C 1 ，具備振幅增幅用邏輯電路2 0之臨jp：値電壓 ，和蓄存基準電壓V1之差分電壓的具體電路的信號增幅 電路1 2 a。 圖6係顯示有關本發明.之第2實施形態之信號增幅電 路之主要部分之構成的電路圖，圖7係顯示示於圖6之信 號增幅電路之動作的定時圖。 -24- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 54 8 6 7 經濟部智慧財產局員工消費合作社印$衣 A7 ________ B7 ___ 五、發明說明（.22) 如圖6所示，有關第2實施形態之信號增幅電路3 0 係加上上述有關第1實施形:態之信號增幅電路1 2 a，另 具備開關S W 3，S W 4，和P型之Μ 0 S電晶體Q 1的 構成。 .... 說明與上述第1實施形態不同之電路構两部.分特，節 點b係連接於開關S W 3之一端側。開關S W 3之另端側 係連接於0 V端子，此〇 V端子係連接於〇 V之電壓源。 又，節點b係連接於電晶體 Q 1之輸出端子/此電晶體 Q 1之輸出端子係連接於取消端子C N。此取消端子C N 中，於每1周期，施加0 V至1 0 V直線性變化的取消電 壓。電晶體Q 1之控制端子係連接於開關S W 4之一端側 。此開關S W 4之另一端側係連接於反相器2 0 b之輸出 側。 於本實施形態中，經由開關s W 1和基準電壓V 1之 電壓源，於電容器C 1構成保持差分電壓之時，k節點a 維持於基準電壓的基準電壓保持電路。又，經由開關 S W 4和電晶體Q 1和Ο V之電壓源和取消電壓之電壓源 ，於電容器C 1保持差分電壓之時，構成保持差分電壓之 時，將節點b設定於振幅增幅用邏輯電路2 0之限値電 壓的臨限値電壓檢出電路。 接著，根據圖7，說明圖6所示之之動作。首先，時 刻T 1 1〜時刻T 1 2之間，呈重置期間。即，時刻 T 1 1〜時刻T 1 2之期間，自定時控制電路1 0送出控 制信號C S。信號增幅電路3 0之開關S W 1和開關 !!·裝· I , * <請先閱讀背面之注意事項本頁： 訂· 線- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -25- 470854V. Description of the invention (20) Each column of S 1 to signal S η. Repeat the above operations from the 1st to η segments in the signal line drive circuit 3, and repeat the scanning line G1 ~ scanning line Gm, and the image can be displayed / as shown above In the liquid crystal display device according to this embodiment, the signal amplification circuit 12a is provided in the digital data sampling section 2, so that the input signal IS can be sampled even if it has only a few microdata changes. For this reason, especially in large-scale liquid crystal display devices or large-scale liquid crystal display devices that display digital signals with a large number of colors, the circuit scale of external circuits can be suppressed and power consumption can be reduced. That is, without increasing the size of the external circuit and the power consumption ground, the signal line driving circuit 3 operated by the digital signal can be internally surveyed in the liquid crystal display device. In addition, the difference in the threshold voltage of the logic circuit 20 for amplitude increase is absorbed by the capacitor C 1, and the reference signal VI s (reference voltage VI95v) is used as the boundary to switch the output signal 0s to 0 V and 1 ο V. β 卩, during the reset period (time T1 to T2), the difference voltage between the reference voltage V 1 and the threshold voltage of the amplitude increase logic circuit 20 is stored in the capacitor C 1, and The node b is set at the threshold voltage of the amplitude increase logic circuit 20. In this way, when the input signal s is switched from low to high by setting the voltage of the node b, the output signal OS can be switched from 0V to 10V when the input signal IS exceeds the reference voltage V1. That is, when the input signal IS exceeds VI, the output signal os can be switched from 0V to 100V. On the contrary, when the input signal is switched from high to low, when the input signal IS is lower than V 1, the output signal can be set to 0S (please read the precautions on the back page). · This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) • 23-54 8 6 7 A7 ____ B7 ___ V. Description of the invention (21) I ^ »I 1 * (Please read the note on the back page first) --Wire · Switch from 10 V to 0 V. That is, when the input signal IS is lower than the reference voltage V 1, the output signal OS can be switched from 10 V to 0 V. „When the threshold value of the logic circuit 20 for amplitude increase is large and uneven, the logic circuit 20 for amplitude increase can be operated normally. That is, the logic circuit 20 for amplitude increase Limiting. The voltage may shift more than 1 V. For example, when the threshold value of logic circuit 20 for amplitude increase is 6.5 V, for example, the threshold voltage of logic circuit 20 for amplitude increase is 6 · At 5 V, in the conventional signal amplifier circuit, in the conventional signal amplifier circuit, it is impossible to switch the output signal 0S to high (1 0V) with the input signal IS with a width of 4 V to 6 V. In this regard, in the signal amplification circuit 2 12a related to this embodiment, during the reset period, the capacitor C 1 stores 1.5 V, and the voltage setting of the node b is 6 · 5 V, so the data is sampled. When the input signal IS exceeds 5 V during this period, the voltage at node b exceeds 6.5 V. Therefore, in such a case, the output signal 0 S is switched to high (1 0 V) 〇 ^ [Second Embodiment] Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs? The signal amplifier circuit 1 2 a is a capacitor C 1 shown in the above-mentioned first embodiment, and includes a logic circuit 20 for amplitude amplification, a jp voltage, a differential voltage, and a differential voltage storing a reference voltage V1. FIG. 6 It is a circuit diagram showing the structure of the main part of the signal amplification circuit according to the second embodiment of the present invention, and FIG. 7 is a timing chart showing the operation of the signal amplification circuit shown in FIG. 6. -24- This paper scale is applicable to China Standard (CNS) A4 Specification (210 X 297 mm) 54 8 6 7 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ________ B7 ___ 5. Description of the invention (.22) As shown in Figure 6, the second implementation The signal amplifier circuit 3 0 of the form is in addition to the signal amplifier circuit 12 a of the first embodiment described above: the signal amplifier circuit 1 2 a of the state, and also has switches SW 3, SW 4, and a P-type M 0 S transistor Q 1. ... Explain the two parts of the circuit structure different from the first embodiment described above. Decitex, the node b is connected to one end of the switch SW 3. The other end of the switch SW 3 is connected to the 0 V terminal, which is the 0 V terminal. Is connected to a voltage source of 0 V. Also, node b is The output terminal connected to transistor Q 1 / the output terminal of transistor Q 1 is connected to the cancel terminal CN. In this cancel terminal CN, a cancel voltage that varies linearly from 0 V to 10 V is applied every one cycle. The control terminal of the transistor Q 1 is connected to one end side of the switch SW 4. The other end side of the switch SW 4 is connected to the output side of the inverter 2 0 b. In this embodiment, via the switches s W 1 and The voltage source of the reference voltage V 1 is a reference voltage holding circuit that maintains the k-node a at the reference voltage when the capacitor C 1 forms a differential voltage. In addition, through the switch SW 4 and the voltage source of the transistors Q 1 and 0 V and the voltage canceling voltage source, when the capacitor C 1 holds the differential voltage and when the differential voltage is held, the node b is set to the logic for amplitude increase. Threshold voltage threshold voltage detection circuit for circuit 20. Next, the operation shown in FIG. 6 will be described with reference to FIG. 7. First, between the time T 1 1 and the time T 1 2, there is a reset period. That is, from time T 1 1 to time T 1 2, the self-timing control circuit 10 sends a control signal CS. Switch SW 1 and switch of signal amplifier circuit 3 0 !! · Installation · I, * < Please read the note on the back page first: Order · Line-This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) -25- 470854

經濟部智慧財產局員工消費合作社印制衣 五、發明說明（？3 ) S W 3呈開啓狀態，開關S W 2和開關S W 4則呈關閉狀 態。此時刻T 1· 1〜時刻T“ 1 2期間，於節點a做爲基準 電壓V 1，例如輸入5 V。又，周時，節點b輸入Ο V。 下個時刻T 1 2〜時刻T 1 4之間，呈臨限値取消期 間。於時刻T 1 2〜時刻T 1 4之期間，定時择制電路 1 0係將開關S W 1和開關S W 4呈開啓狀態，開關 S W 2和開關S W 3則呈開閉狀態。結果，電晶體Q 1呈 開啓狀態。於此時刻T 1 2〜時刻T 1.4之1周期之期間 ，取消端子C N係自Ο V變化至10¥。結果，開關 S W 1呈開啓狀態之故，保持節點a之基準電壓V 1 ( 5 V )，節點b之電壓則自〇 V變化至1 〇 V。然後，節 點b超過振幅增幅用邏輯電路2 0之臨限値電壓之例如 4 · 5 V之時點，於時刻T 1 3反轉振幅增幅用邏輯電路 2 0之輸出。結果，振幅增幅用邏輯電路2 0之輸出信號 〇S則呈1 〇 V，電晶體Q 1係呈關閉狀態。由此，節點 b爲反轉振幅增幅用邏輯電路2 0之輸出邏輯的輸出信號 〇S的電壓，設定呈4 . 5 V。即，節點b設定呈振幅增 幅用邏輯電路2 0之臨限値電壓。爲此，電容器C 1中， 蓄存—0 .. 5 V。 < 下個時刻T 1 4〜時刻T 1 6之間，呈資料取樣期間 。即’此時刻T 1 4〜時刻T 1 6之期間，定時控制電路 1 〇係將開關S W 2呈開啓狀態，開關S W 1和開關 5 W 3和開關S W 4則呈開閉狀態。爲此，於節點a輸入 輸入信號I S。例如，輸入信號I S自4 V變化6 V時， • I 1 ---------111 t 11 * <請先閱讀背面之注意事項本頁) 灯· -•線· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公餐） -26- 476854 A7 B7 五、發明說明（24)Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (? 3) S W 3 is on, and switches S W 2 and S W 4 are off. During this time T 1 · 1 ~ time T 1 2, the node a is used as the reference voltage V 1, for example, 5 V is input. Also, weekly, the node b is input 0 V. The next time T 1 2 to time T 1 Between 4 is a threshold limit cancellation period. Between time T 1 2 and time T 1 4, the timing selection circuit 1 0 turns on the switches SW 1 and SW 4, and switches SW 2 and SW 3 It turns on and off. As a result, the transistor Q 1 turns on. During the period from time T 1 2 to time T 1.4, the cancellation terminal CN changes from 0 V to 10 ¥. As a result, the switch SW 1 is turned on. Because of the state, the reference voltage V 1 (5 V) of the node a is maintained, and the voltage of the node b is changed from 0 V to 10 V. Then, the node b exceeds the threshold of the amplitude increase logic circuit 20 threshold voltage, for example At 4 · 5 V, the output of the logic circuit 20 for amplitude increase is reversed at time T 1 3. As a result, the output signal 0S of the logic circuit 20 for amplitude increase is 10V, and the transistor Q1 is The off state. Therefore, the node b is the voltage of the output signal 0S of the output logic of the logic circuit 20 for inverting amplitude amplification, The setting is 4.5 V. That is, the node b sets the threshold voltage of the logic circuit 20 for amplitude increase. For this reason, the capacitor C 1 stores -0 .. 5 V. < Next time T 1 Between 4 and time T 1 6 is the data sampling period. That is, 'this time T 1 4 to time T 1 6, the timing control circuit 10 is to turn on the switch SW 2 and the switches SW 1 and 5 W 3 and switch SW 4 are on and off. To do this, input the input signal IS at node a. For example, when the input signal IS changes from 4 V to 6 V, • I 1 --------- 111 t 11 * < Please read the note on the back page first) Lamp ··· Line · This paper size is applicable to China National Standard (CNS) A4 (210 X 297 meals) -26- 476854 A7 B7 V. Description of the invention (24)

做爲基準電壓1 V設定之5 V的境界，輸出信號〇 S則自 Ο V向1 Ο V變化。此因卜於電容器C1蓄存一 0 · 5 V |11!|1 丨•裝 i I 鬌 {請先閱讀背面之注意事項本頁) 之故，於輸入信號1 s呈5 V之時刻T 1 5之時點’節點 b之電壓係呈5 V + (- 0 · 5 V ) = 2 · 5 V ’筚過振 幅增幅用邏輯電路2 0之臨限値電壓的4 · 5 。爲此’ 振幅增幅用邏輯電路2 0之輸出信號0 S則自〇 V變化至 1 0 V。 -線. 下個時刻τ 1 6〜時刻T 1 7之期間，呈資料保持期 間。即，時刻T 1 6〜時刻T 1 7之期間，定時控制電路 1 0係令開關S W 1〜s W 4呈關閉狀態。於此時刻 丁 1 6〜時刻Τ 1 7期間，將輸入於資料取樣期間（時刻 丁 1 4〜時刻Τ 1 6 )之間的振幅2 V之數位信號的輸入 信號I S .，做爲振幅1 0 V之數位信號之輸出信號〇S， 暫時性地加以保持。然而，此信號增幅電路3 0以外之動 作係與上述第1實施形態相同。 經濟部智慧財產局員工消費合作社印製 如以上所述，將有關本實施形態之信號增幅電路3 0 使用信號線驅動電路3，可不增大外部電路之規模及消耗 電力地，可呈以數位信號動作之信號線驅動電路3。 更且，·有關本實施形態之液晶顯示裝置之信_._落增幅電 路3 0時，此信號線驅動電路內之元件特性則爲參差，振 幅增幅用邏輯電路2 0之臨限値電壓則於每方塊或每製品 不同之時’可進行振幅小之輸入信號I S之數位信號之取 樣。即，振幅增幅用邏輯電路2 0之臨限値電壓有參差之 時，將此信號增幅電路30可正常動作。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） .27- 476854 經濟部智慧財產局員工消費合作社印^^ A7 B7 ___ 五、發明說明（ 25 ) 【實施形態3】 本發明之第3實施形態係變形上述第2實施形態之節 點a之臨限値取消期間的基準電壓之保持手法者^以、下， 根據圖面詳細地加以說明。 圖8係顯示有關本發明之第3實施形態之信號增幅電 路之主要部之構成的電路圖，圖9係顯示示於信號增幅電 路之動作的定時圖。 如圖8所示，有關第3實施形態之信號增幅電路3 2 係加上上述有關第2實施形態之信號增幅電路3 〇，另具 備開關S W 5，和電·容器C 2，和P型之Μ〇S電晶體 Q 2的構成。 說明與上述第2實施形態不同之電路構成部分時’於 開關S W 2，和開關S W 1間之節點a中，連接電容器 C 2之一端側。電容器C 2之另端側係連接於開~關S W 5 之一端側。開關S W 5之另端側係連接於1 〇 V端子’此 1 0 V端子係連接於1 〇V之電壓源。又，電容器C 2之 另一端側係έΐ接於電晶體 Q 2之輸出端子。此電晶體 Q2之輸入端子係連接於反轉取消端子CNR反轉取 消端子CNR中，於每1周期，施加10V至0V直線性 變化的取消電壓。電晶體Q 2之控制端子係連接於開關 S W 4之一端側。此開關S W 4之另一端側係連接於反相 器2 0 b之輸出側。 於本實施形態中，經由開關S W 4、S W 5和電晶體 {請先閱讀背面 之注意事項 本'Iw-' 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） •28- 476854 A7 B7 五、發明說明（26) !!丨！ •裝 '1 I * (請先閱讀背面之注意事項本頁) Q 2和電容器C 2和10 V之電壓源和反轉取消電壓之電 壓源，於電容器C 1構成保持差分電壓之時，將節點a維 持於基準電壓的基準電壓保持電路。又，經由開關S W 4 和電晶體Q 1和0 V之電壓源和取消電壓之電壓源，於電 容器C 1保持差分電壓之時，構成將節點b聲定於信號增 幅用邏輯電路2 0之臨限値電壓的臨限値電壓檢出電路。 接著，根據圖9，說明圖8所示信號增幅電路3 2之 動作。首先，時刻丁 2 1〜時刻T 2 2之間，呈重置期間 。即，時刻T 2 1〜時刻丁 2 2之期間，自定時控制電路 1 0送出控制信號C S。信號增幅電路3 0之開關S W 1 和開關S W 3和開關S W 5呈開啓狀態，開關S W 2和開 關S W 4則呈關閉狀態。此時刻丁 2 1〜時刻T 2 2期間 ，於節點a做爲基準電壓V 1 ，例如輸入5 V。又，與此 之同時於節點b輸入0 V，於節點C輸入1 〇 V。 · i線· 經濟部智慧財產局員工消費合作社印製 下個時刻T 2 2〜時刻T 2 4之間，呈臨限it取消期 間。於時刻T 2 2〜時刻T 2 4之期間，定時控制電路 1 〇係將開關S W 4呈開啓狀態，將除此之外之開關的開 關S W 1〜開關S W 3和開關S W 5呈關閉之狀態。結果 ’電晶體Q 1和電晶體Q 2則呈開啓狀態。於此時 T 2 2〜時刻T 2 4之期間，取消端子C N係自〇 V變化 至1 0 V。爲此，節點b係自0 V向1 〇 V加以變化。又 ’反轉取消端子C N R係自1 0 V向〇 V變化。爲此，節 點c係自1 〇 v向0 V加以變化。結果，節點a之電壓係 保持於基準電壓V 1 ( 5 V )。然後，節點b超過振幅增 -29- 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 476854 B7 五、發明說明（27) 幅用邏輯電路2 0之臨限値電壓之例如4 · 5 V之時點， 於時刻T 2 3反轉振幅增鼷用邏輯電路2 0之輸出。結果 ’振幅增幅用邏輯電路2 0之輸出信號0 S則呈1 〇 V， 電晶體Q Γ和電晶體Q 2係呈關閉狀態。由此，節點b爲 反轉振幅增幅用邏輯電路2 0之輸出邏輯的轉·出信號〇S 的電壓，設定呈4 · 5 V。即，節點b設定呈振幅增幅用 邏輯電路2 0之臨限値電壓。另一方面，節點c係設定呈 1 Ο V — 4 · 5 V (節點 b 之電壓）=5.5V。 下個時刻Τ 2 4〜時刻Τ 2 6之間，呈資料取樣期間 。即，此時刻Τ 2 4〜時刻Τ 2 6之期間，定時控制電路 1 0係將開關S W 2呈開啓狀態，開關S W 1和開關 S W 3〜S W 5則呈關閉狀態。爲此，於節點a輸入輸入 信號I S。例如，輸入信號I S自4 V變化6 V時，做爲 基準電壓V 1設定之5 V的境界，輸出信號〇S則自〇V 向1 Ο V變化。即輸入信號I S呈5 V之時刻T 2 5之時 點，節點b之電壓係超過振幅增幅用邏輯電路2 0之臨限 値電壓的4 · 5 V之故，振幅增幅用邏輯電路2 0之輸出 信號〇S則自〇 V變化至1 〇 V。 下個時刻T 2 6〜時刻丁 2 7之期間，呈資|保持期 間。即，時刻T 2 6〜時刻T 2 7之期間，定時控制電路 1 0係令開關S W 1〜S W 5呈關閉狀態。於此時刻 T 2 6〜時刻T 2 7期間，將輸入於漬料取樣期間（時刻 T 2 4〜時刻T 2 6 )之間的振幅2又之數位信號的輸入 信號I S，做爲振幅1 0 V之數位信號之輸出信號〇s， 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -30- 1!!·裝 i I <請先閱讀背面之注意事項本頁) 上0· 經濟部智慧財產局員工消費合作社印製 476854 A7 B7 五、發明說明（28 ) 暫時性地加以保持。然而，此信號增幅電路3 0以外之動 作係與上述第1實施形態相祠。 如以上所述*將有關本實施形態之信號增幅電路3 2 使用信號線驅動電路3，可不增大外部電路之規模及消耗 電力地，可呈以數位信號動作之信號線驅動電路:3。 裝 更且，有關本實施形態之液晶顯示裝置之信號增幅電 路3 2時，此信號線驅動電路內之元件特性則爲參差，振 幅增幅用邏輯電路2 0之臨限値電壓則於每方塊或每製品 不同之時，可進行振幅小之輸入信號I S之數位信號之取 樣。即，振幅增幅用邏輯電路2 0之臨限値電壓有參差之 時，仍可將此信號增幅電路30正常動作。 訂 【實施形態4】 本發明之第4實施形態係變形上述第3實施形態之節 點a之臨限値取消期間的基準電壓之保持手法者以下， 根據圖面詳細地加以說明。 " 經濟部智慧財產局員工消費合作社印製 圖1 0係顯示有關本發明之第4實施形態之信號增幅 電路之主要部之構成的電路圖。 如圖1 0所示，有關第4實施形態之信號增ip良電路 3 4係加上上述有關第3實施形態之信號增幅電路3 2， 另具備電容器C 3加以構成。說明與上述第3實施形態不 同之電路構成部分時，於節點a中，蓮接電容器C 3之一 端側。此電容器C 3之另端側係連接於保持電壓V 2。此 實施形態中，做爲保持電壓施加0 V，但爲固定電壓時任 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） Γβΐ - " ： 麵 4 5 8 6. 7 A7 ________ B7 _____ 五、發明說明（?9) 何伏特皆可。 於本實施形態中，經由《開關S W 4、S W 5和電晶體 Q 2和電容器C 2、C 3和1 Ο V之電壓源和反轉取消電 壓之電壓源和保持電壓V 2之電壓源，於電容器C1構成 保持差分電壓之時，將節點a維持於基準電聲的基準電壓 保持電路。 而有關本實施形態之信號增幅電路3 4之動作係與上 述有關第3實施形態之信號增幅電路3 2同樣之故，省略 該說明。 如此，經由於節點a附加電容器C 3地’於圖9所示 臨限値取消期間（時刻T 2 1〜時刻T 2 2 ) ’可將節點 a之電壓易於保持於5 V。即，於重置期間（時刻T 2 1 〜時刻T 2 2 )之間，於此之例中，於電容器C 3蓄積 5 V之電壓之故，臨限値取消期間之間，可容易地將節點 a保持於5 V 〇 【第5實施形態】 經濟部智慧財產局員工消費合作社印剎衣 本發明之第5實施形態係變形上述第4實施形態之信 號增幅電路3 4之電晶體切換手法者。以下，根篝圖面詳 細地加以說明。 圖1 1係顯示有關本發明之第5實施形態之信號增幅 電路3 6之主要部之構成的電路圖，圖1 2係顯示示於圖 1 1之信號增幅電路3 6之動作的定時圖。 如圖1 1所示，有關第5實施形態之信號增幅電路 -32- --------------- ·! 曹 (請先閱讀背面之注意事項本頁) --線· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 4 5 8 6; 7 A7 —_ B7 ___ 五、煢明說明（3〇) ^- — — — — — — — — — — 1« ^ . I I <請先閱讀背面之注意事項本頁) 3 6係於有關上述第4賓施形態之信號增幅電路3 4中， 代替P型之MOS電晶體之屬晶體Q1，設置η型之 Μ〇S電晶體之電晶體Q 3的同時，具備開關S W 6加以 構成。 說明與上述第4實施形態不同之電路構成:部分時，電 晶體Q 3之控制端子係連接於開關S W 6之一端側。開關 S W 6之另端側係連接於振幅增幅用邏輯電路2 0之反相 器2 0 a之輸出側。 於本實施形態中，經由開關S W 6和電晶體Q 3和 0 V之電壓源，於電容器C 1構成保持差分電壓之時，構 成將節點b維設定於振幅增幅用邏輯電路2 〇之臨限値電 壓的臨限値電壓檢出電路。 •線· 經濟部智慧財產局員工消費合作社印製 接著，根據圖1 2，說明圖1 1所示信號增幅電路 3 6之動作。首先，時刻丁 3 1〜時刻T3 2之間，呈重 置期間。即，時刻T 3 1〜時刻丁 3 2之期間，i定時控 制電路1 0送出控制信號C S，信號增幅電路3 〇之開關 S W 1和開關S W 3和開關S W 5呈開啓狀態，開關 S W 2和開關S W 4和開關S W 6則呈關閉狀態。此時刻 T 3 1〜時刻T 3 2期間，於節點a做爲基準電擧v丄， 例如輸入5 V。爲此，於電容器c 3蓄積$ v之電壓。又 ’與此之同時於節點b輸入〇v，於節點c輸入1 〇V。 下個時刻T 3 2〜時刻丁 3 4之間，呈臨限値取消期 間。於時刻T 3 2〜時刻T 3 4之期間，定時控制電路 1 0係將開關S W 4和開關s W 6呈開啓狀態，將除此之 33- 476854 ' A7 _- _ B7 五、發明說明（31 ) 外之開關的開關S W· 1/〜開關S W 3和開關s W 5呈關閉 之狀態。結果，電晶體Q h和電晶體Q 3則呈開啓狀態。 於此時刻丁 3 2〜時刻T 3 4之期間，取消端子C N係自 0 V變化至1 0 V。爲此，節點b係自0 V向1 〇 V加以 變化。又，反轉取消端子C N R係自1 Ο V向〇 V變化。 爲此，節點c係自1 〇 v向〇 V加以變化。結果，節點a 之電壓係保持於基準電壓V 1 ( 5 V )。然後，於節點b 超過振幅增幅用邏輯電路2 0之臨限値電壓之例如 4 · 5 V之時點的T 3 3，反轉振幅增幅用邏輯電路2 〇 之輸出。 經濟部智慧財產局員工消費合作社印製 - — — — — — — — — — — · I I C請先閲讀背面之注意事項本頁) -線. 結果，自反相器2 0 b輸出之振幅增幅用邏輯電路 2 0之輸出信號〇S則呈1 〇 V，電晶體Q 1係呈關閉狀 態。又，自反相器2 0 a輸出之信號呈0 V，電晶體Q 3 諂呈關閉狀態。由此，設定呈節點b爲反轉振幅增幅用邏 輯電路2 0之輸出邏輯的輸出信號〇S的電壓的^ . 5 V 。即，節點b設定呈振幅增幅用邏輯電路2 〇之臨限値電 壓。爲此，於電容器C1蓄存差分電壓之一 〇 β 5V。另 一方面，節點c係設定呈l〇V_4 · 5V (節點b之電 壓）=5 · 5 V。 — j· 下個時刻T 2 4〜時刻丁 2 6之間，呈資料取樣期間 。即，此時刻T 3 4〜時刻T 3 6之期間，定時控制電路 1 0係將開關S W 2呈開啓狀態，開關S W 1和開關 5 W 3〜S W 6則呈關閉狀態。爲此，於節點a輸入輸入 信號I S。例如，輸入信號I S自4 V變化6 V時，做爲 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 34 476854 A7 B7 五、發明說明（32 ) 基準電壓V 1設定之5 V的境界，輸出信號0 S則自Ο V 向1 Ο V變化。即輸入信號I S呈5 V之時刻T 3 5之時 點’節點b之電壓係超過振幅增幅甩邏輯電路2 0之臨限 値電壓的4 · 5 V之故，振幅增幅用邏輯電路2 0之輸出 信號〇S則自0 V變化至1 〇 V。 ·：. 裝 訂 下個時刻丁 3 6〜時刻T 3 7之期間，呈資料保持期 間。即，時刻丁 3 6〜時刻T 3 7之期間，定時控制電路 1 0係令開關S W 1〜S W 6呈關閉朕態。於此時刻 T 3 6〜時刻T 3 7期間，將輸入於資料取樣期間（時刻 丁 3 4〜時刻T 3 6 )之間的振幅2 V之數位信號的輸入 信號I S，做爲振幅1 Ο V之數位信號之輸出信號03, 暫時性地加以保持。然而，此信號增幅電路3 0以外之動 作係與上述第1實施形態相同。 如以上所述，將有關本實施形態之信號增幅電路3 6 使用信號線驅動電路3，可不增大外部電路之規 >莫及消耗 電力地，可呈以數位信號動作之ί言號線驅動電路3 ^ 經濟部智慧財產局員工消費合作社印製 更且，根據有關本實施形態之液晶顯示裝置之信號增 幅電路3 6時，此信號線驅動電路內之元件特性爲參差， 振幅增幅用邏輯電路2 0之臨限値電壓則於每方或每製 品不同之時，可進行振幅小之輸入信號I S之數位信號之 取樣。即，振幅增幅用邏輯電路2 0之臨限値電壓有參差 之時，仍可將此信號增幅電路3 6正常動作。 又，經由於節點a附加電容器C 3地，於圖1 2所示 臨限値取消期間（時刻τ 3 2〜時刻T 3 4 )，可將節點 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -35 - 五、發明說明（33) • — |!1 裝，！ « (請先閱讀背面之注意事項本頁) a之電壓易於保持於5 v。即，於重置期間（時刻丁 3 1 〜時刻T 3 2 )之間，於此έ例中，於電容器C 3蓄積 5 V之電壓之故，臨限値取消斯間之間，可容易地將節點 a保持於5 V。 【第δ實施形態】 本發明之第6實施形態係代替上述第5實施形態之電 晶體Q 2、Q 3，設置轉換閘者。以下，根據圖面加以詳 細說明。 圖1 3係顯示有關本發明之第6實施形態之信號增幅 電路之主要部之構成·的電路圖。 --線- 經濟部智慧財產局員工消費合作社印製 如圖1 3所示，有關第6實施形態之信號增幅電路 3 8係代替有關上述第5實施形態之信號增幅電路3 6之 電晶體Q 2、Q 3，具備轉換閘T G 1、T G 2加以構成 。說明與上述第5實施形態不同之電路構成部分S#，於節 點b連接轉換閘T G 1。此轉換閘T G 1係由η型之 Μ〇S電晶體的電晶體Q 4，和Ρ型之電晶體的電晶體 Q 7所構成。於節點c連接轉換閘T G 2。此轉換閘 T G 2係由η型之Μ 0 S電晶體的電晶體Q 5，|CL ρ型之 電晶體的電晶體Q 6所構成。 於本實施形態中，經由開關S W 4、S W 5、S W 6 和轉換閘T G 2和電容器C 2和1 Ο V之電壓源和反轉取 消電壓之電壓源，於電容器C1保持差分電壓之時，構成 將節點a維持於基準電壓保持電路。又，經由開關S W 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -36 - 476854 A7 B7 五、發明說明（ 34) 7,-—ί —----- 丨丨！裝·ί 請先閱讀背面之注意事項本頁) 、S W 6和轉換閘丁 G 1和Ο V之電壓源和取消電壓之電 壓源，於電容器C Ί保持盖分電壓之時，構成將節點b設 定於振幅增幅用邏輯電路2 〇之臨限値電壓的臨限値電壓 檢出電路。 然而，有關本實施形態之信號增幅電路3. 8之動作係 與有關上述之第5實施形態之信號增幅電路3 6同樣之故 ，省略該說明。 【第7實施形態】 . ' - 本發明之第7實施形態係變形上述第2乃至第6實施 形態之電容器C. 1之差分電壓設定之手法者。以下，根據 圖面詳細地加以說明。 ;線- 圖1 4係顯示有關本發明之第7實施形態之信號增幅 電路之主要部之構成的電路圖，圖1 5係顯示示於圖1 4 之信號增幅電路之動作的定時圖。 經濟部智慧財產局員工消費合作社印製 如圖1 4所示，有關第7實施形態之信號增幅電路 4 0係較上述第3實施形態時，另外設置p型之MO S電 晶體的電晶體Q 8加以構成。 說明與上述第3實施形態不同之電路構成部.兔時，於 電容器C 1之一端側和電容器c 2之一端側間，連接電晶 體Q 8。此電晶體Q 8之控制端子係連接於開關S W 4之 一端側。此開關S W 4之另一端側係連接於反相器2 0 b 之輸出側。 於本實施形態中，經由開關s W 4、S W 5和電晶體 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公餐） -37 476854 經濟部智慧財產局員工消費合作社印^^ A7 _ B7 ___五、發明說明（35) Q 8和電容器C 2和χ 〇 v之電壓源，於電容器C 1構成 保持差分電壓之時，將節黠a維持於基準電壓的基準電壓 保持電路。又，經由開關S W 3〜S W 5和電晶體Q 8和 0V之電壓源和1 〇v之電壓源，於電容器c i保持差分 電懕之時，構成將節點b設定於信號增幅用邏\輯電路2 0 之臨限値電壓的臨限値電壓檢出電路。 接著’根據圖1 5，說明圖1 4所示信號增幅電路 4 0之動作。首先，時刻T 4 1〜時刻丁 4 2之間，呈重 置期間。即，時刻丁 4 1〜诗刻T 4 2之期間，自定時控 制電路1 0送出控制信號C S，信號增幅電路4 0之開關 5 W 1和開關S W 3和開關S W 5呈開啓狀態，開關 S W 2和開關S W 4則呈關閉狀態。此時刻T 4 1〜時刻 T 4 2期間，於節點a做爲基準電壓V 1 ，例如輸入5 V 。又，與此之同時於節點b輸入〇 V，於節點C輸入 1 0 V 〇 — 下個時刻T 4 2〜時刻T 4 4之間，呈臨限値取消期 間。於時刻T 4 2〜時刻T 4 4之期間，定時控制電路 1 0係將開關S W 1〜S W 3和開關S W 5呈關閉狀態， 將開關S W 4呈開啓之狀態。結果，電晶體Q 8|開啓狀 態。於此時刻T 4 2〜時刻T 4 4之期間，電容器C 1和 電容器C 2係透過此電晶體Q 8加以短路。爲此，節點b 係自0 V向1 0 V加以變化。然後，於節點b超過振幅增 幅用邏輯電路2 0之臨限値電壓之例如4 . 5 V之時點的 時刻T 4 3，反轉振幅增幅用邏輯電路2 0之輸出，輸出 • 111111 — — — — — — — ^ · I I <請先閱讀背面之注意事項本頁) 上0· •線- 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -38- 476854 A7 B7 五、煢明說明（36 ) 1!1!·裝 — {請先閱讀背面之注意事項本頁) 信號〇S呈1 〇 V。爲此，電晶體Q 8係呈關閉狀態I結 果’節點b係設定呈反轉振幅增幅用邏輯電路2 〇之輸出 邏輯電壓之臨限値電壓。即，於電容器C Ί蓄存振幅增幅 用邏輯電路2 0之臨限値電壓和基準電壓V 1之5 V的差 分電壓。即，本實施形態中，於電容器C 1蓄靖.. 一 0 · 5 V之電壓。 --線- 下個時刻丁 4 4〜時刻T 5 6之間，呈資料取樣期間 。即，此時刻丁 4 4〜時刻丁 4 6之期間，定時控制電路 1 0係將開關S W 2呈開啓狀態，此外之開關S W之開關 S W 1和開關S W 3〜S W 5則呈關閉狀態。於此時間 T 4 4〜時刻T 4 6之期間。例如，輸入信號I S自4 V 變化至6 V。此時，做爲基準電壓V 1設定之5 V的境界 ，於時刻T 4 5之時點，振幅增幅用邏輯電路2 0之輸出 信號〇S則自0 V向1 〇 V變化。即輸入信號I S超過 5 V之時刻T 4 5，節點b之電壓係超過振幅增ijf用邏輯 電路2 0之臨限値電壓的4 · 5 V。因此，振幅增幅用邏 輯電路2 0之輸出信號〇 S則自低切換至高。 經濟部智慧財產局員工消費合作社印製 下個時刻T 4 6〜時刻T 4 7之期間，呈資料保持期 間。EP，時刻T 4 6〜時刻T 4 7之期間，定時择制電路 1 0係令開關S W 1〜S W 5呈關閉狀態。於此時刻 T 4 6〜時刻T 4 7期間，將輸入於資料取樣期間（時刻 T4 4〜時刻T4 6 )之間的振幅2V之數位信號的輸入 信號I S，做爲振幅1 0 V之數位信號之輸出信號〇 S， 暫時性地加以保持。然而’此信號增幅電路4 0以外之動 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -39 · 476854 A7 B7 五、發明說明（37 ) 作係與上述第1實施形態相同。 •^ — 1 — ! — — — — — — · ^ Μ I (請先閲讀背面之注意事項本頁) 如以上所述，將有關本實施形態之信號增幅電路4 0 使用信號線驅動電路3，可不增大外部電路之規模及消耗 電力地，可呈以數位信號動作之信號線驅動電路3。 更且，有關本實施形態之液晶顯示裝置之信號增幅電 路4 0時，此信號線驅動電路內之元件特性則爲參差，振 幅增幅用邏輯電路2 0之臨限値電壓則於每方塊或每製品 不同之時，可進行振幅小之輸入信號I S之數位信號之取 樣。即，信號增幅用邏輯電路2 0之臨限値電壓有參差之 時，仍可將此信號增幅電路4 0正常動作。 【第8實施形態】 -•線- 本發明之第8實施形態係變形上述第7實施形態之電 容器C 1之差分電壓設定之手法者。以下，根據圖面詳細 地加以說明。 * 經濟部智慧財產局員工消費合作社印製 圖1 6係顯示有關本發明之第8實施形態之信號增幅 電路之主要部之構成的電路圖，圖1 7係顯示示於圖1 6 之信號增幅電路之動作的定時圖。 於本實施形態中，經由開關S W 1和基準電隊V 1之 電壓源，於電容器C 1構成保持差分電壓之時，將節點a 維持於基準電壓的基準電壓保持電路。又，經由開關 SW3〜SW5和電晶體Q8和0V之電壓源和10V之 電壓源，於電容器C 1保持差分電壓之時，構成將節點b 設定於信號增幅用邏輯電路2 0之臨限値電’壓的臨限値電 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -40 - 476854 A7 — B7 _ 五、發明說明（38 ) 壓檢出電路。 、 「 •I-------------^ -1 — (請先閱讀背面之注意事項本··!) 如圖1 6所示，有關第名實施形態之信號增幅電路 4 2係較上述第7實施形態，省略電容器C 2加以構成。 接著，根據圖1 5，說明圖1 6所示信號增幅電路 4 2之動作。首先，時刻T 5 1〜時刻T 5 2/之間，呈重 置期間。即，時刻T 5 1〜時刻T 5 2之期間，自定時控 制電路1 0送出控制信號C S，信號增幅電路4 0之開關 5 W 1和開關s W 3和開關S W 5呈開啓狀態，開關 S W 2和開關S W 4則呈關閉狀態。此時刻丁 51〜時刻 T 5 2期間，於節點a做爲基準電壓V 1，例如輸入5 V 。又，與此之同時於節點b輸入〇 V，於節點C輸入 1 0 V。 下個時刻T 5 2〜時刻T 5 4之間，呈臨限値取消期 間。即於時刻T 5 2〜時刻T 5 4之期間，定時控制電路 --線. 經濟部智慧財產局員工消費舍作社印製 1 0係將開關S W 2和開關S W 3和開關S W 5 i關閉狀 態，將開關S W 1和開關S W 4呈開啓之狀態。結果，電 晶體Q 8呈開啓狀態。於此時刻丁 5 2〜時刻T 5 4之期 間，電容器1和電容器C 2係透過此電晶體Q 8加以短 路。又，開關S W 1呈開啓狀態之故，節點a之雾壓係維 持於基準電壓V 1之5V。爲此，節點a之電壓保持於 5 V，節點b之電壓自〇 V向1 〇 V加以變化。然後，於 節點b超過振幅增幅用邏輯電路2 0之臨限値電壓之例如 4 . 5 V之時點的時刻T 5 3，反轉振幅增幅用邏輯電路 2 0之輸出，輸出信號0S呈1 0V。爲此，電晶體Q8 -41 - 本纸張尺度適用中國國家標準（CNS)A4規格（210x297公釐） 476854 A7 r-------—__ B7 五、發明說明（39 ) 係呈關閉狀態。結果，、節點b係設定呈反轉振幅增幅用邏 輯電路2 0之輸出邏輯電恶之臨限値電壓。即，於電容器 C 1蓄存振幅增幅用邏輯電路2 〇之臨限値電壓和基準電 壓V 1之5 V的差分電壓。即，本實施形態中，於電容器 C 1蓄積一 〇 · 5 V之電壓。 ^ ；. 下個時刻T 5 4〜時刻T 5 6之間，呈資料取樣期間 。即，於時刻丁 5 4〜時刻T 5 6中，定時控制電路1 〇 係將開關S W 2呈開啓狀態，此外之開關s W之開關 S W 1和開關S W 3〜S W 5則呈關閉狀態。於此時間As the boundary of 5 V set by 1 V of the reference voltage, the output signal 0 S changes from 0 V to 1 0 V. This is because the capacitor C1 stores a 0 · 5 V | 11! | 1 丨 • Install i I 鬌 {Please read the precautions on the back page first), at the time T 1 when the input signal is 5 V At 5 o'clock, the voltage at node 'b' is 5 V + (-0 · 5 V) = 2 · 5 V ', which is the threshold of the voltage of the logic circuit 20 for the amplitude increase of 4 · 5. To this end, the output signal 0 S of the logic circuit 20 for amplitude increase changes from 0 V to 10 V. -Line. During the period from the next time τ 1 6 to time T 1 7, the presentation period is held. That is, during the period from time T 1 6 to time T 1 7, the timing control circuit 10 causes the switches SW 1 to SW 4 to be turned off. At this time from Ding 16 to T 1 7, the input signal IS. Of the digital signal with an amplitude of 2 V which is input between the data sampling period (time D 1 to T 1 6) is taken as the amplitude 1 0 The output signal 0S of the digital signal of V is temporarily held. However, operations other than this signal amplifier circuit 30 are the same as those of the first embodiment. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, as described above, the signal amplifier circuit 3 related to this embodiment is used. The signal line drive circuit 3 can be used to increase the size of the external circuit and the power consumption. Operation of the signal line drive circuit 3. In addition, the letter about the liquid crystal display device of this embodiment _._ When the amplifier circuit is 30, the characteristics of the components in the signal line drive circuit are uneven, and the threshold voltage of the logic circuit 20 is used for the amplitude increase. The sampling of the digital signal of the input signal IS with a small amplitude can be performed at a time when each block or product is different. That is, when the threshold voltage of the amplitude increase logic circuit 20 varies, the signal increase circuit 30 can operate normally. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm). 27- 476854 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ^^ A7 B7 ___ V. Description of the invention (25) The third embodiment of the invention is a modification of the method of maintaining the reference voltage during the threshold threshold of the node a in the second embodiment described above, and the details are described below with reference to the drawings. Fig. 8 is a circuit diagram showing a configuration of a main part of a signal amplification circuit according to a third embodiment of the present invention, and Fig. 9 is a timing chart showing the operation of the signal amplification circuit. As shown in FIG. 8, the signal amplifier circuit 3 2 of the third embodiment is added with the signal amplifier circuit 3 of the second embodiment described above, and it further includes a switch SW 5 and an electric container C 2 and a P-type Composition of MOS transistor Q 2. A description will be given of a circuit component different from the above-mentioned second embodiment. At the node a between the switch SW 2 and the switch SW 1, one end of the capacitor C 2 is connected. The other end side of the capacitor C 2 is connected to one end side of the on-off SW 5. The other end of the switch SW 5 is connected to a 10 V terminal. This 10 V terminal is connected to a 10 V voltage source. The other end of the capacitor C 2 is connected to the output terminal of the transistor Q 2 by hand. The input terminal of this transistor Q2 is connected to the reverse cancellation terminal CNR. The reverse cancellation terminal CNR applies a cancellation voltage with a linear change of 10V to 0V every one cycle. The control terminal of transistor Q 2 is connected to one end of switch S W 4. The other end side of the switch SW 4 is connected to the output side of the inverter 2 0 b. In this embodiment, via switches SW 4, SW 5 and transistors {Please read the precautions on the back of this "Iw-" This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) • 28 -476854 A7 B7 V. Description of the Invention (26) !! 丨! • Install '1 I * (Please read the caution page on the back first) Q 2 and capacitor C 2 and 10 V voltage source and reverse cancellation voltage voltage source. When capacitor C 1 forms a differential voltage, it will The node a is maintained in a reference voltage holding circuit of a reference voltage. In addition, through the switch SW 4 and the voltage source of the transistor Q 1 and 0 V and the voltage source canceling the voltage, when the capacitor C 1 maintains a differential voltage, the node b sound is constituted to be near the signal amplification logic circuit 20. Threshold voltage threshold voltage detection circuit. Next, the operation of the signal amplifier circuit 32 shown in Fig. 8 will be described with reference to Fig. 9. First, between time D 2 and T 2 2, there is a reset period. In other words, from time T 2 1 to time D 22, the self-timing control circuit 10 sends a control signal CS. The switches SW1, SW3, and SW5 of the signal amplifier circuit 30 are turned on, and the switches SW2 and SW4 are turned off. At this time T 2 1 to T 2 2, the reference voltage V 1 is used at the node a, for example, 5 V is input. At the same time, 0 V is input to node b and 10 V is input to node C. · I-line · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs The next time between T 2 2 and T 2 4 is the cancellation period of it. Between time T 2 2 and time T 2 4, the timing control circuit 10 turns on the switch SW 4, and turns off the switches SW 1 to SW 3 and SW 5 of the other switches. . As a result, the transistor Q 1 and the transistor Q 2 were turned on. During the period from T 2 2 to T 2 4 at this time, the cancellation terminal CN is changed from 0 V to 10 V. For this reason, the node b is changed from 0 V to 10 V. Also, the 'reverse cancel terminal C N R changes from 10 V to 0 V. For this reason, the node c is changed from 10 v to 0 V. As a result, the voltage of the node a is maintained at the reference voltage V 1 (5 V). Then, the node b exceeds the amplitude increase by -29- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 476854 B7 V. Description of the invention (27) Threshold voltage of logic circuit 20 For example, at the point of 4 · 5 V, the output of the logic circuit 20 for amplitude increase is inverted at time T 2 3. As a result, the output signal 0 S of the logic circuit 20 for amplitude amplification is 10 V, and the transistor Q Γ and the transistor Q 2 are turned off. As a result, the node b is the voltage of the turn-on / out signal 0S of the output logic of the reverse-amplitude-amplification logic circuit 20, and is set to 4.5 V. That is, the node b sets the threshold voltage of the logic circuit 20 for amplitude increase. On the other hand, the node c is set to 10 volts-4 · 5 V (voltage of the node b) = 5.5V. Between the next time T 2 4 to time T 2 6, a data sampling period is presented. That is, during this time T 2 4 to time T 2 6, the timing control circuit 10 turns the switch S W 2 on, and the switches SW 1 and SW 3 to SW 5 turn off. To this end, an input signal IS is input at a node a. For example, when the input signal I S changes from 4 V to 6 V, as the 5 V boundary set by the reference voltage V 1, the output signal 0 S changes from 0 V to 10 V. That is, at the time point T 2 5 when the input signal IS is 5 V, the voltage at the node b exceeds the threshold of the amplitude increase logic circuit 20 and the voltage of 4 · 5 V, the output of the amplitude increase logic circuit 20 The signal OS changes from 0V to 10V. During the period from the next time T 2 6 to the time D 2 27, the capital contribution period is maintained. That is, during the period from time T 2 6 to time T 2 7, the timing control circuit 10 turns off the switches S W 1 to S W 5. Between this time T 2 6 to time T 2 7, the input signal IS of the amplitude 2 and the digital signal input between the sampling period of the stain (time T 2 4 to time T 2 6) is taken as the amplitude 1 0 The output signal of the digital signal of V is 0s. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -30- 1 !! · Install i I < Please read the precautions on the back page first ) Printed on 0 · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 476854 A7 B7 V. Description of Invention (28) Temporarily maintained. However, operations other than this signal amplifier circuit 30 are similar to those of the first embodiment. As described above, * the signal amplifier circuit 3 2 related to this embodiment uses the signal line drive circuit 3, which can be used as a signal line drive circuit that operates with digital signals without increasing the scale and power consumption of external circuits: 3. In addition, when the signal amplifier circuit 32 of the liquid crystal display device of this embodiment is used, the characteristics of the components in the signal line drive circuit are uneven, and the threshold voltage of the logic circuit 20 for the amplitude amplifier is in each block or When each product is different, the digital signal of the input signal IS with a small amplitude can be sampled. That is, when the threshold voltage of the logic circuit 20 for amplitude amplification varies, the signal amplification circuit 30 can still operate normally. [Embodiment 4] The fourth embodiment of the present invention will be described in detail with reference to the drawings below by modifying the method of maintaining the threshold voltage of the threshold a of the third embodiment and the cancellation period. " Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Figure 10 is a circuit diagram showing the structure of the main part of the signal amplifier circuit related to the fourth embodiment of the present invention. As shown in FIG. 10, the signal boosting circuit 34 of the fourth embodiment is configured by adding the signal boosting circuit 32 of the third embodiment described above, and further including a capacitor C3. When describing a circuit component different from the third embodiment, one end of the capacitor C 3 is connected to the node a at the node a. The other end side of the capacitor C 3 is connected to a holding voltage V 2. In this embodiment, 0 V is applied as the holding voltage, but when the paper is a fixed voltage, the Chinese paper standard (CNS) A4 (210 X 297 mm) is applied. Γβΐ-": Surface 4 5 8 6. 7 A7 ________ B7 _____ 5. Description of the invention (? 9) Any volt is acceptable. In this embodiment, the voltage source of the switches SW 4, SW 5 and the transistor Q 2 and the capacitors C 2, C 3, and 10 V, the voltage source of the reverse cancellation voltage, and the voltage source of the holding voltage V 2, When the capacitor C1 constitutes a reference voltage holding circuit that holds the differential voltage, the node a is maintained at the reference electroacoustic. The operation of the signal amplifier circuit 34 of this embodiment is the same as that of the signal amplifier circuit 34 of the third embodiment described above, and the description is omitted. In this way, the additional capacitor C 3 ground 'at the node a can easily maintain the voltage at the node a at 5 V during the threshold cancellation period (time T 2 1 to time T 2 2) shown in FIG. 9. That is, between the reset period (time T 2 1 to time T 2 2), in this example, the voltage of 5 V is accumulated in the capacitor C 3, and it can be easily changed between the threshold and cancellation periods. The node a is maintained at 5 V. [Fifth embodiment] The fifth embodiment of the present invention is a variation of the signal amplification circuit 34 of the fourth embodiment of the present invention, which is a variation of the signal amplification circuit 34 of the fourth embodiment. . In the following, the root map is explained in detail. FIG. 11 is a circuit diagram showing the configuration of the main part of the signal amplification circuit 36 of the fifth embodiment of the present invention, and FIG. 12 is a timing chart showing the operation of the signal amplification circuit 36 shown in FIG. 11. As shown in Figure 11, the signal amplification circuit of the fifth embodiment-32- --------------- · Cao (Please read the caution page on the back first)- Line · This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 public love) 4 5 8 6; 7 A7 —_ B7 ___ V. Ming Ming (3〇) ^-— — — — — — — — — — 1 «^. II < Please read the note on the back page first) 3 6 is in the signal amplifier circuit 3 4 related to the above-mentioned Binsch shape, and it replaces the P-type MOS transistor Q1. The transistor Q 3 of the n-type MOS transistor is provided, and a switch SW 6 is provided for construction. The circuit configuration different from the fourth embodiment will be described. In some cases, the control terminal of the transistor Q 3 is connected to one end of the switch SW 6. The other end side of the switch SW 6 is connected to the output side of the inverter 20 a of the logic circuit 20 for amplitude amplification. In this embodiment, via the switch SW 6 and the voltage source of the transistor Q 3 and 0 V, when the capacitor C 1 constitutes a holding differential voltage, the node b dimension is set to the threshold of the amplitude increase logic circuit 2 0.値 Threshold of voltage 値 Voltage detection circuit. • Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Next, the operation of the signal amplifier circuit 36 shown in FIG. 11 will be described with reference to FIG. 12. First, between time D1 and time T2, there is a reset period. That is, during the period from time T 3 1 to time D 3 2, the i timing control circuit 10 sends a control signal CS, and the switch SW 1, the switch SW 3, and the switch SW 5 of the signal amplifier circuit 3 0 are turned on, and the switches SW 2 and The switches SW 4 and SW 6 are turned off. From this time T 3 1 to time T 3 2, the node a is used as the reference voltage v 丄, for example, 5 V is input. For this reason, a voltage of $ v is accumulated in the capacitor c3. At the same time, 0V is input to node b, and 10V is input to node c. The next time between T 3 2 and T 3 34 will be a deadline and a cancellation period. During the period from time T 3 2 to time T 3 4, the timing control circuit 10 is to turn on the switch SW 4 and the switch s W 6, which will be 33-476854 'A7 _- _ B7. V. Description of the invention ( 31) The switches SW · 1 // of the external switches are turned off. As a result, the transistor Q h and the transistor Q 3 are turned on. During this time Ding 3 2 to T 3 4, the cancellation terminal C N changes from 0 V to 10 V. For this reason, the node b is changed from 0 V to 10 V. The reverse cancellation terminal CN R changes from 10 V to 0 V. For this reason, the node c is changed from 10 v to 0 V. As a result, the voltage of the node a is maintained at the reference voltage V 1 (5 V). Then, when the node b exceeds the threshold of the amplitude increase logic circuit 20, for example, T 3 3 at a time point of 4.5 V, the output of the amplitude increase logic circuit 20 is inverted. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-— — — — — — — — — — IIC Please read the notes on the back page)-line. As a result, the amplitude of the output from the inverter 2 0 b is used to increase The output signal 0S of the logic circuit 20 is 10V, and the transistor Q1 is turned off. In addition, the signal output from the inverter 20 a is 0 V, and the transistor Q 3 谄 is turned off. Accordingly, it is assumed that the node b is the voltage of the output signal 0S of the output logic of the logic circuit 20 for inverting the amplitude increase ^. 5 V. That is, the node b sets a threshold threshold voltage that is a logic circuit 2 for amplitude increase. For this reason, one of the differential voltages β 5V is stored in the capacitor C1. On the other hand, node c is set to 10V_4 · 5V (voltage of node b) = 5 · 5V. — J · The data sampling period is shown between T 2 4 and D 2 6 at the next time. That is, during this time T 3 4 to time T 3 6, the timing control circuit 10 turns the switch S W 2 on, and the switches S W 1 and 5 W 3 to S W 6 turn off. To this end, an input signal IS is input at a node a. For example, when the input signal IS changes from 4 V to 6 V, the Chinese paper standard (CNS) A4 (210 X 297) is adopted as the paper standard. 34 476854 A7 B7 V. Description of the invention (32) Reference voltage V 1 setting In the realm of 5 V, the output signal 0 S changes from 0 V to 1 0 V. That is, at the time point T 3 5 when the input signal IS is 5 V, the voltage at the node b exceeds the threshold of the amplitude increase logic circuit 20 and the voltage of 4 · 5 V, the output of the logic circuit 20 for amplitude increase The signal OS changes from 0 V to 10 V. ·: Binding The period between the next time Ding 36 to T 3 7 is the data retention period. That is, the timing control circuit 10 causes the switches S W 1 to S W 6 to be turned off during the period from time D 36 to time T 37. During this time T 3 6 to time T 3 7, the input signal IS of the digital signal having an amplitude of 2 V which is input between the data sampling period (time T 3 4 to time T 3 6) is taken as the amplitude 1 OV The digital signal output signal 03 is temporarily held. However, operations other than this signal amplifier circuit 30 are the same as those of the first embodiment. As described above, the signal amplifier circuit 3 6 related to this embodiment uses the signal line drive circuit 3 without increasing the size of the external circuit.> It can be driven by digital signals with a signal line. Circuit 3 ^ Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, and according to the signal amplification circuit 36 of the liquid crystal display device of this embodiment, the characteristics of the components in this signal line drive circuit are uneven, and the logic circuit for amplitude increase The threshold value of 20 can be used to sample the digital signal of the input signal IS with a small amplitude when each side or product is different. That is, when the threshold voltage of the amplitude increase logic circuit 20 varies, the signal increase circuit 36 can still operate normally. In addition, by adding a capacitor C 3 to the node a, during the threshold threshold cancellation period shown in FIG. 12 (time τ 3 2 to time T 3 4), the paper size of the node can be applied to the Chinese National Standard (CNS) A4 specification. (210 X 297 mm) -35-V. Description of the invention (33) • — |! «(Please read the caution page on the back first) The voltage of a is easy to keep at 5 v. That is to say, during the reset period (time T 3 1 to time T 3 2), in this example, a voltage of 5 V is accumulated in the capacitor C 3, so the threshold can be easily cancelled. Keep node a at 5 V. [Sixth Embodiment] A sixth embodiment of the present invention replaces the transistors Q2 and Q3 of the fifth embodiment described above with a switching gate. Hereinafter, it will be described in detail based on the drawings. Fig. 13 is a circuit diagram showing the configuration and main parts of a signal amplifier circuit according to a sixth embodiment of the present invention. --Line- Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs as shown in Figure 13. The signal amplifier circuit 38 related to the sixth embodiment replaces the transistor Q of the signal amplifier circuit 36 related to the fifth embodiment described above. 2. Q 3 is composed of switching gates TG 1 and TG 2. A circuit component S # which is different from the fifth embodiment described above will be described, and a switching gate T G 1 is connected to the node b. The switching gate T G 1 is composed of a transistor Q 4 of an n-type MOS transistor and a transistor Q 7 of a P-type transistor. At the node c, a transfer gate T G 2 is connected. The switching gate T G 2 is composed of a transistor Q 5 of an n-type M 0 S transistor and a transistor Q 6 of a CL-type transistor. In this embodiment, the voltage source of the switch SW 4, SW 5, SW 6 and the switching gates TG 2 and the capacitors C 2 and 100 V and the voltage source of the reverse cancellation voltage are used to maintain the differential voltage of the capacitor C1, A circuit for maintaining the node a at the reference voltage is configured. In addition, the paper size of the paper through switch SW 4 is in accordance with China National Standard (CNS) A4 (210 X 297 mm) -36-476854 A7 B7 V. Description of the invention (34) 7, -— ί —----- 丨丨! (Please read the Precautions on the back page), the voltage source of SW 6 and the switching gates G 1 and 0 V and the voltage source canceling the voltage. When the capacitor C Ί keeps the cover voltage, it constitutes the node b A threshold voltage detection circuit is set in the threshold voltage of the amplitude increase logic circuit 2. However, the operation of the signal amplifier circuit 3.8 related to this embodiment is the same as that of the signal amplifier circuit 36 related to the fifth embodiment described above, and the description is omitted. [Seventh Embodiment].--A seventh embodiment of the present invention is a method for modifying the differential voltage setting of the capacitor C. 1 of the second to sixth embodiments described above. Hereinafter, it will be described in detail with reference to the drawings. Line-Fig. 14 is a circuit diagram showing the configuration of the main part of the signal amplification circuit according to the seventh embodiment of the present invention, and Fig. 15 is a timing chart showing the operation of the signal amplification circuit shown in Fig. 14. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs as shown in Figure 14. The signal amplifier circuit 40 of the seventh embodiment is a transistor Q of a p-type MO S transistor in addition to the third embodiment. 8constitute. The circuit configuration different from the third embodiment will be described. In the case of a rabbit, an electric crystal Q 8 is connected between one end side of the capacitor C 1 and one end side of the capacitor c 2. The control terminal of the transistor Q 8 is connected to one end side of the switch SW 4. The other end side of the switch SW 4 is connected to the output side of the inverter 2 0 b. In this embodiment, the paper size of the switch s W 4, SW 5 and transistor is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 meals) -37 476854 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ^^ A7 _ B7 ___ V. Description of the invention (35) The voltage source of Q 8 and capacitors C 2 and χ OV, when capacitor C 1 forms a differential voltage, a reference voltage holding circuit that maintains node 黠 a at the reference voltage . In addition, through switches SW 3 to SW 5 and a transistor Q 8 and a voltage source of 0 V and a voltage source of 10 volts, while the capacitor ci maintains a differential voltage, a logic circuit for setting node b to a signal amplification circuit is configured. Threshold voltage of 2 0 Threshold voltage detection circuit. Next, 'the operation of the signal amplifier circuit 40 shown in FIG. 14 will be described based on FIG. 15. First, a reset period occurs between time T 4 1 and time D 4 2. That is, from time D1 to T4 2, the self-timing control circuit 10 sends a control signal CS, and the switches 5 W 1, SW 3 and SW 5 of the signal amplifier circuit 40 are turned on, and the switch SW is turned on. 2 and switch SW 4 are off. From this time T 4 1 to time T 4 2, the node a is used as the reference voltage V 1, for example, 5 V is input. At the same time, 0 V is input to node b, and 10 V is input to node C. Between the next time T 4 2 and time T 4 4, there is a threshold and cancellation period. During the period from time T 4 2 to time T 4 4, the timing control circuit 10 turns off the switches S W 1 to S W 3 and S W 5 and turns the switch S W 4 on. As a result, the transistor Q 8 | is turned on. Between this time T 4 2 and time T 4 4, the capacitor C 1 and the capacitor C 2 are short-circuited through the transistor Q 8. For this reason, the node b is changed from 0 V to 10 V. Then, at the time T 4 3 when the node b exceeds the threshold value of the logic circuit 20 for amplitude increase, for example, 4.5 V, the output of the logic circuit 20 for amplitude increase is inverted, and the output is • 111111 — — — — — — — ^ · II < Please read the notes on the back page first) 0 · • Line-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -38- 476854 A7 B7 V. Explanation of Ming (36) 1! 1! · Installation— {Please read the precautions on the back page first) The signal 〇S is 1 〇V. For this reason, the transistor Q 8 is in the off state I. The result 'node b' sets the threshold voltage of the logic voltage of the output of the logic circuit 2 for reverse amplitude increase. That is, a differential voltage of 5 V of the threshold voltage of the logic circuit 20 for amplitude increase and the reference voltage V 1 is stored in the capacitor C. That is, in this embodiment, a voltage of 0. 5 V is stored in the capacitor C 1. --Line- Between the next time Ding 4 4 ~ time T 5 6, the data sampling period is presented. That is, during this time Ding 44 to Ding 46, the timing control circuit 10 turns on the switch SW 2 and the switches SW 1 and SW 3 to SW 3 of the switch SW are turned off. Between this time T 4 4 to time T 4 6. For example, the input signal I S changes from 4 V to 6 V. At this time, as the boundary of 5 V set by the reference voltage V 1, at time T 4 5, the output signal 0S of the logic circuit 20 for amplitude increase changes from 0 V to 1 0 V. That is, at the time T 4 5 when the input signal IS exceeds 5 V, the voltage at the node b exceeds the threshold voltage of the logic circuit 20 for the amplitude increase ijf of 4 · 5 V. Therefore, the output signal 0 S of the amplitude increase logic circuit 20 is switched from low to high. Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, from the time T 4 6 to the time T 4 7. EP, during the time T 4 6 to time T 4 7, the timing selection circuit 10 is to turn off the switches S W 1 to S W 5. During this time T 4 6 to time T 4 7, the input signal IS of the digital signal with an amplitude of 2 V which is input between the data sampling period (time T 4 4 to time T 4 6) is used as a digital signal with an amplitude of 10 V The output signal 0S is temporarily held. However, 'this signal amplifier circuit other than 40's This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -39 · 476854 A7 B7 V. Description of the invention (37) The operation is the same as the first implementation above The form is the same. • ^ — 1 —! — — — — — — • ^ Μ I (Please read the caution page on the back first) As described above, the signal amplifier circuit 4 of this embodiment is driven by a signal line 3, The circuit 3 can be driven by a signal line that operates with digital signals without increasing the scale and power consumption of the external circuit. Furthermore, when the signal amplification circuit 40 of the liquid crystal display device of this embodiment is used, the characteristics of the components in the signal line driving circuit are uneven, and the threshold voltage of the logic circuit 20 for amplitude amplification is in each block or each When the products are different, the digital signal of the input signal IS with a small amplitude can be sampled. That is, when the threshold voltage of the logic circuit 20 for signal amplification varies, the signal amplifier circuit 40 can still operate normally. [Eighth Embodiment]-• Wire-An eighth embodiment of the present invention is a method for modifying the differential voltage setting of the capacitor C1 of the seventh embodiment described above. Hereinafter, it will be described in detail with reference to the drawings. * Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 16 is a circuit diagram showing the structure of the main part of the signal amplifier circuit related to the eighth embodiment of the present invention. Figure 17 is a signal amplifier circuit shown in Figure 16 Timing diagram of the action. In this embodiment, when the capacitor C 1 constitutes a reference voltage holding circuit via the voltage source of the switch SW 1 and the reference power group V 1, the reference voltage holding circuit maintains the node a at the reference voltage. In addition, through the switches SW3 to SW5, the transistor Q8, a voltage source of 0V, and a voltage source of 10V, when the capacitor C1 maintains a differential voltage, the node b is set to the threshold voltage of the signal amplification logic circuit 20 'Threshold of voltage limit The paper size of this paper applies to China National Standard (CNS) A4 specification (210 X 297 mm) -40-476854 A7 — B7 _ 5. Description of the invention (38) Voltage detection circuit. , "• I ------------- ^ -1 — (Please read the precautionary note on the back ...!) As shown in Figure 16, the signal amplifier circuit related to the first implementation form 4 2 is a configuration in which the capacitor C 2 is omitted from the seventh embodiment described above. Next, the operation of the signal amplification circuit 42 shown in FIG. 16 will be described with reference to FIG. 15. First, time T 5 1 to time T 5 2 / In between, it is a reset period. That is, from time T 5 1 to time T 5 2, the self-timing control circuit 10 sends a control signal CS, and the signal amplifier circuit 40 switches 5 W 1 and switches s W 3 and switches. SW 5 is in the on state, and switches SW 2 and SW 4 are in the off state. At this time, from time 51 to time T 5 2, node a is used as the reference voltage V 1, for example, 5 V is input. At the same time, Enter 0V at node b and 10 V at node C. The threshold 时刻 cancellation period is between the next time T 5 2 to time T 5 4. That is, the time from time T 5 2 to time T 5 4. Timing control circuit--line. Printed by the Consumer Affairs Office of the Intellectual Property Bureau of the Ministry of Economic Affairs. 1 0 will turn off switch SW 2 and switch SW 3 and switch SW 5 i, and switch SW 1 and the switch SW 4 are turned on. As a result, the transistor Q 8 is turned on. During this time T 5 2 to T 5 4, the capacitor 1 and the capacitor C 2 are short-circuited through the transistor Q 8. In addition, because the switch SW 1 is in an on state, the fog pressure of the node a is maintained at 5 V of the reference voltage V 1. For this reason, the voltage of the node a is maintained at 5 V, and the voltage of the node b is applied from 0 V to 1 0 V. Then, at the time T 5 3 when the node b exceeds the threshold of the amplitude increase logic circuit 20, for example, 4.5 V, the output of the amplitude increase logic circuit 20 is inverted, and the output signal 0S is 1 0V. For this reason, the transistor Q8 -41-This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210x297 mm) 476854 A7 r -----------__ B7 V. Description of the invention (39) As a result, the node b is set to the threshold voltage of the output logic voltage of the logic circuit 20 for the reverse amplitude increase. That is, the capacitor C 1 stores the voltage of the logic circuit 2 for the amplitude increase. The difference voltage between the threshold voltage and the reference voltage V 1 is 5 V. In other words, in this embodiment, The container C 1 accumulates a voltage of 0.5 V. ^;. The data sampling period is between the next time T 5 4 to time T 5 6. That is, from time D 5 to time T 5 6, the timing control The circuit 10 is to turn the switch SW 2 on, and the switches SW 1 and SW 3 to SW 5 of the switch s W are turned off. At this time

T 5 4〜時刻T 5 6之期間。例如，輸入信號I S自4 V 變化至6 V。此時，做爲基準電壓v 1設定之5 V的境界 ，於時刻T 5 5之時點，振幅增幅用邏輯電路2 0之輸出 信號〇S則自0 V向1 〇 V變化。即輸入信號I s超過 5 V之時刻T 5 5，節點b之電壓係超過振幅增幅用邏輯 - … 電路2 0之臨限値電壓的4 · 5 V。因此，振幅增幅用邏 輯電路2 0之輸出信號〇S則自低切換至高。 下個時刻T 5 6〜時刻T 5 7之間，呈資料保持期間 。即，於時刻T 5 6〜時刻T 5 7之期間，定時控制電路 1 0係令開關S W 1〜S W 5呈關閉狀態。於此時^ T 5 6〜時刻T 5 7期間，將輸入於資料取樣期間（時刻 T 5 4〜時刻T 5 6 )之間的振幅2 V之數位信號的輸入 信號I S，做爲振幅1 〇 V之數位信號之輸出信號0 S ’ 暫時性地加以保持。然而’此信號增幅電路4 2以外之動 作係與上述第1實施形態相同。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -42- ilm -------- I _ — (請先閱讀背面之注意事項本頁) 訂： --線· 經濟部智慧財產局員工消費合作社印制π 47^854 A7 B7 五、發明說明（40) 如以上所述，將有關本實施形態之信號增幅電路4 2 使用信號線驅動電路3，豇不增大外部電路之規模及消耗 電力地，可呈以數位信號動作之信號~線驅動電路3。 更且，有關本實施形態之液晶顯示裝置之信號增幅電 路4 2時，此信號線驅動電路內之元件特性叫爲參差，振 幅增幅用邏輯電路2 0之臨限値電壓則於每方塊不同之時 ，可進行振幅小之輸入信號I S之數位信號之取樣。即， 信號增幅用邏輯電路2 0之臨限値電壓有參差之時，仍可 將此信號增幅電路42正常動作。 . . _‘.一. 更且，根據有關本賓施形態之信號增幅電路4 2時， 較上述第7實施形態，呈省略電容器C 2之構成之故，可 達成電路構成之簡化。 【實施形態Θ】 本發明之第9實施形態係變形上述第7實施#彡態之節 點a之臨限値取消期間的基準電壓之保持手法者。以下， 根據圖面詳細地加以說明。 圖1 8係顯示有關本發明之第9實施形態之信號增幅 電路之主要部之構成的電路圖。 如圖1 8所示，有關第9實施形態之信號增幅電路 4 4係加上上述有關第7實施形態之信號增幅電路4 0， 另具備電容器C 3加以構成。說明與上述第7實施形態不 同之電路構成部分時，於節點a中，連接電容器C 3之一 端側。此電容器C 3之另端側係連接於保持電壓V 2。此 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） - 43- ----------裝·！ <請先閱讀背面之注意事項本頁) 訂· 經濟部智慧財產局員工消費合作社印製 476854 - ^ A7 — B7 五、發明說明（41 ) 實施形態中，做爲保持電壓施加〇 V ,但爲固定電壓時任 何伏特皆可。 · 於本實施形態中，.經由開關S W:4、S W 5和電晶體 Q 8和電容器C 2、C 3和1 0V之電壓源，於電容器 C 1·構成保持差分電壓之時，將節_ a維持_·墓準電壓的 基準電壓保持電路。又，經由開關S w 3〜W 5和電晶體 Q8和0V之電壓源和1 〇V之電壓源，於電容器c 1構 成保持差分電壓之時，將節點a設定呈振幅增幅用邏輯電 路2 0之臨限値電壓的臨限値電壓檢出電路。 而，有關本實施形態之信號增幅電路4 4之動作係與 上述有關第7實施形態之信號增幅電路4 0同樣之故，省 略該說明。 如此，經由於節點a附加電容器c 3地，於圖1 5所 示臨限値取消期間（時刻T 4 2〜時刻T 4 4 )，可將節 點a之電壓易於保持於5 V。即，於重置期間（時~刻 T4 1〜時刻T42 )之間，於此之例中，於電容器C 3 蓄積5 V之電壓之故，臨限値取消期間之間，可容易地將 節點a保持k 5 V。 【第1 0實施形態】 本發明之第1 0實施形態係代替上述第9實施形態之 電晶體Q 8，設置轉換閛T G 3者。以下，根據圖面加以 詳細說明。 圖1 9係顯示有關本發明之第1 〇實施形態之信號增 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -44 · -丨丨丨丨丨丨丨丨丨！*裝·！ <請先閱讀背面之注意事項本頁： 訂· •線· 經濟部智慧財產局員工消費合作社印製 54 8 47 經濟部智慧財產局員工消費合作社印製 A7 _ B7 _五、聲明說明t 42 ) 幅電路之主要部之構成、的電路圖。圖2 〇係示於顯示\圖 1 9之信號增幅電路之動作釣定時圖。 如圖1 9所示，有關第1 0實施形態之信號增幅電路 4 6係較上述第9實施形態，.代替電晶體Q 9，設置轉換 閘T G 3加以構成。此轉換閘丁{3係由11型.；^1^〇8電 晶體的電晶體Q 9，和p型之電晶體的電晶體Q 1 0所構 成。電晶體Q 9之控制端子係連接於開關S W 6之一端側 。開關S W 6之另端側係連接於振幅增幅用邏輯電路2 0 之反相器2 0 b之輸出側。電晶體〇1〇之控制端子係連 接於開關S W 4之一端側。開關S W 4之另端側係連接於 振幅增幅用邏輯電路2 0之反相器2 0 b之輸出側。_ 於本實施形態中，經由開關S W 4〜S W 6和轉換閘 TG 3和電容器C 2、C 3和1 0V之電壓源，於電容器 C 1構成保持差分電壓之時，將節點a維持於基準電壓的 基準電壓保持電路。又，經由開關S W 3〜S W 和轉換 閘丁 G 3和Ο V之電壓源和1 〇 V之電壓源，於電容器 C 1保持差分電壓之時，構成將節點b設定於信號增幅用 邏輯電路2 0之臨限値電壓的臨限値電壓檢出電路。 接著，根據圖20，說明圖19所示信號增幅、重路 4 6之動作。首先，時刻丁 6 1〜時刻丁 6 2之間，呈重 置期間。即，時刻T 6 1〜時刻T 6 2之期間，自定時控 制電路1 0送出控制信號C S，信號增幅電路4 0之開關 5 W 1和開關S W 3和開關S W 5呈開啓狀態，開關 S W 2和開關S W 4則呈關閉狀態。此時刻T 6 1〜時刻 ------------111·裝 — * (請先閱讀背面之注意事項本頁) 訂· ··線· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -45- 54 8 47 A7 - ----B7 ------—---_______ 五、發明說明（43 ) — I!丨！ — ! i ! 鬌 (請先閲讀背面之注意事項本頁) 丁 6 2期間’於節點a做爲基準電應V 1，例如輸入5 v 。又，與此之同時於節點、鞴入〇 V，於節點c輸入 1 0 V。 下個時刻T 6 2〜時刻τ 6 4之間，呈臨限値取消期 間。於時刻T 6 2〜時刻τ 6 4之期間，定時控制電路 1 0係將開關S W 1〜S w 3和開關S W 5呈關閉狀態， 將開關S W 4和開關S W 6呈開菡之狀態。結果，電晶體 Q 9和電晶體Q 1 〇呈開啓狀態。即，轉換閘丁 g 3呈開 啓狀態。 ~ 於此時刻T 6 2〜時刻T 6 4之期間，電容器c 1和 電容器C 2係透過此電晶體Q 9和電晶體Q 1 〇加以短路 。爲此，節點a之電壓保持於5 V地，節點b之電壓則自 --線· 經濟部智慧財產局員工消費合作社印制衣 0 V向1 〇 V加以變化。然後，於節點b超過振幅增幅用 邏輯電路2 0之臨限値電壓之例如4 · 5 V之時點的時刻 T 6 3，反轉振幅增幅用邏輯電路2 0之輸出，—出信號 〇S呈1 〇 V。爲此，電晶體Q 9和電晶體Q 1 0係呈關 閉狀態。即，轉換閘T G 3係呈開閉狀態。結果，節點b 係設定呈反轉振幅增幅用邏輯電路2 0之輸出邏輯電壓之 臨限値電壓。即，於電容器C 1蓄存振幅增幅用羼輯電路 2 0之臨限値電壓和基準電壓V 1之5 V的差分電壓。即 ，本實施形態中，於電容器C 1蓄積一 0 · 5 V之電壓。 下個時刻T 6 4〜時刻T 6 6之間，呈資料取樣期間 。即，此時刻丁 6 4〜時刻T 6 6之期間’定時控制電路 1 0係將開關S W 2呈開啓狀態，此外之開關s w 1和開 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -46- 476854 A7 B7 五、發明說明（44) 關S W 3〜s W 6則呈關閉狀態。於此時間丁 6 4〜時刻 T 6 6之期間。例如，輸入信號I S自4 V變化至6 V。 此時，做爲基準電壓V 1設定之5 V的境界，於時刻 T 6 5之時點，振幅增幅用邏輯電路2 0之輸出信號0 S 則自Ο V向1 Ο V變化。即輸入信號I S超辦.5 · V之時刻 T 6 5，節點b之電壓係超過振幅增幅用邏輯電路2 0之 臨限値電壓的4 · 5 V。因此，振幅增幅用邏輯電路2 0 之輸出信號0 S則自低切換至高。， 下個時刻T 6 6〜時刻T 67之期間，呈資料保持期 間。即，時刻丁 6 6〜時刻T 6 7之期間，定時控制電路 1 0係令開關S W 1〜S W 5呈關閉狀態。於此時刻 T 6 6〜時刻T 6 7期間，將輸入於資料取樣期間（時刻 T 6 4〜時刻T 6 6 )之間的振幅2 V之數位信號的輸入 信號I S，做爲振幅1 〇 V之數位信號之輸出信號〇S， 暫時性地加以保持。然而，此信號增幅電路4 0以外之動 作係與上述第1實施形態相同。_ 如以上所述，將有關本實施形態之信號增幅電路4 6 使用信號線驅動電路3，可不增大外部電路之規模及消耗 電力地，可呈以數位信號動作之信號線驅動電路3^1 更且，有關本實施形態之液晶顯示裝置之信號增幅電 路4 6時，此信號線驅動電路內之元件特性則爲參差，振 幅增幅用邏輯電路2 0之臨限値電壓則於每方塊有所不同 之時，可進行振幅小之輸入信號I S之數位信號之取樣。 即，信號增幅用邏輯電路2 0之臨限値電壓有參差之時， 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公餐） .47- 1_!·裝·！ 0 (請先閱讀背面之注意事項本頁) 訂· --線- 經濟部智慧財產局員工消費合作社印製 476854 A7 —' B7 _ 五、發明說明（45 ) 仍可將此信號增幅電路.4 6正常動作。· Π —--------- -- (請先閱讀背面之注意事項本頁) 【第11實施形態】 第11實施形態係顯示使用上述各實施形態的振幅增 幅用邏輯電路2 0之電路構成之一例。 圖2 1係顯示振幅增幅用邏輯電路2 0之電路構成之 ~例圖。由此圖2 1可知，振幅增幅用邏輯電路2 0係具 備P型Μ 0 S電晶體所成電晶體Q 20〜Q 2 6，和η型 Μ〇S電晶體所成電晶體Q 3 0〜Q 3 6加以構成。此振 幅增幅用邏輯電路2 0係一般使用準位偏移電路之故，在 此省略以上之說明。 -·線· 然而，本發明係不限定於上述第1實施形態〜第1 1 實施形態可做種種之變形。例如，對於臨限値取消期間之 動作定時，振幅增幅用邏輯電路2 0之臨限値電壓充分保 持於電容器C 1之期間時，於每資料取樣無需進行臨限値 取消之動作。 ^ 經濟部智慧財產局員工消費合作社印5衣 又，上述各實施形態之中，經由上昇節點b之電壓的 過程，檢出振幅增幅用邏輯電路2 0之臨限値電壓，但亦 可經由下降節點b之電壓的過程，檢出振幅增幅黎邏輯電 路2 0之臨限値電壓。即，上述各實施形態中，雖然於振 幅增幅用邏輯電路之輸出信號自低切換爲高之定時，檢出 臨限値電壓，但亦可以與此相反自高切換爲低之定時，檢 出臨限値電壓。 如以上所述，根據本發明將振幅增幅用邏輯電路之臨 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） «48- 476854 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（46 ) 限値電壓和基準電壓之差分電壓，以差分電壓保持電路力口 以吸收之故，構成振幅增_用邏輯電路之元素特性中會產 生參差，於振幅.增幅用邏輯電路之臨限値®壓有#差不胃 時，將有此振幅增幅用邏輯電路之信號增幅電路IE常地力口 以動作。 * 【第1 2實施形態】 以上係對於有關本發明之圖2之信號增幅電路1 2 a 加以說明，但以下則對於設於有關本發明之圖2之數位類 比變換電路1 6 a的負荷驅動電路，參照圖面具體加以說 明。即，以下中，說明將有關本發明之負荷驅動電路，適 用於液晶顯示裝置之信號線驅動電路之例。 有關本發明之第1 2實施形態之負荷驅動電路係將輸 入影像信號之電壓和邏輯電路之臨限値電壓的差分電壓保 -" -- .—- 持於電容器，將控制供給輸入影像信號之信號線的電壓的 電晶體之開/關，經由以邏輯電路加以進行，令反轉邏輯 電路之邏輯輸出的臨限値電壓的參差以電容器加以吸收者 。更詳細者於以下加以說明。 圖2 2係顯示有關本發明之第1 2實施形態之-負荷驅 動電路之主要部之構成的電路圖，圖2 3係顯示負荷驅動 電路整體之構成的槪略方塊圖，圖2 4係說明正極性用之 負荷驅動電路和正極性用之負荷驅動電‘路之動作區分圖。 圖4之信號線驅動電路3係使用示於圖2 3之負荷驅 動電路加以構成。圖2 3之負荷驅動電路係具有對應各信 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -49 · JIIII1IIIII — · - I i (請先閱讀背面之注意事項本頁) 訂： -·線· 476854 A7 B7 五、發明說明（47 ) 號線設置之正極性用之負荷驅動電路1 1 1 a ，和負極性 用之負荷驅動電路Γ 11拉，和切換控制此等負荷驅動電 路1 1 1 a、1 1 lb內之各種開關的開關切換控制電路 1 1 2 〇T 5 4 to T 5 6. For example, the input signal I S changes from 4 V to 6 V. At this time, as the boundary of 5 V set by the reference voltage v 1, at time T 5 5, the output signal 0S of the logic circuit 20 for amplitude increase changes from 0 V to 1 0 V. That is, at the time T 5 5 when the input signal Is exceeds 5 V, the voltage at the node b exceeds the threshold of the amplitude-increasing logic-... Therefore, the output signal 0S of the logic circuit 20 for amplitude increase is switched from low to high. From the next time T 5 6 to time T 5 7, a data retention period is presented. That is, during the period from time T 5 6 to time T 5 7, the timing control circuit 10 turns off the switches S W 1 to S W 5. At this time ^ T 5 6 to time T 5 7, the input signal IS of the digital signal having an amplitude of 2 V between the data sampling period (time T 5 4 to time T 5 6) is taken as the amplitude 1 〇 The output signal 0 S 'of the digital signal of V is temporarily held. However, operations other than this signal amplification circuit 42 are the same as those in the first embodiment. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -42- ilm -------- I _ — (Please read the precautions on the back page first) Order: --line · Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs π 47 ^ 854 A7 B7 V. Description of the invention (40) As mentioned above, the signal amplifier circuit 4 2 related to this embodiment is driven by the signal line 3, but does not increase. The scale of the large external circuit and the power consumption ground can be signal-actuated by digital signals ~ line drive circuit 3. Furthermore, when the signal amplification circuit 42 of the liquid crystal display device of this embodiment is used, the characteristics of the components in the signal line driving circuit are called staggered, and the threshold voltage of the logic circuit 20 for amplitude amplification is different for each block. At this time, the digital signal of the input signal IS with a small amplitude can be sampled. That is, when the threshold voltage of the signal amplification logic circuit 20 varies, the signal amplification circuit 42 can still operate normally. _’I. Furthermore, when the signal amplifier circuit 42 according to the Benbinsch configuration is used, the configuration of the capacitor C 2 is omitted compared to the seventh embodiment, and the circuit configuration can be simplified. [Embodiment Θ] The ninth embodiment of the present invention is a method of maintaining the reference voltage during the cancellation of the threshold a of the node #a in the seventh embodiment described above. Hereinafter, it will be described in detail with reference to the drawings. Fig. 18 is a circuit diagram showing a configuration of a main part of a signal amplifier circuit according to a ninth embodiment of the present invention. As shown in FIG. 18, the signal amplifier circuit 44 according to the ninth embodiment is configured by adding the signal amplifier circuit 40 according to the seventh embodiment described above, and further comprising a capacitor C3. When describing a circuit configuration different from the seventh embodiment, one end of the capacitor C 3 is connected to the node a. The other end side of the capacitor C 3 is connected to a holding voltage V 2. This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm)-43- ---------- installed ·! < Please read the note on the back page first.) Order · Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs's Consumer Cooperatives 476854-^ A7 — B7 V. Description of the invention (41) In the implementation mode, 0V is applied as a holding voltage, Any volt is acceptable at a fixed voltage. · In this embodiment, the voltage source of the capacitor C 1 · via the switches SW: 4, SW 5 and the transistor Q 8 and the capacitors C 2, C 3 and 10 V is used to reduce the voltage when the differential voltage is maintained. a Reference voltage holding circuit that maintains the tomb-quad voltage. In addition, when the switches c 3 to W 5, the transistor Q8, a voltage source of 0V, and a voltage source of 10V are used, when the capacitor c 1 constitutes a differential voltage, the node a is set to an amplitude increase logic circuit 2 0 Threshold voltage detection circuit. The operation of the signal amplifier circuit 44 of this embodiment is the same as that of the signal amplifier circuit 40 of the seventh embodiment described above, and the description is omitted. In this way, by adding the capacitor c 3 ground of the node a, the voltage of the node a can be easily maintained at 5 V during the threshold threshold cancellation period (time T 4 2 to time T 4 4) shown in FIG. 15. That is, during the reset period (time to time T4 1 to time T42), in this example, the voltage of 5 V is accumulated in the capacitor C 3, and the node can be easily switched between the threshold and cancellation periods. a keeps k 5 V. [Tenth Embodiment] The tenth embodiment of the present invention replaces the transistor Q 8 of the ninth embodiment described above, and a switch 閛 T G 3 is provided. Hereinafter, it will be described in detail based on the drawings. Figure 19 shows the signal increase related to the 10th embodiment of the present invention. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -44 ·-丨 丨 丨 丨 丨 丨 丨 丨 丨! * Loading! < Please read the note on the back page first: Order · • Line · Printed by the Consumers 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 54 8 47 Printed by the Consumers' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 _ B7 _ V. Statement Statement ) The structure and circuit diagram of the main part of the circuit. Fig. 2 is a timing chart of the operation of the signal amplification circuit shown in Fig. 19. As shown in FIG. 19, the signal amplification circuit 46 according to the tenth embodiment is configured to be provided with a switching gate T G 3 instead of the transistor Q 9 as compared with the ninth embodiment. The switching gate {3 is composed of a transistor Q 9 of type 11; ^ 1 ^ 〇8 transistor, and a transistor Q 1 0 of p-type transistor. The control terminal of transistor Q 9 is connected to one end of switch SW 6. The other end side of the switch SW 6 is connected to the output side of the inverter 2 0 b of the logic circuit 2 0 for amplitude amplification. The control terminal of the transistor 010 is connected to one end of the switch SW4. The other end side of the switch SW 4 is connected to the output side of the inverter 20 b of the logic circuit 20 for amplitude amplification. _ In this embodiment, via switches SW 4 to SW 6 and switching gates TG 3 and capacitors C 2, C 3 and 10 V voltage source, when capacitor C 1 forms a differential voltage, node a is maintained at the reference Reference voltage holding circuit. In addition, through the switches SW 3 to SW, the voltage source of the switching gates G 3 and 0 V, and the voltage source of 10 V, when the capacitor C 1 maintains a differential voltage, a node b is set to the signal amplification logic circuit 2 Threshold voltage of 0 threshold voltage detection circuit. Next, the operation of the signal amplification and the re-routing circuit 46 shown in FIG. 19 will be described with reference to FIG. 20. First, between time Ding 6 1 to time Ding 6 2, there is a reset period. That is, from time T 6 1 to time T 6 2, the self-timing control circuit 10 sends a control signal CS, and the switch 5 W 1, the switch SW 3 and the switch SW 5 of the signal amplifier circuit 40 are turned on, and the switch SW 2 And the switch SW 4 is turned off. At this moment T 6 1 ~ moment ------------ 111 · installation— * (Please read the precautions on the back page first) Order · · · Line · This paper size applies to Chinese National Standard (CNS ) A4 specification (210 X 297 mm) -45- 54 8 47 A7----- B7 -------------_______ V. Description of the invention (43)-I! 丨! —! I! 鬌 (Please read the note on the back page first) ding 6 2 Period ′ is used as the reference voltage V 1 at node a, for example, input 5 v. At the same time, 0 V is input to the node and 10 V is input to the node c. The next time T 6 2 to time τ 6 4 is a threshold period and a cancellation period. During the period from time T 6 2 to time τ 6 4, the timing control circuit 10 turns off the switches SW 1 to SW 3 and SW 5 and turns the switches SW 4 and SW 6 on. As a result, the transistor Q 9 and the transistor Q 1 0 are turned on. That is, the switching gate g 3 is opened. ~ Between this time T 6 2 ~ time T 6 4, the capacitor c 1 and the capacitor C 2 are short-circuited through the transistor Q 9 and the transistor Q 1 〇. For this reason, the voltage at node a is kept at 5 V ground, and the voltage at node b is changed from 0 to 10 volts printed by the consumer consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Then, at the time T 6 3 when the node b exceeds the threshold of the amplitude increase logic circuit 20, for example, 4.5 V, the output of the amplitude increase logic circuit 20 is inverted, and the output signal is shown as 10 volts. For this reason, the transistor Q 9 and the transistor Q 1 0 are turned off. That is, the transition gate T G 3 is in an opened and closed state. As a result, the node b is set to the threshold voltage of the output logic voltage of the logic circuit 20 for reverse amplitude increase. That is, a differential voltage of 5 V of the threshold voltage of the amplitude increasing edit circuit 20 and the reference voltage V 1 is stored in the capacitor C 1. That is, in this embodiment, a voltage of 0 · 5 V is accumulated in the capacitor C 1. The data sampling period is between the next time T 6 4 to time T 6 6. That is, during this time from Ding 6 4 to T 6 6 'the timing control circuit 1 0 is to turn on the switch SW 2. In addition, the switch sw 1 and the format of the paper are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -46- 476854 A7 B7 V. Description of the invention (44) Off SW 3 ~ s W 6 are closed. Between this time Ding 6 4 ~ time T 6 6. For example, the input signal I S changes from 4 V to 6 V. At this time, as the boundary of 5 V set by the reference voltage V 1, at time T 65, the output signal 0 S of the logic circuit 20 for amplitude increase changes from 0 V to 1 0 V. That is, at time T 6 5 when the input signal IS exceeds .5 · V, the voltage at node b exceeds 4 · 5 V of the threshold voltage of the logic circuit 20 for amplitude increase. Therefore, the output signal 0 S of the amplitude increase logic circuit 20 is switched from low to high. During the period from the next time T 6 6 to time T 67, the data retention period is presented. That is, during the period from time D6 to time T67, the timing control circuit 10 turns off the switches SW1 to SW5. During this time T 6 6 to time T 6 7, the input signal IS of the digital signal having an amplitude of 2 V which is input between the data sampling period (time T 6 4 to time T 6 6) is taken as the amplitude 1 0 V. The output signal 0S of the digital signal is temporarily held. However, operations other than this signal amplification circuit 40 are the same as those of the first embodiment. _ As described above, the signal amplifier circuit 4 6 related to this embodiment uses the signal line driver circuit 3, which can be used as a signal line driver circuit that operates with digital signals without increasing the scale and power consumption of external circuits. 3 ^ 1 In addition, when the signal amplification circuit 46 of the liquid crystal display device of this embodiment is used, the characteristics of the components in the signal line driving circuit are uneven, and the threshold voltage of the logic circuit 20 for amplitude increase is different in each block. When it is different, the digital signal of the input signal IS with a small amplitude can be sampled. That is, when the threshold voltage of the logic circuit for signal amplification 20 varies, the paper size applies the Chinese National Standard (CNS) A4 specification (210x297 meals). 47- 1_! ···· 0 (Please read the caution page on the back first) Order · --- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 476854 A7 — 'B7 _ V. Description of the invention (45) The signal can still be amplified by the circuit. 4 6 Normal operation. · Π —----------(Please read the caution page on the back first) [Eleventh embodiment] The eleventh embodiment shows the use of the logic circuit for amplitude increase of each of the above embodiments 2 0 An example of the circuit configuration. Fig. 21 is a diagram showing an example of a circuit configuration of a logic circuit 20 for amplitude amplification. From FIG. 21, it can be seen that the logic circuit 20 for amplitude increase is provided with a transistor Q 20 to Q 2 6 formed of a P-type M 0 S transistor, and a transistor Q 3 0 to a n-type M0S transistor. Q 3 6 is constructed. The logic circuit 20 for amplitude increase is because a level shift circuit is generally used, and the above description is omitted here. -· Line · However, the present invention is not limited to the above-mentioned first embodiment to the eleventh embodiment, and various modifications can be made. For example, for the operation timing of the threshold threshold cancellation period, when the threshold threshold voltage of the amplitude increase logic circuit 20 is sufficiently maintained within the period of the capacitor C1, the threshold threshold cancellation operation is not required for each data sample. ^ The Intellectual Property Bureau employee ’s cooperative of the Ministry of Economic Affairs prints 5 clothes. In each of the above embodiments, the threshold voltage of the logic circuit 20 for amplitude increase is detected through the process of increasing the voltage at node b, but it can also be reduced by During the process of the voltage at the node b, the threshold voltage of the logic circuit 20 is detected. That is, in each of the above embodiments, although the threshold voltage is detected at the timing when the output signal of the amplitude increase logic circuit is switched from low to high, it is also possible to detect the threshold when it is switched from high to low Threshold voltage. As described above, according to the present invention, the paper size of the logic circuit for amplitude increase is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) «48- 476854 Printed by the Consumers’ Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (46) The differential voltage between the threshold voltage and the reference voltage is maintained by the differential voltage to absorb the circuit. As a result, there will be variations in the characteristics of the elements that constitute the amplitude increase logic circuit. When the logic circuit's threshold is too high, the signal amplification circuit IE of the logic circuit will be used to operate. * [Twelfth Embodiment] The above is a description of the signal amplifier circuit 1 2 a of FIG. 2 related to the present invention, but the following is a load drive provided to the digital analog conversion circuit 16 a of FIG. 2 related to the present invention. The circuit will be specifically described with reference to the drawings. That is, an example in which the load driving circuit of the present invention is applied to a signal line driving circuit of a liquid crystal display device will be described below. The load driving circuit according to the twelfth embodiment of the present invention guarantees a differential voltage between the voltage of the input video signal and the threshold voltage of the logic circuit-"-.-Holding the capacitor and supplying control to the input video signal The on / off of the transistor of the voltage of the signal line is performed by a logic circuit, so that the threshold voltage difference of the logic output of the inversion logic circuit is absorbed by a capacitor. More details will be described below. FIG. 2 is a circuit diagram showing the structure of the main part of a load driving circuit according to the 12th embodiment of the present invention. FIG. 2 is a schematic block diagram showing the entire structure of a load driving circuit. FIG. The operation division diagram of the load driving circuit for sexual use and the load driving circuit for positive polarity. The signal line driving circuit 3 of Fig. 4 is constructed using a load driving circuit shown in Fig. 23. The load drive circuit in Figure 2 has the corresponding Chinese paper standard (CNS) A4 size (210 X 297 mm) for each letter paper size -49 · JIIII1IIIII — ·-I i (Please read the precautions on the back page first ) Order:-· Line · 476854 A7 B7 V. Description of the invention (47) The load driving circuit for the positive polarity 1 1 1 a provided by the line, and the load driving circuit Γ 11 for the negative polarity are pulled and switched to control these Load switching circuit 1 1 1 a, 1 1 lb. Switching control circuit for various switches 1 1 2 〇

.圖2 4係說明正極性用之負荷驅動電路1.1 1 a和負 極性用之負荷驅動電路1 1 1 b之機能區分圖。如此圖 2 4所示，於本實施形態中，輸入影像信號Vi η係〇 V 〜1 Ο V間之信號，將此分爲輸入影像信號V i η爲〇 V 〜5V和5 V〜10之2個情形，驅動正極性用之負荷驅 • · 動電路1 1 1 a和負極性用之負荷驅動電路Γ 1 1 b。 即，負極性用之負荷驅動電路1 1 1 b係預先將信號 線S設定於5 V，於輸入影像信號V i η爲0 V〜5 V之 時，將信號線S之電壓下降至輸入影像信號V i η之電壓 加以動作之緩衝電路。正極性用之負荷驅動電路1 1 1 a 係預先將信號線S設定於5 V，於輸入影像信號V i η爲 5 V〜1 0 V之時，將信號線S之電壓上昇至輸入影像信 號V i η之電壓加以動作之緩衝電路。被此等負荷驅動電 路1 1 1 a、1 1 1 b之任意者驅動，係經由開關切換控 制電路1 1. 2加以控制。 然而，本實施形態中，將預先設定於信號線S之電壓 ，設定於具有0〜1 0 V之電壓振幅之輸入影像信號 V i η之中間電壓的5 V，但設定於此中間電壓以外之電 壓亦可。 圖2 2係正極性用之負荷驅動電路11 1 a之電路圖 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -50 - --------------裝 i-J 0 <請先閱讀背面之注意事項本頁) 訂· i線· 經濟部智慧財產局員工消費合作社印製 476854 A7 B7 五、發明說明（ 48 ) il — 丨！！ — I·裝 i I (請先閱讀背面之注意事項本頁) 。各正極性用之負荷驅動電路1 i i a係如圖22所示， 具有開關S W 1 〇 1〜開關^禪104，和？1^〇8電晶 體戶斤成電晶體Q 1 〇 i，和將反相器呈2段縱連續連接之 邏輯電路1 1 3，和電容器C 1 Ο 1。經由正極性用之負 荷驅動電路1 1 1 a、1 i 1 b驅動之信號線S中，如圖 4所示’連接畫像顯示用之丁 f T、液晶容量及補助容量 等，圖2 2係簡化之故，令信號線S之負荷以等價性阻抗 R和電容器C102。 … 開關S W 1 〇 1、S w 1 〇 2之一端係連接於信號線 - . - .- .... s ’開關S W 1 〇 1之另一端係連接於開關s W 1 0 3之 一端和電容器C 1 〇 1之一端，於開關s W 1 0 3之另一 端中，供給輸入影像信號V i η。電容器C 1 0 1之另一 端係連接於邏輯電路1 1 3之輸入端子，邏輯電路1 1 3 .線. 經濟部智慧財產局員工消費合作社印制衣 之輸出端子係連接電晶體Q 1 〇 1之閘極端子。於電晶體 Q 1 0 1之源極端子施加第1之電壓V D D (例ία 1 0 V )，於該汲極端子連接開關S W 1 0 2之另一端。於開關 SW104之一端連接信號線S，於開關SW104之另 一端施加第2之電壓V D (例如5 V )。開關S W 1 〇 1 -J. 〜S W 1 〇 . 4係經由圖2 3所示開關切換控制電降1 1 2 切換控制。 圖2 2中，令開關SW1 0 1和電容器C 1 0 1之連 接點爲a ，令電容器C 1 〇 1和邏輯電路11 3之連接點 爲b，令邏輯電路1 1 3和電晶體Q 1 〇 1之連接點爲c ，令開關SW104、SW102之連接點爲d。 本紙張尺度適用中國國家標準（CNS)A4規格（210x 297公釐） · 51 · 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（ 49) 然而，電容器C 1. .〇 1則構成本實施形態之差分電壓 保持電路'第1之電壓V JDlD則構成本實施形態之第1電 壓供給電路。一· 圖2 5係圖2 2之負荷驅動電路11 l a內之各部定 時圖.，以下，使用此定時圖，說明圖2 2之雩路.動作。首 先，於時刻T 1 0 1〜T 1 0 2之期間內，開關切換控制 電路1 1 2係將開關SW1 0 1〜SW1 〇 3呈關閉，令 開關S W 1 0 4呈開啓。由此，信號線S之電壓（圖2 2 之d )係與苐2之電壓V D呈同樣之電壓（例如5 V )。 接著，於時刻T 1 〇 2〜T 1 〇 3之期間內，開關切 換控制電路1 1 2係僅令開關S W 1 〇 3呈開啓。由此， 圖2 2之a點之電壓係等於輸入影像信號V i η之電壓。 圖2 5中，輸入影像信號V i η之電壓係顯示7 · 5V之 例。惟開關S W 1 0 1呈關閉之故，信號線S (圖2 2之 -* · * 一一 d點）之電壓係維持於5 V。 在此，將反轉邏輯電路1 1 3之輸出邏輯的臨限値電 壓假定呈5·5V時，經由某種手段，將邏輯電路113 之輸入端子（圖2 2之b點）之電壓，設定於該邏輯電路 1 1 3之臨限値電壓。將此圖22之b點設定於+羅輯電路 1 1 3之臨限値電壓的手法係以後述之其他實施形態加以 說明。將此邏輯電路1 1 3之輸入端子設定於臨限値電壓 時，邏輯電路1 1 3之輸出端子（圖2 2之c點）之電壓 係理論上呈0 V和1 0 V之中間電壓的5 V前後。但是， 現實上圖2 2之b點之電壓係較臨限値電壓的5，5 V高 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）—一- 52- (請先閱讀背面之注意事項本頁) 裝 ··綠· A7 B7 五、發明說明（印) !!·裝 i J (請先閲讀背面之注意事項頁) 一些或低一些之故，此時邏輯電路1 1 3之輸出端子（圖 2 2之c點）之電壓係各呈1〇又，或呈〇¥。圖25中 ，顯示1 0 V之例。 惟，時刻T 1 0 1〜時刻T 1 0 2之期間係呈開關 S 0 1和開關SW 1 〇 2爲關閉之故，邏氣電路 1 1 3之輸出電壓爲任何V時，對於後述之時刻T 1 〇 3 以後之信號線S的輸入影像信號V i η之輸出，不會有任 何影響。 一 此時，開關S W 1 〇 3爲開啓之故，圖2 2之a點之 電壓係呈輸入影像信號V i η電壓的7 · 5 V。爲此，於 電容器C 1 0 1，保持輸入影像信號V i η之電壓（ 7 · 5ν)和邏輯電路113之臨限値（5 · 5V)之差 分電壓（2 V )。 ••線. 經濟部智慧財產局員工消費合作社印製 接著，時刻Τ 1 〇 3之後，開關切換控制電路1 1 2 係令開關S W 1 〇 1、s W 1 0 2呈開啓，開關 SW103;SW104呈關閉。於時刻Τ103之時點 ，圖2 2之a點係對7 · 5 V而言，d點係5 V之故，開 關SW1 01呈開啓時，a點之電壓被d點所連續而下降 。電容器C 1 0 1係維持上述差分電壓（2 V )之故，此 電容器C 1 0 1之另一端之圖2 2之b點之電壓亦追隨A 點之電壓下降，邏輯電路1 1 3之輸出則反轉，呈低準位 (例如0 V ) ^由此，電晶體Q 1 〇 1呈開啓，第1之電 壓V D D則介由電晶體Q 1 〇 1和開關s w 1 〇 2，供予 信號線S，信號線S (圖2 2之d點）之電壓則徐徐上昇 -53- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公餐） 476854 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（51 ) 〇 當信號線S之電壓上昏時，對應於此圖2 2之a點、 b點之電壓亦，上昇。然後，呈時刻T - 10 4，信號線S之 電壓等於輸入影像信號V i η之電壓的7 · 5 V，圖2 2 之a點之電壓亦等於7 . 5 V。電容器C 1 〇\1係保持上 述差分電壓（2 V )之故，圖2 2之b點之電壓係呈臨限 値電壓的5 · 5 V。爲此，邏輯電路1 1 3之輸出則再反 轉呈高準位（例如1 0 V )。由此，電晶體Q 1 0 Γ則呈 關閉。 電晶體Q 1 0 1呈關閉之時，信號線S.上之容量 C 1 〇 2係徐徐放電，於信號線S內，經由再分配電荷， 圖2 2之d點之電壓雖下降，邏輯電路1 1 3之輸入端子 (圖2 2之b點）之電壓則下降邏輯電路1 1 3之臨限値 電壓的時點，再將電晶體Q 1 0 1加以開啓，圖2 2之d 點之電壓係再上昇。將如此之動作，於電容器C 1經由保 持上述差分電壓（2 V )的狀態下加以重覆，信號線S ( 圖2 2之d點）之電壓係保持於輸入影像信號V i η之電 壓的7 . 5 V。 圖2 6係顯示負極性用之負荷驅動電路1 1 . b之詳 細柿成的電路圖。如圖26所示，負荷驅動電路1 1 lb 係電晶體Q 1 0 1爲η型，和電晶體Q 1 0 1之源極電極 接地之部分，與圖2 2之負荷驅動電·路1 1 1 a不同，其 他之構成則爲相同。 如以上所述，第1 2實施形態係於圖2 2所示電容器 請先'M讀背面之注意^項本*1> 裝 訂 •線 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -54 - 476854 A7 ___ B7 五、發明說明（52 ) C 1 〇 1保持差分電壓、之狀態，以開關SW 10 1、 s W 1 0 2和邏輯電路1 1, 3和電晶體Q 1 0 1構成回歸 迴圈之故，信號線S之電壓較輸入影像信號V i η之電壓 爲低時，將電晶體Q 1 〇 1呈開啓，進行信號線S之電壓 拉起之控制，於信號線S之電壓略等於輸入影释信號 V i η之電壓的時點，將電晶體Q 1 〇 1呈關閉^由此， 信號線S之電壓係設定呈略等於輸入影像信號V i η之電 Μ 〇 … 即，第1 2實施形態中，將邏輯電路1 1 3之臨限値 電壓和輸入影像信號V i η之電壓之差分電壓保持於電容 器C 1 0 1之後，於信號線S供給輸入影像信號V i η之 故，於構成邏輯電路1 1 3之電晶體之臨限値電壓有參差 之時，信號線S之電壓則不受該影響。 【第1 3實施形態】 ~ 圖2 2所示之邏輯電路1 1 3係組合電晶體加以構成 之故，經由電晶體之臨限値或移動度之參差，邏輯電路 1 1 3之輸出準位則變化，而有使得電路無法正常動作之 虞。在此，以下所示之第1 3實施形態係於電容器、_ C 1 0 1設定邏輯電路1 1 3之臨限値和輸入影像信號 V i η之電壓的差分電壓時，將點b設定於邏輯電路 1 1 3之臨限値電壓的臨限値電壓設定電路，具體地明白 化，將邏輯電路1 1 3之特性之參差相抵銷爲特徵者。 圖2 7係負荷驅動電路之第1 3實施形態之電路圖， ϋ張尺度適用中國國家標準（CNS)A4規格（21(^ 297公釐)-55- ' :~"" • 1IIII1I — — — — ! ^ · 1 I C請先閱讀背面之注意事項本頁) 訂·· 線- 經濟部智慧財產局員工消費合作社印制衣 476854 A7 B7 五、發明說明（53 ) -!!裝·！ * <請先閲讀背面之注意事項本頁) 與第1 2實施形態同樣地，做爲液晶顯示裝置之信號線驅 動電路3加以使用者。圖么7之負荷驅動電路係與圖2 2 同樣地，具有開關S W 1 0 1〜S W 1 0 4，和P Μ 0 S 電晶體所成電晶體Q 1 0 1 ，和將反相器.2段縱連續連接 之邏輯電路1 1 3，和電容器C 1 0 1。此外·.:，圖2 7之 負荷驅動電路係具有電容器C1 0 3，和開關SW1 〇 5 〜SW107，和 PMOS 電晶體 Q102、Q103。 電容器C 1 0 1、C 1 0 3之各一端和S W 1 〇 1、 S W 1 〇 3之各一端係相互連接。於電容器C1 01之另 一端，連接邏輯電路1 1 3之輸入端子和開關SW10 5 之一端，開關s W r 〇 5之另一端係設定於第3之電壓（ 例如0 V )。電容器C 1 〇 3之另一端係連接開關 s W 1 〇 6之一端，開關S W 1 〇 6之另一端係施加第4 之電壓（例如1 0 V )。 ί線· 於邏輯電路1 1 3之輸出端子中，連接開關~ 經濟部智慧財產局員工消費合作社印製 S W 1 〇 7之一端和電晶體Q 1 〇 1之閘極端子，於開關 SW107之另一端係連接電晶體Ql〇2、Q103之 各閘極端子。電晶體Q 1 〇 2之源極/汲極電極之中的一 方係連接於電谷§&0 1 〇 1和開關SW1 〇 5間_上另一方 係連接於取消端子C Ν。電晶體Q 1 0 3之源極/汲極電 極之中的一方係連接於電容器C 1 〇 3和開關S W 1 〇 6 間，另一方係連接於反轉取消端子C Ν·ΙΙ。於取消端子 C Ν中，施加於某周期呈〇 ν至1 〇 ν直線性變化的取消 電壓。於反轉取消端子CNR中，施加於某周期呈1 〇ν -56- 本紙張尺度過用中國國豕標準（CNS)A4規格（210 X 297公® ) 47令854 A7 B7 五、聲明說明（54) 至0 v直線性變化的反,轉取消電壓。 _ 2 7中，令開關S H 0 1、S W 1 〇 3和電容器 C 1 〇 1、C 1 〇 3之連接點爲a，令電容器C 1 0 1和 邏輯電路1 1 3之連接點爲b，令邏輯電路1 1 3 fp電晶 體Q 1 0 1之連接點爲c，令開關S W 1 〇 1、. SW1 〇 2之連接點爲d，令電容器C1 0 3和開關 SW106之連接點爲e。 然而，電容器C 1 0 1則構成本實施形態之差分電壓 保持電路，第1之電壓V D D則搆成本實施形態之第1電 壓供給電路。開關S W 1 0 5〜S W 1 〇 7和電晶體 Q102、Q10 3和電容器C103構成本實施形態之 臨限値電壓設定電路。 圖2 8係圖2 7之負荷驅動電路內之各部定時圖’以 下，使用此定時圖，說明圖2 7之電路動作。 首先，於時刻Τ 1 1 1〜Τ 1 1 2之期間內，開關切 換控制電路1 1 2係僅將開關S W 1 〇 4呈開啓。由此， 信號線S之電壓係與第2之電壓V D呈同樣之電壓（例如 5 V )。 ' 接著，於時刻Τ 1 1 2〜丁 1 1 3之期間內^^開關切 換控制電路1 1 2係將開關S W 1 0 1、S W 1 〇 2、 SW104、SW107呈關閉，將開關SW103、 SW105、SW106呈開啓。由此，圖27之a點之 電壓係等於輸入影像信號V i η之電壓。圖2 8中’輸入 影像信號V i η之電壓係顯示7 · 5 V之例。開關 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -57 · •I 丨 — ! !裝 i I » {請先閱讀背面之注意事項本頁) 16- i線· 經濟部智慧財產局員工消費合作社印製 476854 A7 B7 五、發明說明（55 ) s W 1 0 1呈關閉之故，信號線s (圖2 7之d點）之電 壓係維持於5 V ·。又，開鼴S w 1 〇 5、s w i 〇 6爲開 啓之故，電容器C 1 〇 1和開關sw 1 〇 5之連接點（圖 2 7之b點）係呈〇 v，電容器c 1 〇 3和開關 S W 1 〇 6之連接點（圖2 7之e點）係呈1 O.v。開關 SW107爲關閉之故，電晶體qi〇2、Ql〇3皆爲 關閉。 接著，於時刻丁 1 1 3〜時刻丁1 1 5之期間內，開 關切換控制電路1 1 2係僅令開關s w 1 0 7呈開啓。又 ，於時刻T 1 1 3〜時刻T 1 1 5之期間，取消端子c N 係直線地自Ο V變化至1 〇 v，反轉取消端子c N R係直 線地自1 Ο V變化至〇 V。然而，c N端子和C N R端子 之電壓設定係以開關切換控制電路1 1 2，或其他電路方 塊加以進行。 於時刻τ 1 1 3之時點，邏輯電路1 1 3之出係低 準位之故，電晶體Q 1 〇 2、Q 1 〇 3皆爲開啓，電容器 C 1 0 1和開關S W 1 〇 5之連接點（圖2 7之b點）之 電壓係徐徐'上昇，電容器C 1 〇 3和開關SW1 〇 6之連 接點（圖2 ·7之e點）之電壓係徐徐下降。 一 於時刻τ 1 1 4時，圖2 7之b點之電壓則超過邏輯 電路1 1 3之臨限値電壓（例如5 · 5 V )，邏輯電路 1 1 3之輸出係呈高準位（約1 〇 V )，電晶體Q 1 0 1 和電晶體Q 1 0 2、Q 1 0 3皆呈關閉。爲此，時刻 ΤΙ 1 4〜ΤΙ 1 5之期間內係呈圖27之b點之邏輯電 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -58 - > — — — — — 1 丨 — — — — I* II (請先閱讀背面之注意事項本頁) 言· i線. 經濟部智慧財產局員工消費合作社印製 476854 A7 B7 五、發明說明（56) 路1 1 3之臨限値電壓（例如5 · 5 V )，圖2 7之e點 電壓係呈所定電壓（例如4 “· 5 V )。 即，邏輯電路1 1 3之輸入電壓.較邏輯電路1 1 3之 臨限値電壓爲高之時點，電晶體q 1 〇 2、Q 1 0 3呈關 閉之故，邏輯電路1 1 3之輸入端子（圖2 7/之b點）之 電壓，則等於邏輯電路1 ^ 3之臨限値電壓地加以設定。 此時，圖2 7之點a係設定於輸入影像信號V i η之電壓 的7 · 5 V之故，於電容器c 1 Ο 保持輸入信號 V i η之電壓（7 · 5 V )和邏輯電路1 1 3之臨限値電 壓（5 · 5 V )之差分電壓（2 V )。 接著，呈時刻Τ 1 1 5時，開關切換控制電路1 1 2 係令開關S W 1 〇 1、S W 1 〇 2呈開啓，令開關 SW1 〇 3〜SW1 07呈關閉。於時刻丁 1 1 5之時點 ，信號線S之電壓爲5 V，圖2 2之a點之電壓係呈 7 · 5 V之故，受到信號線S之電壓之影響，圖^ 7之a 點之電壓則下降。電容器C 1 〇 1係保持上述差分電壓（ 2V)之故，追隨圖2 7之a點之電壓下降，降低邏輯電 路1 1 3之_入端子（圖27之b點）之電壓。此圖27 之點b之電壓則總究呈邏輯電路1 1 3之臨限値|壓以下 ，邏輯電路1 1 3之輸出則呈低準位（約0 V )。由此， 電晶體Q 1 0 1呈開啓，信號線S (圖2 7之d點）之電 壓則上昇，對應於此，圖2 7之a點、b點及e點之電壓 亦上昇。此等一連之動作間’電容器C 1 〇 1係保持差分 電壓（2 V )。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -59 · ί ---I------^ .1 — 9 (請先閲讀背面之注意事項本頁) - --線- 經濟部智慧財產局員工消費合作社印製 476854 A7 B7 五、發明說明（57 ) illlllllllllj ^ ·11 (請先閲讀背面之注意事項^本頁> 然後，呈時刻T 1 1 6時，信號線s及a點之電壓等 於輸入影像信號V i n之露壓的7 · 5 V。此商，電容器 C 1 〇 1係保持上述差分電壓（.2 V)之故，邏輯電路 1 1 3之輸入端子（圖2 7之b點）之電壓係呈臨限値電 壓的5 · 5V。爲此，邏輯電路1 13之輸出·端子則呈高 準位（約1 Ο V )。由此，電晶體Q 1 〇 1則呈關閉。信 號線S (圖2 7之d點）之電壓係經由容量C 1 〇 2之放 電徐徐下降，當下降至某程度時，再使電晶體q 1 〇 1加 以開啓，信號線S之電壓係再上昇。 如此地，電容器C 1 〇 1於保持分電壓（2 V )的狀 態下，將如上述之動作加以重覆，信號線S (圖2 7之d 點）之電壓係保持於輸入影像信號V i η之電壓（ 7 · 5 V ) 〇 線- 經濟部智慧財產局員工消費合作社印製 然而，於圖2 9顯示負極性用之負荷驅動電路 1 1 1 b之電路圖。負荷驅動電路1 1 1 b係將信^號線 S以Ο V〜5 V之範圍加以驅動的緩衝電路，爲此電晶體 Q 1 0 1爲η型Μ〇S電晶體，該源極端子係連接於接地 ，電晶體Q1 0 2、Q 1 0 3亦置換於Ν型MOS電晶體 。又，開關S W 1 〇 5係連接於1 Ο V之電壓端#，開關 S W 1 〇 6係連接於Ο V之電壓端子。電晶體Q 1 0 2之 源極端子係連接於反轉取消端子C N R，電晶體Q 1 0 3 之汲極端子係連接於取消端子C Ν。對此之外，爲與上述 正極性用之負荷驅動電路1 1 1 a同樣之構成、動作之故 ，在此省略該詳細說明。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公餐） -60- 476854 A7 B7 五、發明說明（58 ) 如以上所述，圖2. 7之電路係設置相互向相反方向進 行充放電的2個電容器C 1- 0 1、C 1 0 3 ’於邏輯電路 1 1 3之輸入端子（圖2 7之點b ).呈臨限値電壓的時點 ，令電晶體Q 1 0 2、Q 1 0 3呈關閉之故，可將圖2 7 之點b設定於邏輯電路1 1 3之臨限値電壓v爲此，邏輯 電路1 1 3之臨限値電壓爲參差之時，於此等電容器 C101保持邏輯電路113之臨限値電壓和輸入影像信 號V i η之電壓的差分電壓。 - 爲此，於圖2 8之時刻Τ 1 1 5以後，信號線S之電 壓較輸入影像信號V i η之電壓爲高時，將電晶體 Q 1 0 1呈關閉，拉下信號線S之電壓，信號線S之電壓 較輸入影像信號V i η之電壓爲低時，將電晶體Q 1 0 1 呈開啓，進行將信號線S之電壓拉起之控制，將信號線S 之電壓設定呈略等於輸入影像信號V i η之電壓。 然而，可將本實施形態之電晶體Q 1 0 2、Q 1 0 3 以轉換閘T G加以構成。圖3 0係將電晶體Q 1 0 2、 經濟部智慧財產局員工消費合作社印5衣 (請先閱讀背面之注意事項本頁) Q 1 0 3置換爲轉換閘T G之正極性用之負荷驅動電路 1 1 1 a之電路圖，圖3 1係將電晶體Q1 0 2、 Q 1 0 3置換爲轉換閘TG之負極性用之負荷驅動属路 1 1 1 b之電路圖。如此等圖3 1及圖3 2所示，將轉換 閘TG以P型之MOS電晶體Q131和N型之MOS電 晶體Q1 3 2加以構成，令P型之MOS電晶體Q1 3 1 之閘極端子介由反相器I V，連接於開關SW1 〇 7亦可 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -61 - 476854 A7 B7 五、發明說明（59 ) 【第14實施形態】 ^ ill — ! — ·裝 i I (請先閱讀背面之注意事項本頁) 第1 4寳施形態係簡化第1 3賓:施形態（圖27)之 電路者。 .圖3 2係負荷驅動電路之第1 4實施形態之電路圖， 與第1 2實施形態及第1 3實施形態词樣地，例如做爲圖 4所示液晶顯示裝置之信號線驅動電路3加以使用者。 圖3 2之電路係代替圖2 7之電路之電晶體Q 1 0 2 、Q 1 0 3，設置電晶體Q 1 0 4者爲特徵。電晶體 Q 1 0 4之源極/汲極電極之中的一方係連接於電容器 C 1 0 1和開關S W 1 〇 5間，另一方面係連接於電容器 C 1 0 3和開關S W 1 〇 5間。又，電晶體Q 1 0 4之閘 極端子係連接於開關S W 1 0 7之一端。 圖32中，令開關SW101 、SW103和電容器 C101、C103之連接點爲a ，令電容器C101和 邏輯電路1 1 3之連接點爲b，令邏輯電路1 1 3和電晶 體Q10 1之連接點爲c，令開關SW101、 經濟部智慧財產局員工消費合作社印製 SW102之連接點爲d，令電容器C103和開關 S W 1 0 6.之連接點爲e。 ^ 然而，電容器C 1 0 1則構成本實施形態之差分電壓 保持電路，第1之電壓V D D則構成本實施形態之第1電 壓供給電路，開關S W 1 〇 5〜S W Γ 〇 7和電晶體 Q 1 0 4和電容器C 1 0 3構成本實施形態之臨限値電壓 設定電路。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐)-62- 476854 A7 B7 五、聲明說明（βΟ ) 〜 圖3 3係圖3 2之負荷驅動電路內之各部β定時圖，以 下，使用此定時圖，說明圖4 2之電路動作。 首先，於時刻Τ 1 2 1〜Τ 1 2.2之期間內，開關切 換控制電路1 1 2係僅將開關S W 1 〇 4呈開啓。由此， 信號線S之電壓係與第2之電壓V D呈同樣之電壓（例如 5 V ) 〇 裝 接著，於時刻Τ 1 2 2〜Τ 1 2 3之期間內，開關切 換控制電路1 1 2係將開關S W 1 〇 1 ·、s W 1 〇 2、 S W 1 〇 4、S W 1 0 7呈關閉，將開關S W 1 〇 3、 SW105、SW106呈開啓。由此，圖32之a點之 電壓係呈輸入影像信號V i η之電壓（例如7 · 5 V )。 訂 此期間內，係開關S W 1 〇 1呈關閉之故，信號線S (圖 3 2之d點）之電壓係維持於5V。又，開關SW1 〇 5 、S W 1 〇 6爲開啓之故，圖3 2之b點係呈0 V，e點 - 一— 係呈1 0 V。開關S W 7爲關閉之故，電晶體Q 1 0 4爲 關閉狀態。 ' 經濟部智慧財產局員工消費合作社印製 接著，於時刻τ 1 2 3〜時刻τ 1 2 5之期間內，開 關切換控制電路1 1 2係僅令開關S W 1 0 7呈開啓。此 時，電晶體Q 1 0 4係開啓狀態之故，圖3 2之>點和e 點則短路，兩電壓向一致方向變化。具體而言，b點之電 壓係自0 V徐徐上昇，e點之電壓係自1 0 V徐徐下降。 呈時刻T1 24之時，邏輯電路1 1 3之輸入端子（ 圖3 2之b點）之電壓超越邏輯電路1 1 3之臨限値電壓 ，邏輯電路1 1 3之輸出電壓係娛化呈高準位（例如 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） -63 - 476854 - ^ : A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（61 ) 1 Ο V )。由此，電晶體Q 1 〇 3則關閉，1)點之電壓係 不會上昇超過此·。由此，露輯電路1 1 3之輸入端子（圖 3 2之b點）之電壓係赂等於邏輯電路1 1 3之臨限値電 壓。此時，圖3 2之a點係維持於輸入影像信號V i η之 電壓的7 · 5V之故，於電容器C101，保持輸入電壓 (7 · 5 V )和邏輯電路1 1 3之臨限値電壓（5 · 5 V )之差分電壓（2 V ) 〇 接著，呈時刻Τ 1 2 5時，開關切換控制電路1 1 2 係令開關S W 1 〇 1、S W 1 〇 2呈開啓，令開關 S W 1 〇 3〜S W 1 0 7呈關閉。由此，圖3 2之點d、 點a之電壓則下降，電容器C 1 〇 1係保持差分電壓（ 2 V)之故，b點之電壓亦追隨下降。爲此，邏輯電路 1 1 3之輸出則呈低準位（約Ο V )，電晶體Q 1 0 1呈 開啓，信號線S之電壓則徐徐上昇。之後，追隨信號線S 之電壓之上昇，b點之電壓亦上昇之故，呈時刻ΐ 1 2 6 時，b點之電壓則超過邏輯電路1 1 3之臨限値電壓，反 轉邏輯電路1 1 3之輸出，呈高準位（例如1 Ο V )。由 此，電晶體Q 1 0 1則關閉，信號線S之電壓係不會上昇 至其上。 ^ 如以上所述，第1 4實施形態係將電容器C 1 0 1、 C 1 0 3之各一端，各連接於電晶體Q 1 0 4之源極/汲 極電極，將電晶體Q 1 0 4之閘極電極對應邏輯電路 1 1 3之輸出電壓加以控制之故’可將圖3 2之b點之電 壓和e點之電壓相反地控制，與第1 3實施形態同樣地， (·請先閱讀背面之注意事項 本頁) 裝 -線· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -64- 476854 A7 B7 五、發明說明（ 62 ) 將邏輯電路.1 1 3之輸入端子（圖32之13點)之電壓設， 定略等於邏輯電路1 1 3之臨限値。爲此，以較上述第 1 3之實施形態簡單之電路構成，於電容器C 1 0 1保持 邏輯電路1 1 3之臨限値電壓和輸入影像信號V i η、之電 壓的差分電壓。 於圖3 4顯示負極性用之負荷驅動電路1 1 lb之詳 細構成之電路圖。如圖3 4所示，負荷驅動電路1 1 1 b 係在於電晶體Q 1 0 1、Q 1 0 4爲η型Μ 0 S電晶體， 和電晶體Q 10 1之源極電極爲接地之點上，與圖3 2之 負荷驅動電路1 1 1 a不同，其他則爲相同。 然而，可將本實施形態之電晶體Q 1 〇 4以轉換閘 T G加以構成。圖3 5係將電晶體Q 1 0 4置換爲轉換閘 T G之正極性用之負荷驅動電路1 1 1 a之電路圖，圖 3 6係將電晶體Q 1 0 4置換爲轉換閘T G之負極性用之 負荷驅動電路1 1 lb之電路圖。如此等圖35¾圖36 所示，將轉換閘丁 G以P型之Μ 0 S電晶體Q 1 4 1和N 型之M〇S電晶體Q 1 4 2加以構成，另一方面介由反相 器I V，連-於開關S W 1 〇 7亦可。 【第1 5實施形態】 有關第1 5實施形態之負荷驅動電路係於電容器保持 輸入影像信號之電壓和邏輯電路之臨限値電壓之差分電壓 時，於電容器之輸入影像信號側之端子連接另外之電容器 ，將此端子可安定保持於輸入影像信號之電壓者。更詳細 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -65 - --------------裝·ΓΙ Λ (請先閱讀背面之注意事項本頁) 訂· -線· 經濟部智慧財產局員工消費合作社印製 476854 A7 B7 五、發明說明（63 ) 而言說明於下。。 (請先閱讀背面之注意事項本頁) 圖3 7係正極性用之氮荷驅動電路Γ1 1 a之電路圖 。各負荷驅動電路1 11 a係如调3 7所示，具有開關 S W 1 〇 1〜S W 1 〇 7，和做爲類比開關之P Μ〇S電 晶體Q 1 0 1〜Q 1 0 3，和將反相器2段縱連.續連接之 邏輯電路1 1 3，和電容器C 1 〇 1〜c i 〇 4。開關 3〜1〇1〜3〜1〇7係經由圖23所示開關切換控制 電路1 1 2切換控制。 開關S W 1 〇 1、S W 1 〇 2之一端係連接於信號線 S，開關S ’W 1 〇 1之另一端係連接於開關S W 1 0 3之 一端和電容器C 1 〇 1、C 1 〇 3、C 1 〇 4之一端。開 關s W 1 〇 3之另一端係供給輸入影像信號V i η。 經濟部智慧財產局員工消費合作社印製 電容器C 1 〇 1之另一端係連接於邏輯電路1 1 3之 輸入端子和開關S W 1 〇 5之一端和電晶體Q 1 0 2之汲 極端子。邏輯電路1 1 3之輸出端子係連接於電晶~體 Q 1 0 1之閘極端子和開關S W 1 〇 7之一端。電晶體 Q 1 0 1之源極端子中，施加第1之電壓V D D (例如 10V)，於該汲極端子中連接開關SW102之另一端 。於開關S W 1 〇 4之一端連接信號線S，於開關^_ S W 1 〇 4之另一端施加第2之電壓V D D (例如5 V ) 〇 電晶體Q 1 0 2之源極端子係連接於取消端子c Ν。 於此取消端子C Ν施加於某周期呈0 V至1 〇 V直線性變 化的取消電壓。開關SW1 〇 5之另一端係設定於第3之 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -66 - 476854 A7 B7 五、發明說明（64) 電壓（例如0 V ) 〇 電容器C 1 0 3之另P端係連接於開關s W 1 〇 6之 一端和電晶體Q 1 0 3之源極端子。電晶體Q 1 0 3之汲 極端子係連接反轉於取消端子C NR。於此反轉取消端子 C N R施加於某周期呈1 0 V至ΰ V直線性琴；ίΐ：的反轉取 消電壓。開關SW1 〇 6之另一端係設定於第4之電壓（ 例如10V)。電容器C104之一端係設定於第5之電 壓（例如0 V )。 ' 圖3 7中，令開關S w 1 0 1、S W 1 0 3和電容器 C 1 〇 1、C 1 0 3、C 1 0 4之連接點爲a，令電容器 C 1 〇 1和邏輯電路1 1 3之連接點爲b，令邏輯電路 1 1 3和電晶體Q 1 0 1之連接點爲c，令開關 SW101、SW102之連接點爲d，令電容器 C 1 〇 3和開關S W 1 〇 6之連接點爲e。 然而，電容器C 1 〇 1則構成本實施形態之i分電壓 保持電路，第1之電壓V D D則構成本實施形態之第1電 壓供給電路。開關S W 1 〇 5〜S W 1 〇 7和電晶體 Q 1 0 2、Q 1 0 3和電容器C 1 0 3構成本實施形態之 臨限値電壓設定電路，電容器C 1 0 4構成本實|形態之 輸入電壓維持電路。 圖3 8係圖3 7之負荷驅動電路1 1 1 a內之各部定 時圖，以下，使用此定時圖，說明圖3 7之負荷驅動電路 1 1 1 a之動作。 首先，於時刻T1 3 1〜T1 3 2之期間內’開關切 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） -67- 111!·裝· ί 猶 (請先閱讀背面之注意事項本頁) 訂： •線· 經濟部智慧財產局員工消費合作社印製 476854 Α7 Β7 五、發明說明（65 ) ί請先閱讀背面之注意事項本頁) 換控制電路1 1 2係僅將開關S W 1 0 4呈開啓。由此’ 信號線S之電壓係與第2之^電壓V D呈同樣之電壓（例如 5 V )。 接著，於時刻T 1 3 2〜T 1 3 3之期閒內’開關切 換控制電路1 1 2係將開關S W 1 0 1、S W 1/，〇 2、 SW104、SW107呈關閉，將開關SW103、 SW105、SW106呈開啓。由此，圖37之a點之 電壓係呈輸入影像信號V i η之電壓。圖3 7中，輸入影 像信號V i η之電壓係顯示7 · 5 V之例。如上所述’電 壓爲5V以上的7·5V之故，正極性用之負荷驅動電路 1 1 1 a則驅動信號線S，又，開關S W 1 〇 1呈關閉之 故，信號線S (圖3 7之d點）之電壓係維持於5 V。更 且，開關SW105、SW106爲開啓之故，電容.器 C 1 〇 1和開關S W 1 〇 5之連接點（圖3 7之b點）係 呈0V，電容器C 1 〇 3和開關SW1 〇 6之連^點（圖 3 7之e點）係呈1 Ο V。開關S W 1 〇 7爲關閉之故， 經濟部智慧財產局員工消費合作社印5衣 電晶體Q1 02、Q1 03皆爲關閉。又，電容器 C 1 04係k持輸入信號V i η的電壓之7 · 5V。 接著，於時刻Τ 1 3 3〜時刻Τ 1 3 5之期翼內，開 關切換控制電路1 1 2係僅令開關S W 1 〇 7呈開啓。又 ，於時刻Τ 1 3 3〜時刻Τ 1 3 5之期間，取消端子C Ν 係直線地自0 V變化至1 〇 V，反轉取消端子C N R係直 線地自1 0 V變化至0 V。然而，C Ν端子和CNR端子 之電壓設定係以開關切換控制電路1 1 2，或其他電路方 -68- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 476854 A7 B7 五、發明說明（66) 塊加以進行。 於時刻丁 1 3 3之時點，邏輯電路1 1 3之輸出係低 準位之故，電晶體Q 1 〇 2、Q 1 〇_ 3皆爲開啓，電容器 C 1 0 1和開關S W 1 〇 5之連接點（圖3 7之b _)之 電懕係徐徐上昇，電容器C 1 〇 3和開關S W· 1 0 6之連 接點（圖3 7之e點）之電壓係徐徐下降。 訂： 於時刻丁 1 3 4時，圖3 7之b點之電壓則超過邏輯 電路1 1 3之臨限値電壓（例如5 · 5: V )，邏輯電路 1 1 3之輸出係呈高準位（約1 〇 V )，電晶體Q 1 0 1 和電晶體Q 1 0 2、Q 1 0 3皆呈關閉。爲此，時刻 T 1 3 4〜T 1 3 5之期間內係呈圖3 7之b點之邏輯電 路1 1 3之臨限値電壓（例如5 · 5 V )，圖3 7之e點 電壓係呈所定電壓（例如1 Ο V - 5 · 5 V = 4 · 5 V ) 〇 -線- 經濟部智慧財產局員工消費合作社印製 即，邏輯電路1 1 3之輸入電壓較邏輯電路1 1 3之 臨限値電壓爲高之時點，電晶體Q 1 0 2呈關閉之故，圖 3 7之b點之電壓等於邏輯電路1 1 3之臨限値電壓地加 以設定。此時，圖3 7之點a係經由電容器C 1 0 4安定 維持於設定於輸入影像信號V i η之電壓的7 ·尽V。爲 此，邏輯電路113之臨限値電壓（5·5V)和輸入影 像信號V i η之電壓（7 · 5V)之差分電壓則保持於電 容器C 1 0 1。 接著，呈時刻τ 1 3 5時，開關切換控制電路1 1 2 係令開關S W 1 0 1、S W 1 〇 2呈開啓，令開關 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -69- 476854 A7 B7 五、發明說明（67) (請先閱讀背面之注意事項本頁) S W 1 〇 3〜S W 1 Q、7呈Μ閉。於時刻T 1 3 5之時點 ’信號線S之電壓爲5 V、櫚3 7之a點之電壓係呈 7 · 5 V之故，受到信號線s之電壓之影響，圖3 7之a 點之電壓則下降。電容器C 1 〇 1係保持上述差分電壓（ 2V)之故，追隨a點之電壓下降，降低邏腎.電路1 1 3 之輸入端子（圖3 7之b點）之電壓。總究，邏輯電路 1 1 3之輸入端子之電壓呈邏輯電路1 1 3之臨限値電壓 以下，邏輯電路1 1 3之輸出則呈低準位（約Ο V )。由 此，電晶體Q 1 Ο Γ呈開啓，信號線S (圖3 7之d點） 之電壓則上昇，對應於此，圖3 7之a點、b點及e點之 電壓亦上昇。 經濟部智慧財產局員工消費合作社印制农 然後，呈時刻T136時，邏輯電路113之輸入端 子（圖3 7之b點）之電壓超過邏輯電路1 1 3之臨限値 ’邏輯電路1 1 3之輸出端子則呈高準位（約1 Ο V )。 由此，電晶體Q 1 0 1則呈關閉，信號線S (圖7之d 點）之電壓係經由容量C 1 0 2之放電徐徐下降，但是， 當下降至某程度時，圖3 7之d點之電壓較邏輯電路 1 1 3之臨限値電壓爲低，邏輯電路1 1 3之輸出端子係 再呈低準位（約〇 V )。爲此，再使電晶體Q 1 JCU 1加以 開啓，信號線S之電壓係再上昇。於此一連串動作中，電 容器CIO 1於保持上述差分電壓（2V)。 於時刻T 1 3 6以後，經由重覆如此動作，信號線S (圖3 7之d點）係保持於輸入影像信號V i η之電壓（ 約 7 · 5 V )。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -70 - 476854 A7 B7 五、發明說明（68) 然而，於圖3 9顯示負極性用之負荷驅動電路 1 lib之電路圖。此負極性用之負荷驅動電路1 1 1 b 係將信號線S以Ο V〜5 V之範圍加以驅動的緩衝電路， 爲此電晶體Q 1 0 1爲η型Μ 0 S電晶體，該源極端，子係 連接於接地，電晶體Q 1 0 2、Q 1 0 3亦置換:於Ν型 Μ〇S電晶體。又，開關S W 1 〇 5係連接於1 〇 V之電 壓端子，開關SW1 〇 6係連接於0V之電壓端子。電晶 體Q 1 0 2之源極端子係連接於反轉取消端子C N R，電 晶體Q 1 0 3之汲極端子係連接於取消端子C Ν。對此之 外，爲與上述正極性用之負荷驅動電路1 1 1 a同樣之構 成、動作之故，在此省略該詳細說明。 如以上所述，根據本實施形態之負荷驅動電路 1 1 1 a 、1 1 1 b時，信號線S之電壓較輸入影像信號 V i η之電壓爲高之時，將電晶體Q1 〇 1呈關閉，拉下 信號線S之電壓，信號線S之電壓較輸入影像信~號V i η 之電壓爲低時，將電晶體Q 1 Ο 1開啓，進行拉起信號線 S之電壓的控制之故，將信號線S之電壓設定呈略等於輸 入影像信號V i η之電壓，且加以維持。 又，如圖37及圖38所示，於特性參差取_與期間（ 時刻丁 1 3 3〜丁 1 3 5 )，將輸入影像信號V i η之電 壓和邏輯電路1 1 3之臨限値電壓的差分電壓，保持於電 容器C 1 〇 1，將此差分電壓於保持於電容器C1 0 1之 狀態，將電晶體Q 1 〇 1呈開/關控制之故，邏輯電路 1 1 3之臨限値爲參差狀態時，於安定期間（時刻 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -71 - — Ί! -裝 f J I (請先閱讀背面之注意事項本頁) 訂·- -·線- 經濟部智慧財產局員工消費合作社印製 476854 A7 B7 五、發明說明（69) 丁 1 3 6以後），將供予信號線S之電壓，可維持與輸入 影像信號V i η之電壓略等之電壓。 illlllllllln ^ i — <請先閱讀背面之注意事項本頁> i線· 又：，如圖3 7及圖3 8所示，於圖3 7之a點’連接 電容器C 1 〇 4之故，將特性參差取消期間（時刻 丁 1 3 3〜T 1 3 5 )之a點電壓，安定保持·.於對電容器 之寫入期間（時刻T 1 3 2〜T 1 3 3 )所設定之輸入影 像信號V i η之電壓。即，無電容器C 1 0 4之時’特性 參差取消期間（時刻Τ 1 3 3〜Τ 1 3 5 )之圖3 7之a 點電壓係由於電晶體Q 1 0 2、Q 1 0 3之容量等’多少 呈浮動狀態。爲此，於本實施形態中，於圖3 7之a點’ 經由連接電容器C 1· 0 4，於對電容器之寫入期間（時刻 T132〜T133)，將輸入影像信號Vin之電壓和 〇V之差分電壓保持於電容器C 1 0 4，將此於特性參差 取消期間（時刻T 1 3 3〜丁 1 3 5 )亦保持地，將a點 安定地維持於輸入影像信號V i η。 一 然而，可將本實施形態之電晶體Q 1 0 2、Q 1 〇 3 以轉換閘T G加以構成。圖4 0係將電晶體Q 1 0 2、 經濟部智慧財產局員工消費合作社印制衣 Q 1 0 3置k爲轉換閘T G之正極性用之負荷驅動電路 1 1 1 a之電路圖，圖4 1係將電晶體Q 1 〇 2、f Q 1 0 3置換爲轉換閘TG之負極性用之負荷驅動電路 1 1 lb之電路圖。如此等圖41及圖42所示，將轉換 閘TG以P型之M〇S電晶體Q 1 3‘1和N型之MO S電 晶體Q 1 3 2加以構成，令P型之Μ 0 S電晶體Q 1 3 1 之閘極端子介由反相器I V，連接於開關S W 1 〇 7亦可 本紙張尺度導用中國國豕標準（CNS)A4規格（210 X 297公爱） -72 · 476854 ： A7 B7 五、發明說明（.70) — 【第1 6實施形態】 有關第1 6實施形態之負荷驅動電路係將上述第1 5 實施形態之負荷驅動電路加以簡化者。 二:· 圖4 2係負荷驅動電路之第1 6實施形態之電路，與 上述第1 5實施形態同樣地，例如做爲圖4所示液晶顯示 裝置之信號線驅動電路3加以使用者夂 圖4 2之電路係代替圖3 7之電路之電晶體Q 1 0 2 、Q 1 0 3，設置電晶體Q 1 0 4者爲特徵。電晶體 Q 1 0 4之源極/汲極電極之中的一方係連接於電容器 C 1 0 1和開關S W 1 〇 5間，另一方面係連接於電容器 C 1 0 3和開關S W 1 0 5間。又，電晶體Q 1 0 4之閘 極端子係連接於開關S W 1 0 7之一端。 圖42中，令開關SW101、SW103fc電容器 C101、C103、C104之連接點爲a ，令電容器 C 1 0 1和邏輯電路1 1 3之連接點爲b，令邏輯電路 1 1 3和電1體Q 1 0 1之連接點爲c，令開關 SW101、SW102之連接點爲d，令電容器_ C 1 0 3和開關SW1 06之連接點爲e。 然而，電容器C 1 0 1則構成本實施形態之差分電壓 保持電路，第1之電壓V D D則構成本實施形態之第1電 壓供給電路，開關S W 1 〇 5〜S W 1 0 7和電晶體 Q 1 0 4和電容器C 1 0 3構成本實施形態之臨限値電壓 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） · 73 - ίι.------------裝I * {請先閲讀背面之注意事項本頁) 訂： --線- 經濟部智慧財產局員工消費合作社印製 4 5 8 7 經濟部智慧財產局員工消費合作社印剔衣 A7 ---------- B7 ______五、發明說明（71 ) 設定電路，電容器C 1.0 4構成本實施形態之輸入電壓維 持電路。 .、 圖4 3係圖4 2之負荷驅動電路1 1 1 a內之各部定 Bf Η，以下，使用此定時圖，說明圖42之負荷驅動電路 1 1 1 a之動作。 首先，於時刻T 1 4 1〜T 1 4 2之期間內，開關切 換控制電路1 1 2係僅將開關S W 1 〇 4呈開啓。由此， ft號線S之電壓係與第2之電壓V D呈同樣之電壓（例如 5 V ) 〇 •- 接著，於時刻τ 1 4 2〜丁 1 4 3之期間內，開關切 換控制電路1 1 2係將開關S W 1 〇 1、S W 1 〇 2、 SWl〇4、SWl〇7呈關閉，將開關SW103、 SW105 、SW106呈開啓。由此，圖42之a點之 電壓係呈輸入影像信號V i η之電壓（例如7 · 5 V )。 此期間內，係開關S W 1 〇 1呈關閉之故，信號線S (圖 4 2之d點）之電壓係維持於5 V。又，開關S W 1 〇 5 、SW106爲開啓之故，圖42之b點係呈0V，e點 係呈1 0 V、開關S W 1 〇 7爲關閉之故，電晶體 Q 1 0 4爲關閉狀態。又，電容器C 1 0 4係保择輸入信 號Vi η之電壓的7· 5V。 接著，於時刻Τ 1 4 3〜時刻Τ 1 4 5之期間內，開 關切換控制電路1 1 2係僅令開關S W 1 0 7呈開啓。此 時，電晶體Q 1 0 4係開啓狀態之故，圖4 2之b點和e 點則短路，兩電壓向一致方向變化。具體而言’ b點之電 請 先 閱 讀 背 面 之 注 意 事 項 裝 頁 訂 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公t ) -74- 476854 τ ' Α7 _ Β7 五、發明說明（ 72) 壓係自Ο V徐徐上昇，.e點之電壓係自1 Ο V徐徐下降。 i I I I 1--— — — — — — i — * ί請先閱讀背面之注意事項本頁) 呈時刻T 1 4 4之時 >邏輯電路1 1 3之輸入端子（ 圖4 2之b點）之電壓超越邏輯電路1 1 3之臨限値電遷 ’邏輯電路1 1 3之輸出電壓係變化呈高準位（例如、 1 Q V )。由此，電晶體Q 1 0 4則關閉，b/點之電壓係 不會上昇超過此。由此，邏輯電路1 13之輸入端子（圖 4 2之b點）之電壓係設定略等於邏輯電路1 1 3之臨限 値電壓。此時，圖4 2之a點係經由電容器C 1 0 4，安 定維持於輸入影像信號V i η之電壓的7 · _5 V。因此， 邏輯電路1 1 3之臨限値電壓（5 · 5 V )和輸入影像信 號V i η之電壓（例如7·5V)之差分電壓（2V)， 則保持於電容器C 1 Ο 4。 接著，呈時刻τ 1 4 5時，開關切換控制電路1 1 2 係令開關S W 1 〇 1、S W 1 〇 2呈開啓，令開關 - …’ 一一 --線- 經濟部智慧財產局員工消費合作社印製 SW1 0 3〜SW1 07呈關閉。由此，電容器c 1 01 係於保持上述差分電壓（2 V )之狀態，圖4 2之a點、 b點之電壓係暫時下降，令電晶體Q 1 〇 1開啓，信號線 S之電壓則徐徐上昇。 接著，呈時刻T1 46時，邏輯電路1 1 3各輸入端 子（圖4 2之b點之）電壓則超過邏輯電路1 1 3之臨限 値電壓，邏輯電路1 1 3之輸出端子則呈高準位（例如 1 0 V )。由此，電晶體Q 1 〇 1則關閉，信號線S (圖 4 2之d點）之電壓係自容量C 1 0 2之放電，徐徐下降 。但是，下降至某個程度時，圖4 2之d點電壓較邏輯電 -75· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 476854 . ..· ... A7 B7 五、發明說明（73 ) {請先閲讀背面之注意事項本頁) 路1 1 3之臨限値電壓爲低，.邏輯電路1 1 3之輸出端子 係再呈低準位（·約〇 V ) 4。“爲此，再使電晶體Q 1 0 1開 啓，信號線S之電壓再上昇。 於時刻丁 1 4 6之後，經由重覆如此動作，信號線S (圖.4 2之d點）係保持於輸入影像信號V i\n之電壓（ 約 7 · 5 V ) 〇 然而，於圖3 9顯示負極性用之負荷驅動電路 1 1 1 b之電路圖。此負極性用之負荷驅動電路1 11 b 係將信號線S以Ο V〜5 V之範圍加以驅動的緩衝電路， 爲此電晶體Q 1 0 1爲η型Μ〇S電晶體，該源極端子係 連接於接地，電晶體Q 102、Q103亦置換於Ν型 MOS電晶體。又，開關SW1 〇 5係連接於1 0V之電 壓端子，開關S W 1 〇 6係連接於0 V之電壓端子。對此 之外，爲與上述正極性用之負荷驅動電路1 1 1 a同樣之 構成、動作之故，在此省略該詳細說明。 經濟部智慧財產局員工消費合作社印製 如以上所述，根據本實施形態之負荷驅動電路 1 1 1 a 、1 1 lb時，信號線S之電壓較輸入影像信號 V i η之電壓爲高之時，將電晶體Q1 0 1呈關閉’拉下 信號線S之電壓，信號線S之電壓較輸入影像信..遞· V i η 之電壓爲低時，將電晶體Q 1 Ο 1開啓，進行拉起信號線 S之電壓的控制之故，將信號線S之電壓設定呈略等於輸 入影像信號V i η之電壓，且加以維持。 又，如圖4 2及圖4 3所示，於特性參差取消期間（ 時刻Τ143〜Τ145)，將輸入影像信號V in之電 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -76- 476854 - - - · - r . ' A7 B7 五、發明說明（料） 壓和邏輯電路1 1 3之臨限値電壓的差分電壓，保持於電 容器C 1 〇 1，將此差分露壓於保持於電容器C 1 0 1之 狀態，將電晶體Q 1 0.1呈開/關控制之故，邏輯電路 1 1 3之臨限値爲參差狀態時’於安定期間（時刻 丁 1.4 6以後），將供予信號線S之電壓’可維持與輸入 影像信號V i η之電壓略等之電壓。 而且，如圖4 2及圖4 3所示’於圖4 2之a點’連 接電容器C 1 0 4之故，將特性參差取消期間（時刻 T 1 4 3〜T 1 4 5 )之a點電壓’安定保持於對電容器 之寫入期間（時刻T 1 4 3〜T 1 4 5 )所設定之輸入影 像信號V i η之電壓。即，無電容器C 1 0 4之時，特性 參差取消期間（時刻Τ1 43〜Τ1 45)之圖42之a 點電壓係由於電晶體Q 1 〇 2、Q 1 0 3之容量等’多少 呈浮動狀態。爲此，於本實施形態中，於圖4 2之a點’ 經由連接電容器C 1 0 4 ’於對電容器之寫入期間（時刻 丁142〜丁143)，將輸入影像信號Vin之電壓和 0 V之差分電壓保持於電容器C 10 4 ’將此於特性參差 取消期間（時刻T 1 4 3〜T 1 4 5 )亦保持地，將a點 安定地維持於輸入影像信號V i η。 < 然而，可將本實施形態之電晶體Q 1 0 4以轉換閘 T G加以構成。圖4 5係將電晶體Q 1 〇 4置換爲轉換閘 τ G之正極性用之負荷驅動電路1 1 1 a之電路圖，圖 4 6係將電晶體Q 1 〇 4置換爲轉換閘T G之負極性用之 負荷驅動電路1 1 1 b之電路圖。如此等圖4 5及圖4 6 本紙張尺度適用中國國家標準（CNS)A4規格（210x 297公釐） -77 - — — — — — — Ί — ·裝·！ (請先閱讀背面之注意事項本頁) . --線- 經濟部智慧財產局員工消費合作社印製 476854 A7 B7 五、發明說明（75) 111!11裝·！ <請先閱讀背面之注意事項本頁) 所示，將轉換閘T G以P型之Μ 0 S電晶體Q 1 4 1和N 型之Μ 0 S電晶體Q 1 4么加以構成，另一方面介由反相 器I V，連接於開關S W 1 0 7-亦可。 然而，本發明係非限定於上述第1 2實施形態〜第 1 6實施形態可進行種種之改變。例如，於Ji述第1 2實 施形態〜第1 6實施形態中，說明將有關本發明之負荷驅 動電路適用於液晶顯示裝置內之信號線驅動電路3之例者 ，但本發明係除信號線驅動電路3 .之外，可廣泛地被適用 〇 又，圖2 2等所示之各種開關係可使用轉換閘或類比 開關加以構成。 ' 線· 又，於圖2 2等中，雖說明了將反轉增幅輸入之信號 的反相器，2段縱連續連接，構成邏輯電路1 1 3之例， 但只要是組合電晶體之構成者，於邏輯電路1 1 3之內部 構成中，則無特別之限制。 ~ 經濟部智慧財產局員工消費合作社印製 更且，於上述第1 2實施形態〜第1 6實施形態中， 將信號線S預先設定呈5 V，輸入影像信號V i η較5 V 爲高之時，驅動正極性之負荷驅動電路1 1 1 a ，將信號 線S自5V上昇至輸入影像信號V i η，輸入影ί象it號 V i η較5 V爲低之時，驅動負極性之負荷驅動電路 1 1 1 b，將信號線S自5 V下降至輸入影像信號V i η ，可提升設定於信號線S電壓之正確牲。但是，無需設置 正極性之負荷驅動電路1 1 1 a和負極性之負荷驅動電路 1 1 1 b之兩者。例如將信號線S預先設定呈5 V，僅以 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -78 - 476854 A7 B7 五、發明說明（.76) 正極性之負荷驅動電路，將信號線S上昇至0 V〜1 0 V 之輸入影像信號V i η的電趨亦可。 又，上述第1 2實施形態〜第1 6實施形態中，將圖 2 3之正極性之負荷驅動電路1 1 1 a和負極性之負荷驅 動電路1 1 1 b之任一者，對應輸入影像信蜂> i η之電 壓加以驅動，無關於輸入影像信號V i n之電壓，將雙方 之負荷驅動電路1 1 1 a、1 1 1 b同時加以驅動亦可。 如以上所詳細之說明，根據本發明之時，將邏輯電路 之輸入端子之電壓設定呈略等於邏輯電路之臨限値電壓之 後，將自外部之輸入信號供予驅動負荷之故，對於邏輯電 路之臨限値的參差，供予驅動負荷之電壓則不接受其影響 。因此，將本發明例如適用於液晶顯示裝置之信號驅動電 路之時，可得亮度無斑駁顯示品質優異之驅動電路一體型 之液晶顯示裝置。 【第1 7實施形態】 ' 有關第1 7實施形態之負荷驅動電路係將輸入影像信 號之電壓，和將對信號線之電壓供給開關之電晶體控制的 邏輯電路之臨限値電壓之差分電壓，保持於電容、#之後， 經由於信號線供給電壓地，令邏輯電路之臨限値之參差以 電容器加以吸收者。又，於電晶體和電壓源間，設置定電 流電路地，將於信號線供給電壓時之信號線之電壓變化之 比例呈一定地，確保負荷增幅電路之線性者。更詳細而言 ，說明如下i 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -79 - iln — 1 — ml! · I 1 » (請先閱讀背面之注意事項本頁) 訂· .線· 經濟部智慧財產局員工消費合作社印製 476854 二。 A7 B7 五、發明說明（77) 圖4 7係顯示本發明之第1 7實施形態之負荷驅動電 路之主要部之構成之電路隊。圖4 8係顯示負荷驅動電路 本體之構成的槪略方塊圖。圖4 9係說明正極性用之負荷 驅動電路和正極性用之負荷驅動電路之動作區分圖。 .圖4係信號線驅動電路3，係使用示於· 8之負荷 驅動電路的構成。圖4 8之負荷驅動電路係具有對應各信 號線所設之正極性用之負荷驅動電路2 1 1 a ，和負極性 用之負荷驅動電路2 1 1 b，和切換控制此等負荷驅動電 路2 1 1 a、2 1 1 b內之各種開關之開關切換控制電路 2 1 2 〇 圖4 9係說明正極性用之負荷驅動電路和正極性用之 負荷驅動電路之動作區分圖。如此圖4 9所示，於本實施 形態之中，輸入影像信號V i η係〇 V〜1 〇 V間之信號 ，將此輸入影像信號V i η分爲0V〜5V和5V〜 1 2 V之2個情形，驅動正極性用之負荷驅動電路~ 2 1 1 a ，和負極性用之負荷驅動電路2 1 1 b。 即，負極性用之負荷驅動電路2 1 1 b係將信號線S 預先設定於Ο V，輸入影像信號V i η於〇 V〜5 V時， 將信號線S之電壓上降至輸入影像信號V i η之_翼_壓加以 動作之緩衝電路。正極性用之負荷驅動電路2 1 1 a係預 先將信號線S設定於1 〇 V，於輸入影像信號V i η爲 5 V〜1 〇 V之時，將信號線S之電壓下降至輸入影像信 號V i η之電壓加以動作之緩衝電路。被此等負荷驅動電 路2 1 1 a 、2 1 1 b之任意者驅動，係經由開關切換控 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） · 80 - I I----1-------裝 i — (請先閱讀背面之注意事項本頁) 訂： 經濟部智慧財產局員工消費合作社印製 476854 A7 B7 五、贅明說明（78) 制電路2 1 2加以控制.。 然而，本實施形態中心將切換正極性用之負荷驅動電 路2 1 1 a和負極性用之負荷驅動電路2 1 1 b之驅動的 電壓，設定於具有0〜1 0 V之電壓振幅之輸入影像信號 V i η之中間電壓的5 V，但設定於此中間電’歷以外之電 壓亦可。 圖4 7係正極性用之負荷驅動電路2 1 1 b之電路圖 。各負荷驅動電路2 1 1 b係如圖4 7所示，具有開關 S W 2 0 1〜開關S W 2 0 4，和P Μ 0 S電晶體所成電 晶體Q 2 0 1 ，和前述反相器2 1 4和後段反相器2 1 5 所成邏輯電路2 1 3，和電容器C 2 0 1 ，和定電流電路 I 1 。經由負荷驅動電路2 1 1 a、2 1 1 b驅動之信號 線S中，如圖4所示，連接畫像顯示用之T F T、液晶容 量及補助容量等，圖4 7係簡化之故，令信號線S之負荷 以等價性阻抗R和電容器C 2 0 2。 開關S W 2 0 1、S W 2 0 2之一端係連接於信號線 S，開關SW2 0 1之另一端係連接於開關SW2 0 3之 一端和電容器C 2 0 1之一端，於開關S W 2 0 3之另一 端中，供給輸入影像信號V i η。電容器C 2 0.丄之另一 端係連接於邏輯電路2 1 3之輸入端子，邏輯電路2 1 3 之輸出端子係連接電晶體Q 2 0 1之閘極端子。於電晶體 Q 2 0 1之源極端子電壓V D D (例如1 Ο V )則介由定 電流電路I 1加以施加，於該汲極端子連接開關 SW2 0 2之另一端。於開關SW2 0 4之一端連接信號 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） .81 - !!!·裝 i _ * (請先閱讀背面之注意事項本頁) -Ή. --線- 經濟部智慧財產局員工消費合作社印製 476854 A7 B7 五、發明說明（79) ί請先閱讀背面之注意事項本頁) 線S，於開關S W 2 0. 4之另.一端施加電壓V S S (例如 0 V )。開關S W 2 0 1 > S W 2 0 4係經由圖4 8所示 開關切換控制電路2 1 2切換控制。- 圖4 7中，令開關SW2 0 1和電容器C 2 0 1之連 接點爲a，令電容器C 2 0 1和邏輯電路2 Γ.3之連接點 爲b，令邏輯電路2 1 3和電晶體Q2 0 1之連接點爲c ，令開關SW20 1、SW202之連接點爲d。 然而，電容器C 2 0 1則構成本實施形態之差分電壓 保持電路，電壓V D D之電壓源和定電流電路I 1則構成 將本實施形態之信號線S之電壓以一定之比例變化之電壓 變更電路，開關S W 2 0 3則構成本實施形態之輸入電壓 設定電路。 圖5 0係圖4 7之負荷驅動電路2 1 1 b內之各部定 時圖，以下，使用此定時圖，說明圖4 7之負荷驅動電路 2 1 1 b之動作。 首先，於時刻T 2 1 1〜T 2 1 2之期間（重置期間 )內，開關切換控制電路2 1 2係將開關S W 2 0 1〜 經濟部智慧財產局員工消費合作社印制衣 S W 2 0 3呈關閉，令開關S W 2 0 4呈開啓。由此，信 號線S之電壓（圖4 7之d點）係與電壓V S S秦同樣之 電壓（例如〇 V )。 接著，於時刻T2 1 2〜T2 1 3之期間（電容器之 寫入期間）內，開關切換控制電路2 1 2係僅令開關 SW1 〇 3呈開啓。由此，圖4 7之a點之電壓係等於輸 入影像信號V i η之電壓。圖5 0中，輸入影像信號 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） -82 · 476854 A7 _ B7 五、發明說明（ BO) V i η之電壓係顯示3 V之例。惟開關S W 2 0 1呈關閉 之故，信號線S (圖4 7之點）之電壓係維持於〇ν。 裝 訂 在此’將前段反相器2 1 4之臨限値電壓假定呈5 V 時，經由某種手段，將前段反相器2 1 4之輸入端子、（圖 4 7之b點）之電壓，設定於前段反相器2 1. 4之臨限値 電壓。將此圖4 7之b點設定於前段反相器2 1 4之臨限 値電壓的手法係以後述之其他實施形態加以說明。將前段 反相器2 1 4之輸入端子設定於臨限値電壓時，邏輯電路 2 1 3之輸出端子（圖4 7之c點）之電壓係幾近呈等於 電源電壓的1 0 V。因此，此期間內係電晶體Q 2 0 1係 呈關閉。此時，開關S W 2 0 3呈開啓之故，圖4 7.之a 點之電壓係呈輸入影像信號V i η之電壓的3 V。爲此， 於電容器C 2 0 1 ，保持輸入影像信號V i η之電壓（例 如3 V )和前段反相器2 1 4之臨限値（例如5 V )之差 分電壓（例如2 V ) 。 ^ 接著，時刻Τ 2 1 3之後（寫入期間、安定期間）， 開關切換控制電路2 1 2係令開關S W 2 0 1、 經濟部智慧財產局員工消費合作社印製 SW202呈開啓，開關SW203、SW204呈關閉 。於時刻Τ 2 1 3之時點，圖4 7之a點係對31而言， d點係0V之故，開關SW2 0 1呈開啓時，a點之電壓 被d點所連續而下降。電容器C 2 0 1係維持上述差分電 壓（2V)之故，此電容器C 2 01之另一端之圖4 7之 b點之電壓亦追隨a點之電壓下降’邏輯電路2 1 3之輸 出則反轉，呈低準位（例如0 V )。由此，電晶體 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -83- 476854 A7 __B7___ 五、發明說明（81 ) !!·裝 i I (請先閱讀脅面之注意事項本頁) Q 2 Ο 1呈開啓，一定電流自定電流電路I 1介由電晶體 Q 2 Ο 1和開關S W 2 0 2“，供予信號線S，信號線S ( 圖4 7之d點）之電壓則以一定之斜率上昇。 當信號線S之電壓以一定之斜率上昇時，對應於此圖 4 7之a點、b點之電壓亦以一定之斜率上昇、、然後，呈 時刻T 2 1 4，信號線S之電壓等於輸入影像信號V i η 之電壓的3 V，圖4 7之a點之電壓亦等於3 V。電容器 C 2 0 1係保持上述差分電壓（2 V )之故，圖4 7之b 點之電壓係呈前段反相器2 1 4的5 V。爲此，邏輯電路 2 1 3之輸出則再反轉呈高準位（例如1 Ο V )。由此， 電晶體Q 2 Ο 1則呈關閉，自定電流電路I 1向信號線8 之電流供給，即電壓之供給被切斷。經由此動作，信號線 S係設定呈略等於輸入影像信號V i η之電壓。 --線· 經濟部智慧財產局員工消費合作社印製 圖5 1係顯示正極性用之負荷驅動電路2 1 1 a之詳 細構成的電路圖。如圖5 1所示，正極性用之負驅動電 路2 1 1 a係電晶體Q 2 Ο 1爲η型，和定電流電路I 1 爲連接於電壓V S S之點，與圖4 7之負極性用之負荷驅 動電路2 1 1 b不同。誌點以外，與上述負極性用之負荷 驅動電路2 1 1 b同樣之故，省略其詳細說明。—一 如以上所述，根據有關本發明第1 7實施形態之負荷 驅動電路2 1 1 b時，於電容器C 2 Ο 1保持差分電壓之 狀態，以開關S W 2 Ο 1、S W 2 Ο ·2和邏輯電路2 1 3 和電晶體Q 2 Ο 1構成回歸迴圈之故，將信號線S之電壓 預先設定於OV之後，將電壓VDD介由電晶體Q20 1 •84- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 476854 A7 —.^ B7 五、發明說明（ 82) ’供予信號線S，信號線S之電壓則略等於輸入影像信號 v i η之電壓的時點，將雪晶體q 2 0 1呈關閉。將電壓 V D D之供給切斷之故，令信號線S之設定呈略等於輸入 影像信號V i η之電壓。 又，將前段反相器2 1 4之臨限値電壓和.輸入影像信 號V i η之電壓之差分電壓保持於電容器C 2 0 1之後， 於信號線S供給輸入影像信號V i η之故，於前段反相器 2 1 4之臨限値電壓有參差之時，信號線S之電壓則不受 該影響。 更且，根據有關本實施形態之負荷驅動電路2 1 1 b 時，於信號線S供給電壓V D D之時，介由定電流電路 I 1加以供給之故，無關輸入影像信號V i η之電壓或信 號線S之電壓，以一定斜率變化，可使信號線S之電壓拉 起。即，無設置定電流電路I 1之時，隨著信號線S之電 - --. -嫌— 壓接近電壓VDD，電晶體Q2 0 1之關啓阻抗會增大， 而產生信號線S之電壓上昇之傾斜變小的現象。即，經由 設定於信號線S之電壓，信號線S之電壓上昇之傾斜會有 所變化。' 又，邏輯電路2 1 3係具有電路延遲之故，良邏輯電 路2 1 3之輸入端子（圖4 7之b點鐘之電壓到達臨限値 ，至電晶體Q 2 0 1實際關閉時需要一定之時間。爲此’ 嚴密地思考之後，設定於信號線S之電壓係較輸入影像信 號Vin之電壓略高。 因此，信號線S之電壓上昇之傾斜變化時，實際上設 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）~ - 85 - ： — 1!·裝 i I 4 (請先閱讀背面之注意事項本頁) 訂： --線· 經濟部智慧財產局員工消費合作社印制农 476854 A7 — B7 五、發明說明（83 ) 定於信號線S之電壓和輸入影像信號V i η之電壓的誤差 係經由設定於信號線S之電壓之高度，會產生參差不齊的 現象。即，負荷驅動電路2 1 1 a之線性會惡化。如此地 ，於設定於信號線S之電壓，和輸入影像信號V i η之電 壓的誤差上，產生參差之時，會有產生寫入錯_之虞。 對此，於有關本實施形態之負荷驅動電路2 1 1 b中 ，無關於信號線S之電壓，將信號線S之電壓上昇之斜率 d t呈一定之故，實際上設定於信號線S之電壓和輸入影 像信號V i η之電壓的誤差則可呈一定者。爲此，可確保 負荷驅動電路2 1 1 a之線性，而不會產生所謂之寫入錯 誤。 又，根據有關本實施形態之負荷驅動電路2 1 1 b時 ’將欲保持電容器C 2 0 1之差分電壓，設定於電容器 C 2 0 1之時，將前段反相器2 1 4之臨限値電壓和輸入 影像信號V i n之電壓，於同一周期加以取樣之&，較將 此等2個電壓之設定以各別之周期進行之時，可設定正確 之差分電壓。 【第1 8實施形態】 _一 本發明之第1 8實施形態係將上充述第1 7實施形態 之前段反相器2 1 4之輸入端子側之電壓（圖4 7之點b )’明白設定於段反相器2 1 4之臨限値電壓的具體.手法 者。 圖5 2係有關本實施形態負極性用之負荷驅動電路 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -86 - — 11-裝 i I 禮 <請先《讀背面之注意事項本頁) 訂： i線- 經濟部智慧財產局員工消費合作社印製 476854 A7 B7 五、發明說明（β4) 2Γ1b之電路圖。有關本實施形態負荷驅動電路 2 1 1 b係上述圖47所示，於負荷驅動電路2 1 1 b係 加上開關S W 2 0 5〜開關S W 2 0 8加以構成。 開關SW 2 0 6之一端係連接電容器C 2 〇 1之一端 ，開關S W 2 0 6之另一端係連接於電壓VD D:(例如 10)。開關SW205之一端係連接於前段反相器 2 1 4之輸入端子，開關SW2 0 5之另一端係連接於前 段反相器2 1 4之輸出端子。開關S W 2 〇 7之一端係連 接於前段反相器2 1 4之輸出端子，開關SW2 0 7之另 一端係連接於後段反相器2 1 5之輸入端子，開關 S W 2 0 8之一端係連接於後段反相器2 1 5之輸入端子 ，開關S W 2 0 8之另一端係連接於電壓V S S (例如 〇 λ，）。 開關S W 2 0 5〜S W 2 0 8亦經由圖4 8所示之開 - -- 一一 關切換控制電路2 1 2加以切換控制。 圖5 2中，令開關SW2 01和電容器C 20 1之連 接點爲a ，令電容器C 2 0 1和邏輯電路2 1 3之連接點 爲b，令邏輯電路2 1 3和電晶體Q 2 0 1之連接點爲c ，令開關S W 2 0 1、S W 2 0 2之連接點爲d 然而，電容器C 2 0 1則構成本實施形態之差分電壓 保持電路，電壓V D D之電壓源和定電流電路I 1則構成 將本實施形態之信號線S之電壓以一定之比例變化之電壓 變更電路，開關S W 2 0 3則構成本實施形態之輸入電壓 設定電路，開關S W 2 0 5之回歸迴圈構成本實施形態之 — 1!!!裝 i 1 « Γ4先閱讀背面之注意事項^^^本頁> 訂* ;線· 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -87· 476854 A7 _ B7 五、發明說明（85 ) 臨限値電壓設定電路、 {請先閱讀背面之注意事項本頁) 圖5 3係圖5 2之負荷-驅動電路2 lib內之各部定 時圖’以下，使用此定時圖，說明圖5 2之負荷驅動電路 2 1 1 b之動作。 •首先，於時刻T 2 2 1〜T 2 2 2之期間，··(重置期間 )內’開關切換控制電路2 1 2係將開關SW2 04、 SW206、SW208呈開啓，令開關SW201〜 S W 2 0 3、S W 2 0 5、S W 2 0 7 呈關閉。由此，信 號線S之電壓（圖5 2之d點）係與電壓V S S呈同樣之 電壓（例如〇 V )。又，前段反相器2 1 4之輸入端子之 電壓係呈與電壓V D D同樣之電壓（例如1 〇 V )，後段 反相器2 1 5之輸入端子之電壓係與電壓V S S呈同樣之 電壓（例如0 V )。在此，將前段反相器2 1 4之輸入端 子之電壓呈電壓VDD，後段反相器2 1 5之輸入端子之 電壓呈電壓V S S，係於構成前段反相器2 1 4或後段反 經濟部智慧財產局員工消費合作社印制衣 相器2 1 5之C Μ〇S電晶體，不流入貫穿電流之故。即 ，經由將構成C Μ 0 S電晶體之Ρ型Μ 0 S電晶體和η型 Μ〇S電晶體中之一方的Μ 0 S電晶體充分呈關閉之狀態 ，使貫穿電流不流入。由此，可達成此負荷驅動電篇 2 1 1 b之電力消耗之減低。因此’施加於前段反相器 214之輸入端子和後段反相器215之輸入端子的電壓 ，係電壓V D D (例如1 0 V )和電壓V S S (例如〇 V )之任一者皆可。 接著，於時刻T 2 2 2〜T 2 2 3之期間（電容器之 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -88- • . 、.. ： 、.·——. ·· * . ...- *. *— A7 ______ B7 _______ 五、發明說明（86) 寫入期間）內，開關切換控制電路2 1 2係僅令開關 S W 2 0 3、S W 2 0 5 呈開啓-，令開關 S W 2 0 1、 SW202、S 204 SW0 6 〜SW 208 呈關閉。由 此，圖5 2之a點之電壓係等於輸入影像信號V in之電. 壓。圖5 3中，輸入影像信號V i η之電壓係顯苹3 V之 例。惟開關S W 2 0 1呈關閉之故，信號線S (圖4 7之 d點）之電壓係維持於Ο V。 又，開關S W 2 0 5爲開啓之故，圖5 2之b點之電 壓係設定呈略等於前段反相器2 1 4之臨限値電壓（在此 呈5 V )。即，經由將前段反相器2 1 4之輸出向輸入反 饋，前段反相器2 1 4之輸入端子及輸出端子之電壓係設 定呈略等於前段反相器2 1 4之臨限値電壓的電壓。因此 ，於電容器C20 1 ，保持輸入影像信號V i η之電壓（ 例如3 V )和前段反相器2 1 4之臨限値（例如5 V )之 差分電壓（例如2 V )。 一 接著’時刻Τ 2 2 3之後（寫入期間、安定期間）， 開關切換控制電路2 1 2係令開關S W 2 0 1、 SW202、SW207呈開啓，開關SW203〜 SW206、SW208呈關閉。於時刻Τ223之腾點 ，圖5 2之a點係對3 V而言，d點係呈〇 V。爲此，開 關S W 2 0 1呈開啓時，a點之電壓被d點所連續而下降 。電容器C 2 0 1係維持上述差分電壓（2V)之故，此 電谷isC 2 0 1之另一端之圖5 2之b點之電壓亦追隨a 點之電壓下降，邏輯電路2 1 3之輸出則反轉，呈低準位 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱)Tg9 ·~ (請先閱讀背面之注意事項再填寫本頁) •線. tL· A7 B7 五、發明說明（87 ) (例如Ο V )。由此，，電晶體q 2 〇 1呈開啓，一定電流 自定電流電路I 1介由電晶體Q2 0 1和開關SW2 0 2 ，供予信號線S，信號線s (圖5 2之d點）之電壓則以 一定之斜率d t上昇。 .當信號線S之電壓以一定之斜率d t上昇.食·，對應於 此圖5 2之a點、b點之電壓亦以一定之斜率d t上昇。 然後，呈時刻T224，信號線S之電壓等於輸入影像信 號V i η之電壓的3 V，圖5 2之a點之電壓亦等於3 V 。電容器C 2 0 1係保持上述差分電壓（2 V )之故，僵 5 2之b點之電壓係呈前段反相器2 1 4的5V。爲此， 邏輯電路2 1 3之輸出則再反轉呈高準位（例如1 〇 V ) 。由此，電晶體Q 2 0 1則呈關閉，自定電流電路I 1向 信號線S之電流供給，即電壓之供給被切斷。經由此動作 ，信號線S係設定呈略等於輸入影像信號V i η之電壓的 -* - r 3 V 〇 經濟部智慧財產局員工消費合作社印製 -----I - -------裝 i — • . (請先閱讀背面之注意事項本頁) --線. 圖5 4係顯示正極性用之負荷驅動電路2 1 1 a之詳 細構成的電路圖。如圖5 4所示，正極性用之負荷驅動電 路2 1 1 a係電晶體Q 2 0 1爲η型，和定電流電路I 1 爲連接於電壓VSS之點，與圖5 2之負極性用之·負荷驅 動電路2 1 l b不同。此點以外，與上述負極性用之負荷 驅動電路211b同樣之故，省略其詳細說明。 如以上所述，榭據有關本發明第1 8實施形態之負荷 驅動電路2 1 1 b時，，與上述第1 7實施形態伺樣地， 令信號線S之設定呈略等於輸入影像信號V i η之電壓。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） .9〇 . B7 五、發明說明（ 88) ---------------裝·1· 鑤 (請先閱讀背面之注意事項本頁) 又，將前段反相器2 1 4之臨限値電壓和輸入影像信 號V i n之電壓之差分電壓保持於電容器c 2 0 1之後， 於信號線S供給輸入影像信號V i η-之故，於前段反相器 2 1 4之臨限値電壓有參差之時，信號線S之電壓則不受 該影響。 · 乂· 更且，根據有關本實施形態之負荷驅動電路2 1 1 b 時，於信號線S供給電壓V D D之時，介由定電流電路 I 1加以供給之故，無關輸入影像價號V i η之電壓或信 號線S之電壓，以一定斜率d t變化，可使信號線S之電 壓拉起。爲此，負荷驅動電路2 1 1 a之線性可被確保， 即，不會產生所謂之寫入錯誤。 線· 又，根據有關本實施形態之負荷驅動電路2 1 1 b時 ，將欲保持電容器C 2 0 1之差分電壓，設定於電容器 C 2 〇 1之時，將前段反相器2 1 4之臨限値電壓和輸入 影像信號V i η之電壓，於同一周期加以取樣之^，較將 此等2個電壓之設定以各別之周期進行之時，可設定正確 之差分電壓。 經濟部智慧財產局員工消費合作社印製 然而，本發明係非限定於上述第1 7實施形態及第 1 8實施形態可進行種種之改變。例如，於上述_赛1 7實 施形態及第1 8實施形態中，說明將有.關本發明之負荷驅 動電路適用於液晶顯示裝置內之信號線驅動電路3之例者 ，但本發明係除信號線驅動電路3之外，亦可廣泛地被適 用。 又，上述第1 7實施形態及第1 8實施形態所示各種 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -91 - 476854 A7 ______B7_____ 五、發明說明（89) ----------------裝— (請先閱讀背面之注意事項本頁) 開關係可使用轉換閘或類比開關加以構成。又，上述實施 形態中，雖說明了將反轉壏幅輸入之信號的反相器，2段 縱連續連接，構成邏輯電路2 1 3之例，但只要是組合電 晶體之構成者，於邏輯電路2 1 3之內部構成中，則無特 別之限制。 /二· 線· 更且，於上述第1 7實施形態及第1 8實施形態中， 輸入影像信號V i η較5 V爲高之時，驅動正極性用之負 荷驅動電路2 1 1 a ，將信號線8自1〇又上昇至輸入影 像信號V i η，輸入影像信號V i η較5 V爲低之時，驅 動負極性之負荷驅動電路1 1 1 b，將信號線S自Ο V下 降至輸入影像信號V' i η，可提升設定於信號線S電壓之 正確性。但是，無需設置正極性之負荷驅動電路1 1 1 a 和負極性之負荷驅動電路1 1 1 b之兩者。例如將信號線 S預先設定呈0 V，僅以正極性之負荷驅動電路，將信號 線S上昇至〇 V〜1 〇 V之輸入影像信號V i η 電壓亦 可〇 經濟部智慧財產局員工消費合作社印製 又/上述第1 7實施形態及第1 8實施形態中，將圖 4 8之正極性之負荷驅動電路2 1 1 a和負極性之負荷驅 動電路2 1 1 b之任一者，對應輸入影像信號V η之電 壓加以驅動，無關於輸入影像信號V i η之電壓，將雙方 之負荷驅動電路2 1 1 a、2 1 1 b同時加以驅動亦可。 如以上所詳細之說明，根據本發明之時，將構成輸入 信號之電壓和邏輯電路之前段反轉增幅電路之臨限値的差 分電壓，保持於差分電壓保持電路之後，以電壓變更電路 -92- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 4 5 8 6 7 A7 _______B7 ___ 五、發明說明（90) 將信號線之電壓以一定比例變化之故，對於邏輯電路之臨 限値有參差時，可將信號線-之電壓設定略等於輸入信號之 電壓。又輸入信號之電壓和實際設定信號線之電壓的誤差 爲一定，而提升線性。因此，將本發明例如適用於液晶顯 示裝置之信號驅動電路之時，可得亮度無斑駁顯示品質優 異之驅動電路一體型之液晶顯示裝置。 ---------------裝 i — 0 (請先閱讀背面之注意事項本頁) -•線- 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -93-Figure 2 4 is a diagram illustrating the functional distinction between the load driving circuit 1.1 1 a for positive polarity and the load driving circuit 1 1 1 b for negative polarity. As shown in FIG. 24, in this embodiment, the input video signal Vi η is a signal between 0 V and 10 V, and this is divided into input video signals V i η between 0 V and 5 V and 5 V and 10. In two cases, a load driving circuit for driving a positive polarity • A driving circuit 1 1 1 a and a load driving circuit for a negative polarity Γ 1 1 b. That is, the load driving circuit for negative polarity 1 1 1 b sets the signal line S to 5 V in advance, and decreases the voltage of the signal line S to the input image when the input image signal V i η is 0 V to 5 V. A buffer circuit that operates on the voltage of the signal V i η. The load driving circuit for positive polarity 1 1 1 a is to set the signal line S to 5 V in advance, and when the input video signal V i η is 5 V to 10 V, the voltage of the signal line S is increased to the input video signal. A buffer circuit that operates with a voltage of V i η. It is driven by any of these load driving circuits 1 1 1 a, 1 1 1 b, and is controlled by the switch control circuit 1 1.2. However, in this embodiment, the voltage set in advance on the signal line S is set to 5 V of the intermediate voltage of the input image signal V i η having a voltage amplitude of 0 to 10 V, but it is set to a value other than this intermediate voltage. Voltage is also available. Figure 2 Circuit diagram of 2 1 load circuit for positive polarity 11 1 a This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) -50------------- --Install iJ 0 < Please read the notes on the back page first) Order · i-line · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 476854 A7 B7 V. Description of the Invention (48) il — 丨! !! — I · install i I (please read the caution page on the back first). The load driving circuit 1 i i a for each positive polarity is shown in FIG. 22, and includes switches SW1 to 104, and? 1 ^ 〇8 transistor crystal transistor Q 1 〇i, and the inverter in a two-segment vertical continuous logic circuit 1 1 3, and capacitor C 1 〇 1. In the signal line S driven by the load driving circuit 1 1 1 a and 1 i 1 b for positive polarity, as shown in FIG. 4, the connection to the image display device f T, the liquid crystal capacity, and the auxiliary capacity are shown in FIG. 2 2 series. For simplicity, let the load of the signal line S be the equivalent impedance R and the capacitor C102. … One end of the switch SW 1 〇1, Sw 1 〇2 is connected to the signal line-.-.- .... s' The other end of the switch SW 1 〇1 is connected to one end of the switch s W 103 One end of the capacitor C 1 〇1 supplies an input video signal V i η to the other end of the switch s W 103. The other end of the capacitor C 1 0 1 is connected to the input terminal of the logic circuit 1 1 3, and the logic circuit 1 1 3. The line. The output terminal of the printed clothing of the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economy is connected to the transistor Q 1 〇1 Gate terminal. A first voltage V D D (eg, α 10 V) is applied to the source terminal of the transistor Q 1 0 1, and the other terminal of the switch S W 1 0 2 is connected to the drain terminal. A signal line S is connected to one end of the switch SW104, and a second voltage V D (for example, 5 V) is applied to the other end of the switch SW104. The switches S W 1 〇 1 -J. To S W 1 〇 .4 are controlled by the switch 1 12 through the switch control shown in FIG. 23. In FIG. 22, let the connection point of the switch SW1 0 1 and the capacitor C 1 0 1 be a, let the connection point of the capacitor C 1 〇1 and the logic circuit 11 3 be b, and let the logic circuit 1 1 3 and the transistor Q 1 The connection point of 〇1 is c, and the connection point of switches SW104 and SW102 is d. This paper size applies the Chinese National Standard (CNS) A4 specification (210x 297 mm) · 51 · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (49) However, capacitor C 1. .〇1 The first voltage V JD1D constituting the differential voltage holding circuit '1 of this embodiment constitutes the first voltage supply circuit of this embodiment. I. Fig. 25 is a timing chart of each part in the load driving circuit 11 la of Fig. 22, and this timing chart will be used to explain the operation of the circuit in Fig. 22. First, the switch switching control circuit 1 12 turns off the switches SW1 0 1 to SW1 03 during the period from time T 1 0 1 to T 102, and turns the switch SW 1 0 4 on. Therefore, the voltage of the signal line S (d in FIG. 2 2) is the same voltage (for example, 5 V) as the voltage V D of 苐 2. Then, during the period from time T 1 02 to T 1 03, the switch switching control circuit 1 12 only turns on the switch SW 103. Therefore, the voltage at point a in FIG. 22 is equal to the voltage of the input video signal V i η. In Fig. 25, an example in which the voltage of the input video signal V i η is 7 · 5V is displayed. However, because the switch S W 1 0 1 is turned off, the voltage of the signal line S (points-* · *-d in Figure 2 2) is maintained at 5 V. Here, when the threshold voltage of the output logic of the inversion logic circuit 1 1 3 is assumed to be 5 · 5V, the voltage of the input terminal (point b in FIG. 22) of the logic circuit 113 is set by some means. Threshold voltage at the logic circuit 1 1 3. The method of setting the point b in FIG. 22 to the threshold voltage of the logic circuit 1 1 3 is described in other embodiments described later. When the input terminal of this logic circuit 1 1 3 is set to a threshold voltage, the voltage of the output terminal of logic circuit 1 13 (point c in Fig. 2) is theoretically an intermediate voltage between 0 V and 1 0 V. Around 5 V. However, in reality, the voltage at point b in Figure 2 is 5,5 V, which is higher than the threshold voltage. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) —One-52- (Please Read the precautions on the back page first) Installation ·· Green · A7 B7 V. Description of the invention (print) !! · Install i J (Please read the precautions on the back first) Some or lower, logic circuit at this time The voltages at the output terminals of 1 1 3 (point c in Fig. 22) are each 10 or ￥. In Figure 25, an example of 10 V is shown. However, the period from time T 1 0 1 to time T 1 0 2 is that the switches S 0 1 and SW 1 are turned off. When the output voltage of the logic circuit 1 1 3 is any V, for the time to be described later The output of the input image signal V i η of the signal line S after T 1 〇3 will not have any influence. At this time, because the switch SW 103 is turned on, the voltage at point a in FIG. 22 is 7 · 5 V of the voltage of the input image signal V i η. For this reason, the difference voltage (2 V) between the voltage (7 · 5ν) of the input image signal V i η and the threshold 値 (5 · 5V) of the logic circuit 113 is held in the capacitor C 1 0 1. •• Line. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Then, at time T 1 〇3, the switch switching control circuit 1 1 2 is set to switch SW 1 〇1, s W 1 0 2 is turned on, switch SW103; SW104 Was closed. At time T103, point a in Figure 2 is for 7.5 V and point d is 5 V. When switch SW1 01 is turned on, the voltage at point a is continuously decreased by point d. Capacitor C 1 0 1 maintains the above-mentioned differential voltage (2 V). The voltage at point b of Figure 2 2 on the other end of capacitor C 1 0 1 also follows the voltage drop at point A. The output of logic circuit 1 1 3 It is reversed to a low level (for example, 0 V) ^ Thus, the transistor Q 1 〇1 is turned on, and the first voltage VDD is supplied through the transistor Q 1 〇1 and the switch sw 1 〇2 to supply a signal The voltage of line S and signal line S (point d in Fig. 2) increased slowly. -53- This paper size applies to China National Standard (CNS) A4 specification (210 X 297 meals) 476854 A7 B7 Employees of Intellectual Property Bureau, Ministry of Economy Printed by a consumer cooperative V. Description of the invention (51) 〇 When the voltage of the signal line S goes dark, the voltages corresponding to points a and b in this figure 22 also rise. Then, at time T-104, the voltage of the signal line S is equal to 7.5 V of the voltage of the input video signal V i η, and the voltage at point a in Fig. 2 is also equal to 7.5 V. Capacitor C 1 0 \ 1 maintains the above-mentioned differential voltage (2 V). The voltage at point b in Fig. 2 is a threshold voltage of 5 · 5 V. For this reason, the output of the logic circuit 1 1 3 is inverted to a high level (for example, 10 V). As a result, the transistor Q 1 0 Γ is turned off. When the transistor Q 1 0 1 is turned off, the capacity C 1 〇2 on the signal line S is slowly discharged. In the signal line S, the charge is redistributed. Although the voltage at point d in FIG. 2 drops, the logic circuit The voltage at the input terminal of 1 1 3 (point b in Fig. 2) drops to the threshold voltage of the logic circuit 1 1 3, then the transistor Q 1 0 1 is turned on, and the voltage at point d in Fig. 2 2 Department rises again. This operation is repeated under the condition that the capacitor C 1 maintains the above-mentioned differential voltage (2 V), and the voltage of the signal line S (point d in FIG. 22) is maintained at the voltage of the input image signal V i η 7.5 V. Fig. 26 is a detailed circuit diagram showing the load driving circuit 1 1. B for negative polarity. As shown in FIG. 26, the load driving circuit 1 1 lb series transistor Q 1 0 1 is η-type, and the source electrode of the transistor Q 1 0 1 is grounded, and the load driving circuit 1 1 of FIG. 2 2 1 a is different, the other components are the same. As mentioned above, the 12th embodiment is shown in Figure 22. Capacitors please read 'Notes on the back ^ Item * 1> Binding and thread paper size applicable to China National Standard (CNS) A4 (210 X 297 mm) -54-476854 A7 ___ B7 V. Description of the invention (52) C 1 〇1 keeps the differential voltage and the state to switch SW 10 1, s W 1 0 2 and logic circuit 1 1, 3 and transistor Q 1 0 1 constitutes a return loop. When the voltage of the signal line S is lower than the voltage of the input image signal V i η, the transistor Q 1 〇1 is turned on to control the voltage of the signal line S. When the voltage of the signal line S is slightly equal to the voltage of the input interpretation signal V i η, the transistor Q 1 〇1 is turned off ^ Thus, the voltage of the signal line S is set to be slightly equal to the input image signal V i η That is, in the 12th embodiment, the differential voltage between the threshold voltage of the logic circuit 1 13 and the voltage of the input video signal V i η is held in the capacitor C 1 0 1 and then supplied to the signal line S. The input video signal V i η has a reference to the threshold voltage of the transistor constituting the logic circuit 1 1 3 The time, the voltage of the signal line S is not subject to this effect. [13th embodiment] ~ The logic circuit 1 1 3 shown in Fig. 2 is a combination of a transistor, and the output level of the logic circuit 1 1 3 is based on the threshold of the transistor or the difference in the degree of movement. It may change, and the circuit may not operate normally. Here, in the 13th embodiment shown below, when the differential voltage between the threshold voltage of the logic circuit 1 1 3 and the voltage of the input video signal V i η is set in the capacitor _ C 1 0 1, the point b is set at The threshold voltage setting circuit of the threshold voltage of the logic circuit 1 3 is specifically understood, and it is a feature to offset the variation in the characteristics of the logic circuit 1 13. Figure 2 7 is the circuit diagram of the 13th implementation of the load drive circuit. The sizing scale is applicable to the Chinese National Standard (CNS) A4 specification (21 (^ 297 mm) -55- ': ~ " " • 1IIII1I — — — —! ^ · 1 IC Please read the precautions on the back page of this page) Order ·· Thread-Printed clothing for the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 476854 A7 B7 V. Description of the Invention (53)-!! * < Please read the note on the back page first) As in the 12th embodiment, it is used as the signal line driver circuit 3 of the liquid crystal display device. The load driving circuit of Figure 7 is the same as that of Figure 2 and has switches SW 1 0 1 to SW 1 0 4 and a transistor Q 1 0 1 formed by a P M 0 S transistor and an inverter. 2 The logic circuit 1 1 3 is continuously connected in segments, and the capacitor C 1 0 1. In addition, the load driving circuit of Fig. 27 includes a capacitor C103, switches SW1 to SW107, and PMOS transistors Q102 and Q103. Each end of the capacitors C 1 0 1 and C 1 0 3 and each end of S W 1 0 1 and S W 1 03 are connected to each other. The other end of the capacitor C1 01 is connected to the input terminal of the logic circuit 1 1 3 and one end of the switch SW10 5. The other end of the switch s W r 〇 5 is set to a third voltage (for example, 0 V). The other end of the capacitor C 103 is connected to one end of the switch sW 106, and the other end of the switch SW 106 is applied with a fourth voltage (for example, 10 V). ί Wire · Connect the switch to the output terminal of the logic circuit 1 1 3 ~ One terminal of the printed circuit SW 1 〇7 and the gate terminal of the transistor Q 1 〇1 printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, and the other of the switch SW107 One end is connected to the gate terminals of the transistors Q102 and Q103. One of the source / drain electrodes of the transistor Q 1 〇 2 is connected to the electric valley § & 0 1 〇 1 and the switch SW 105 _, and the other is connected to the cancel terminal C N. One of the source / drain electrodes of the transistor Q 103 is connected between the capacitor C 103 and the switch SW 106, and the other is connected to the inversion cancel terminal C ΝΙΙ. In the cancellation terminal CN, a cancellation voltage that is linearly changed in a certain period from 0 ν to 1 〇 ν is applied. In the reversal cancel terminal CNR, it is applied to a certain period of 1 〇ν -56- This paper size has been used in China National Standard (CNS) A4 specification (210 X 297 male ®) 47 order 854 A7 B7 V. Statement ( 54) Inverse to linear change of 0 v, turn to cancel voltage. In _ 2 7, let the connection point of the switches SH 0 1, SW 1 〇3 and the capacitors C 1 〇1, C 1 〇3 be a, and let the connection point of the capacitor C 1 0 1 and the logic circuit 1 1 3 be b. Let the connection point of the logic circuit 1 1 3 fp transistor Q 1 0 1 be c, let the connection point of the switches SW 1 〇1,. SW1 〇2 be d, and let the connection point of the capacitor C103 and the switch SW106 be e. However, the capacitor C 101 constitutes the differential voltage holding circuit of this embodiment, and the first voltage V D D constitutes the first voltage supply circuit of this embodiment. The switches SW 1 0 5 to SW 1 07, transistors Q102, Q10 3, and capacitor C103 constitute a threshold voltage setting circuit of this embodiment. Fig. 28 is a timing chart of each part in the load driving circuit of Fig. 27 '. The timing chart is used to explain the operation of the circuit of Fig. 27. First, during the period from time T 1 1 1 to T 1 1 2, the switch switching control circuit 1 1 2 only turns on the switch SW 1 04. Therefore, the voltage of the signal line S is the same voltage as the second voltage V D (for example, 5 V). 'Next, within the period from time T 1 1 2 to D 1 1 3 ^^ The switch switching control circuit 1 1 2 turns off the switches SW 1 0 1, SW 1 〇2, SW104, and SW107, and switches SW103 and SW105 , SW106 is on. Therefore, the voltage at point a in FIG. 27 is equal to the voltage of the input video signal V i η. Fig. 2 shows an example where the voltage of the input video signal V i η is 7 · 5 V. The paper size of this paper applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -57 · • I 丨 —!! I i »{Please read the precautions on the back page first) 16-i line · economy Printed by the Consumer Cooperatives of the Ministry of Intellectual Property Bureau 476854 A7 B7 V. Description of the invention (55) s W 1 0 1 is closed, the voltage of the signal line s (point d in Fig. 27) is maintained at 5 V ·. In addition, the openings Sw 1 〇5 and swi 〇6 are open. The connection point between capacitor C 1 〇1 and switch sw 1 〇5 (point b in Fig. 27) is OV, and the capacitor c 1 〇3 The connection point (point e in Fig. 27) with the switch SW 10 is 1 Ov. Because the switch SW107 is closed, the transistors qi02 and Q103 are both closed. Next, during the period from time 1 1 3 to time 1 15, the switch switching control circuit 1 1 2 only turns on the switch sw 1 0 7. During the period from time T 1 1 3 to time T 1 1 5, the cancellation terminal c N changes linearly from 0 V to 10 volts, and the reverse cancellation terminal c NR changes linearly from 10 volts to 0 volts. . However, the voltage setting of the c N terminal and the C N R terminal is performed by switching the control circuit 1 12 or other circuit blocks. At the time point τ 1 1 3, the logic circuit 1 13 is at a low level. The transistors Q 1 〇2, Q 1 〇3 are all turned on, and the capacitor C 1 0 1 and the switch SW 1 〇 5 The voltage at the connection point (point b in Fig. 2) is gradually increased, and the voltage at the connection point (point e in Fig. 2 · 7) between the capacitor C1 〇3 and the switch SW1 〇6 is gradually decreased. At time τ 1 1 4, the voltage at point b in Fig. 2 exceeds the threshold voltage of logic circuit 1 1 3 (for example, 5 · 5 V), and the output of logic circuit 1 1 3 is at a high level ( (Approximately 10 volts), the transistors Q 1 0 1 and the transistors Q 1 0 2 and Q 1 0 3 are both turned off. For this reason, the paper size of the logical electronic paper presented at point b in FIG. 27 during the time between ΤΙ 1 4 and ΤΙ 1 5 applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -58-> — — — — — 1 丨 — — — — I * II (Please read the note on the back page first) Words · i-line. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 476854 A7 B7 V. Description of Invention (56) Road The threshold voltage of 1 1 3 (for example, 5 · 5 V), the voltage at point e in Figure 27 is a predetermined voltage (for example, 4 "· 5 V). That is, the input voltage of logic circuit 1 1 3 is more than that of logic circuit. Threshold of 1 1 3 When the voltage is high, the transistor q 1 〇2, Q 1 0 3 are closed, the voltage of the input terminal of the logic circuit 1 1 3 (Figure 2 7 / point b), then It is equal to the threshold voltage of the logic circuit 1 ^ 3. At this time, the point a in Fig. 2 is set to 7 · 5 V of the voltage of the input image signal V i η, and the input is held in the capacitor c 1 〇 The difference voltage (2 V) between the voltage (7 · 5 V) of the signal V i η and the threshold voltage (5 · 5 V) of the logic circuit 1 1 3. Then, the time T 1 1 5 The switch switching control circuit 1 1 2 turns on the switches SW 1 〇1, SW 1 〇2, and turns off the switches SW1 〇3 ~ SW1 07. At the time D1 1 5, the voltage of the signal line S is 5 V, the voltage at point a in Fig. 2 is 7.5 V. Due to the voltage of the signal line S, the voltage at point a in Fig. 7 decreases. The capacitor C 1 〇1 maintains the above-mentioned differential voltage ( 2V), following the voltage drop at point a in Figure 27, the voltage of the _ input terminal (point b in Figure 27) of the logic circuit 1 1 3 is reduced. The voltage at point b in Figure 27 is always a logic circuit The threshold of 1 1 3 is lower than the voltage, and the output of the logic circuit 1 1 3 is at a low level (about 0 V). Therefore, the transistor Q 1 0 1 is turned on, and the signal line S (Figure 2 7 d The voltage at point) rises, corresponding to this, the voltage at points a, b, and e in Figure 27 also rises. The capacitor C 1 〇1 between these successive operations maintains a differential voltage (2 V). Paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -59 · ί --- I ------ ^ .1 — 9 (Please read the precautions on the back page first)-- -Line-Ministry of Economy Printed by the Intellectual Property Cooperative's Consumer Cooperative 476854 A7 B7 V. Description of Invention (57) illlllllllllj ^ · 11 (Please read the precautions on the back ^ This page > Then, at time T 1 1 6, the signal lines s and a The voltage at the point is equal to 7 · 5 V of the dew pressure of the input image signal V in. In this quotient, the capacitor C 1 〇 1 keeps the above-mentioned differential voltage (.2 V). The voltage at the input terminal (point b in Figure 27) of the logic circuit 1 13 is a threshold voltage of 5 · 5 V. For this reason, the output and terminals of the logic circuit 113 are at a high level (about 10 volts). As a result, the transistor Q 100 is turned off. The voltage of the signal line S (point d in Fig. 27) gradually decreases through the discharge of the capacity C 1 〇2. When it drops to a certain level, the transistor q 1 〇1 is turned on again, and the voltage of the signal line S is again rise. In this way, the capacitor C 1 〇1 repeats the above operation while maintaining the divided voltage (2 V), and the voltage of the signal line S (point d in FIG. 27) is maintained at the input image signal V i η voltage (7.5 V) 〇 Line-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. However, the circuit diagram of the load driving circuit 1 1 1 b for negative polarity is shown in FIG. The load driving circuit 1 1 1 b is a buffer circuit that drives the signal line S in the range of 0 V to 5 V. To this end, the transistor Q 1 0 1 is an n-type MOS transistor. The source terminal is Connected to ground, transistors Q1 0 2 and Q 1 0 3 are also replaced with N-type MOS transistors. The switch S W 105 is connected to a voltage terminal # of 10 V, and the switch S W 105 is connected to a voltage terminal of 0 V. The source terminal of the transistor Q 1 0 2 is connected to the inversion cancel terminal C N R, and the drain terminal of the transistor Q 1 0 3 is connected to the cancel terminal C NR. Except for this, the configuration and operation are the same as those of the load driving circuit 1 1 1 a for positive polarity described above, and the detailed description is omitted here. This paper size applies to Chinese National Standard (CNS) A4 specifications (210 X 297 meals) -60- 476854 A7 B7 V. Description of the invention (58) As mentioned above, the circuit of Figure 2.7 is set in the opposite direction to each other Charge and discharge two capacitors C 1- 0 1, C 1 0 3 'at the input terminals of the logic circuit 1 1 3 (point b in Figure 2 7). At the threshold voltage, the transistor Q 1 0 2 For the reason that Q 1 0 3 is closed, the point b in FIG. 2 can be set to the threshold voltage v of the logic circuit 1 1 3 for this purpose. When the threshold voltage of the logic circuit 1 1 3 is staggered, These capacitors C101 hold a differential voltage between the threshold voltage of the logic circuit 113 and the voltage of the input video signal V i η. -For this reason, after the time T 1 1 5 in FIG. 2, when the voltage of the signal line S is higher than the voltage of the input image signal V i η, the transistor Q 1 0 1 is turned off and the signal line S is pulled down. Voltage, when the voltage of the signal line S is lower than the voltage of the input image signal V i η, the transistor Q 1 0 1 is turned on, the control of pulling up the voltage of the signal line S is set, and the voltage of the signal line S is set to Slightly equal to the voltage of the input image signal V i η. However, the transistors Q 1 0 2 and Q 1 0 3 of this embodiment may be configured by the switching gate T G. Figure 3 0 is the transistor Q 1 0 2. The employee ’s consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed 5 clothes (please read the precautions on the back page first) Q 1 0 3 is replaced with a load driver for the positive polarity of the switching gate TG The circuit diagram of the circuit 1 1 1 a, Fig. 31 is a circuit diagram in which the transistor Q1 0 2 and Q 1 0 3 are replaced by the load driving slave circuit 1 1 b for the negative polarity of the switching gate TG. As shown in FIG. 31 and FIG. 3, the switching gate TG is composed of a P-type MOS transistor Q131 and an N-type MOS transistor Q1 3 2 so that the gate terminal of the P-type MOS transistor Q1 3 1 The inverter is connected to the switch SW1 through the inverter IV. The paper size is also applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) -61-476854 A7 B7 V. Description of the invention (59) [第14th embodiment] ^ ill —! — · Install i I (please read the precautions on the back page first). The 14th Bao Shi pattern is to simplify the circuit of the first 3 guest: Shi pattern (Figure 27). Fig. 3 is a circuit diagram of the fourteenth embodiment of the load driving circuit, similar to the twelfth embodiment and the thirteenth embodiment, for example, as the signal line driving circuit 3 of the liquid crystal display device shown in Fig. 4 user. The circuit in FIG. 3 is a feature in which the transistors Q 1 0 2 and Q 1 0 3 are replaced in place of the transistor Q 1 0 2 in the circuit in FIG. 27. One of the source / drain electrodes of the transistor Q 1 0 4 is connected between the capacitor C 1 0 1 and the switch SW 1 0 05, and the other is connected between the capacitor C 1 0 3 and the switch SW 1 0 5 between. The gate terminal of the transistor Q 1 0 4 is connected to one terminal of the switch SW 1 0 7. In FIG. 32, let the connection points of the switches SW101 and SW103 and the capacitors C101 and C103 be a, let the connection point of the capacitor C101 and the logic circuit 1 1 3 be b, and let the connection point of the logic circuit 1 1 3 and the transistor Q10 1 be c. Let the connection point of switch SW101 and SW102 printed by the Intellectual Property Bureau of the Ministry of Economic Affairs' consumer cooperative be d, and the connection point of capacitor C103 and switch SW 106 be e. ^ However, the capacitor C 101 constitutes the differential voltage holding circuit of this embodiment, and the first voltage VDD constitutes the first voltage supply circuit of this embodiment. The switches SW 1 〇5 ~ SW Γ 〇7 and the transistor Q 104 and the capacitor C 103 constitute a threshold voltage setting circuit of this embodiment. This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) -62- 476854 A7 B7 V. Statement (β〇) ~ Figure 3 3 is the β timing diagram of each part in the load drive circuit of Figure 32 In the following, using this timing chart, the circuit operation of Fig. 42 will be described. First, during the period from time T 1 2 1 to T 1 2.2, the switch switching control circuit 1 1 2 only turns on the switch SW 1 04. Therefore, the voltage of the signal line S is the same voltage as the second voltage VD (for example, 5 V). Then, during the period from time T 1 2 2 to T 1 2 3, the switch control circuit 1 1 2 The switches SW 1 〇1 ·, s W 1 〇2, SW 1 〇4, and SW 107 are turned off, and the switches SW 1 〇3, SW105, and SW106 are turned on. Therefore, the voltage at point a in FIG. 32 is the voltage (for example, 7 · 5 V) of the input video signal V i η. During this period, because the switch SW101 is turned off, the voltage of the signal line S (point d in FIG. 32) is maintained at 5V. In addition, the switches SW1 05 and SW1 06 are turned on. Point b in FIG. 3 is 0 V, and point e-1-is 10 V. The switch SW 7 is turned off, and the transistor Q 104 is turned off. 'Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. During the period from time τ 1 2 3 to time τ 1 2 5, the switch switching control circuit 1 1 2 only turns on the switch SW 1 0 7. At this time, the transistor Q 1 0 4 is in an on state, and the points &e; and e in FIG. 3 are short-circuited, and the two voltages change in the same direction. Specifically, the voltage at point b gradually increases from 0 V, and the voltage at point e gradually decreases from 10 V. At time T1 24, the voltage of the input terminal (point b in Figure 3 2) of the logic circuit 1 1 3 exceeds the threshold voltage of the logic circuit 1 1 3, and the output voltage of the logic circuit 1 1 3 is high. Level (for example, this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 public love) -63-476854-^: A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Description (61) 1 Ο V). As a result, the transistor Q 103 is turned off, and the voltage at point 1) does not rise above this value. Therefore, the voltage at the input terminal (point b in Figure 32) of the exposed circuit 1 13 is equal to the threshold voltage of the logic circuit 1 1 3. At this time, the point a in FIG. 3 is maintained at 7 · 5V of the voltage of the input image signal V i η. In the capacitor C101, the input voltage (7 · 5 V) and the threshold of the logic circuit 1 1 3 are held. Voltage (5 · 5 V) Differential voltage (2 V) 〇 Then, at time T 1 25, the switch switching control circuit 1 1 2 turns on the switches SW 1 〇1, SW 1 〇2 and turns on the switch SW 1 〇3 ～ SW 1 07 are closed. As a result, the voltages at points d and a in FIG. 3 decrease, and the capacitor C 1 01 maintains a differential voltage (2 V), so the voltage at point b also follows the decrease. For this reason, the output of the logic circuit 1 1 3 is at a low level (about 0 V), the transistor Q 1 0 1 is turned on, and the voltage of the signal line S is gradually increased. Then, following the rise of the voltage of the signal line S, the voltage of the point b also rises. At time ΐ 1 2 6, the voltage at the point b exceeds the threshold voltage of the logic circuit 1 1 3 and the logic circuit 1 is inverted. The output of 1 3 is at a high level (for example, 1 0 V). Therefore, the transistor Q 1 0 1 is turned off, and the voltage of the signal line S does not rise to it. ^ As described above, in the fourteenth embodiment, each end of the capacitors C 1 0 1 and C 1 0 3 is connected to the source / drain electrode of the transistor Q 1 0 4 and the transistor Q 1 0 Because the gate electrode of 4 corresponds to the output voltage of the logic circuit 1 1 3, 'the voltage at point b and the voltage at point e in Fig. 3 can be controlled in the opposite direction, as in the first embodiment, (· Please Please read the notes on the back page first) Installation-line · This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) -64- 476854 A7 B7 V. Description of the invention (62) Logic circuit. 1 The voltage setting of the input terminal of 1 3 (point 13 in Fig. 32) must be slightly equal to the threshold of the logic circuit 1 1 3. For this reason, the circuit configuration is simpler than the embodiment 13 described above, and the threshold voltage of the logic circuit 1 13 and the differential voltage of the input video signal V i η are held in the capacitor C 1 0 1. Figure 3 4 shows the circuit diagram of the detailed structure of the load driving circuit 1 1 lb for the negative polarity. As shown in FIG. 3, the load driving circuit 1 1 1 b is a point where the transistors Q 1 0 1 and Q 1 0 4 are n-type M 0 S transistors, and the source electrode of the transistor Q 10 1 is grounded. This is different from the load driving circuit 1 1 1 a of FIG. 3, and the other is the same. However, the transistor Q 104 of this embodiment may be configured by a switching gate T G. Figure 3 5 is a circuit diagram of a load driving circuit 1 1 a for replacing the transistor Q 1 0 4 with the positive polarity of the switching gate TG, and Figure 3 6 is replacing the transistor Q 1 0 4 with the negative polarity of the switching gate TG. A circuit diagram of a 1 1 lb load drive circuit. As shown in FIG. 35¾ and FIG. 36, the switching gate G is composed of a P-type M 0 S transistor Q 1 4 1 and an N-type M 0S transistor Q 1 4 2. Device IV, connected to switch SW 107. [15th embodiment] The load driving circuit according to the 15th embodiment is connected to the terminal of the input image signal side of the capacitor when the capacitor holds the differential voltage between the input image signal voltage and the threshold voltage of the logic circuit Capacitor, this terminal can be stably maintained at the voltage of the input video signal. More details This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) -65--------------- Installation · ΓΙ Λ (Please read the note on the back first Matters on this page) Order · -line · Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 476854 A7 B7 V. Description of Invention (63) The description is as follows. . (Please read the caution page on the back first) Figure 3 7 is the circuit diagram of the Γ1 1 a nitrogen-driven drive circuit for positive polarity. Each load driving circuit 1 11 a is shown in FIG. 3 7 and has switches SW 1 〇1 to SW 1 〇7, and P MOS transistors Q 1 0 1 to Q 1 0 3 as analog switches, and The two segments of the inverter are connected vertically, and the logic circuit 1 1 3 and the capacitors C 1 〇1 to ci 〇4 are continuously connected. The switches 3 to 10 to 3 to 107 are switched and controlled by the switch switching control circuit 1 12 shown in Fig. 23. One end of the switch SW 1 〇1, SW 1 〇2 is connected to the signal line S, and the other end of the switch S 'W 1 〇1 is connected to one end of the switch SW 1 0 3 and the capacitor C 1 〇1, C 1 〇3 , C 1 〇4. The other end of the switch s W 103 is supplied with an input video signal V i η. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The other end of the capacitor C 1 0 1 is connected to the input terminal of the logic circuit 1 1 3 and one of the switches S W 1 05 and the drain terminal of the transistor Q 1 0 2. The output terminal of the logic circuit 1 13 is connected to the gate terminal of the transistor Q 1 0 1 and one terminal of the switch S W 107. To the source terminal of the transistor Q 1 0 1, a first voltage V D D (for example, 10 V) is applied, and the other terminal of the switch SW102 is connected to the drain terminal. A signal line S is connected to one end of the switch SW 1 〇4, and a second voltage VDD (for example, 5 V) is applied to the other end of the switch ^ _ SW 1 〇4. The source terminal of the transistor Q 1 0 2 is connected to cancel Terminal c Ν. Here, the cancellation terminal CN is applied with a cancellation voltage that changes linearly from 0 V to 10 V in a certain period. The other end of the switch SW1 〇5 is set to the third paper size applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) -66-476854 A7 B7 V. Description of the invention (64) Voltage (eg 0 V ) 〇 The other P terminal of the capacitor C 103 is connected to one terminal of the switch s W 10 and the source terminal of the transistor Q 103. The drain terminal connection of the transistor Q 1 0 3 is reversed to the cancel terminal C NR. Here the reverse cancellation terminal C N R is applied to a linear piano with a period of 10 V to ΰ V; ΐ ΐ: reverse cancellation voltage. The other end of the switch SW1 06 is set to the fourth voltage (for example, 10V). One terminal of the capacitor C104 is set to a fifth voltage (for example, 0 V). 'In Fig. 37, let the connection points of the switches S w 1 0 1, SW 1 0 3 and the capacitors C 1 〇1, C 1 0 3, and C 1 0 4 be a, and let the capacitor C 1 〇1 and the logic circuit 1 The connection point of 1 3 is b, the connection point of logic circuit 1 13 and transistor Q 1 0 1 is c, the connection point of switches SW101 and SW102 is d, and the capacitor C 1 〇3 and switch SW 1 〇6 The connection point is e. However, the capacitor C 1 0 1 constitutes the i-division voltage holding circuit of this embodiment, and the first voltage V D D constitutes the first voltage supply circuit of the embodiment. The switches SW 1 〇5 to SW 1 〇07 and the transistor Q 1 0 2, Q 1 0 3 and the capacitor C 1 0 3 constitute the threshold voltage setting circuit of this embodiment, and the capacitor C 1 0 4 constitutes the actual embodiment. Input voltage sustain circuit. Fig. 8 is a timing chart of each part in the load driving circuit 1 1 1 a of Fig. 37. Hereinafter, using this timing chart, the operation of the load driving circuit 1 1 1 a of Fig. 37 will be described. First of all, within the period from time T1 3 1 to T1 3 2, the paper size of the switch is applicable to the Chinese National Standard (CNS) A4 (210 X 297 public love) -67- 111! ··· Note on the back page) Order: • Printed by the Consumers Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 476854 Α7 Β7 V. Invention Description (65) Please read the note on the back page first) Replace the control circuit 1 1 2 series Only switch SW 1 0 4 is turned on. Therefore, the voltage of the signal line S is the same voltage as the second voltage V D (for example, 5 V). Next, during the period from time T 1 3 2 to T 1 3 3 ', the switch switching control circuit 1 1 2 turns off the switches SW 1 0 1, SW 1 /, 02, SW104, and SW107, and switches SW103, SW105 and SW106 are on. Therefore, the voltage at point a in FIG. 37 is the voltage of the input video signal V i η. In Fig. 3, the voltage of the input image signal V i η shows an example of 7 · 5 V. As described above, the reason why the voltage is 7.5V or more of 5V, the load driving circuit for positive polarity 1 1 1 a drives the signal line S, and because the switch SW 1 〇1 is turned off, the signal line S (FIG. 3 Point d of 7) is maintained at 5 V. Furthermore, the switches SW105 and SW106 are turned on. The connection point between the capacitor C 1 〇1 and the switch SW 1 〇5 (point b in FIG. 37) is 0V, and the capacitor C 1 〇3 and the switch SW1 〇6. The point ^ (point e in Figure 37) is 10 volts. The switch SW 1 07 is closed, and the employees ’cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs printed 5 clothing transistors Q1 02 and Q1 03 are closed. The capacitor C 1 04 is 7 · 5V of the voltage of the input signal V i η. Then, during the period from time T 1 3 3 to time T 1 35, the switch switching control circuit 1 1 2 only turns on the switch SW 107. In addition, during the period from time T 1 3 3 to time T 1 35, the cancellation terminal CN is changed linearly from 0 V to 10 V, and the reverse cancellation terminal CN R is changed linearly from 10 V to 0 V. However, the voltage setting of the CN terminal and CNR terminal is to switch the control circuit 1 1 2 or other circuits. -68- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 476854 A7 B7 V. Description of the Invention (66). At the time point 1 3 3, the output of the logic circuit 1 13 is at a low level. The transistors Q 1 〇2, Q 1 〇_3 are all turned on, the capacitor C 1 0 1 and the switch SW 1 〇5 The voltage at the connection point (b_ in Fig. 37) slowly rises, and the voltage at the connection point (point e in Fig. 37) between capacitor C1 03 and switch SW · 106 is gradually decreased. Order: At time 1 314, the voltage at point b in Figure 3 7 exceeds the threshold value of the logic circuit 1 1 3 (for example, 5 · 5: V), and the output of the logic circuit 1 1 3 is of high standard. Bit (about 10 volts), transistors Q 1 0 1 and transistors Q 1 0 2 and Q 1 0 3 are both off. For this reason, during the period from time T 1 3 4 to T 1 3 5, the threshold voltage of the logic circuit 1 1 3 at point b in FIG. 3 7 (for example, 5 · 5 V), and the voltage at point e in FIG. 3 7 The voltage is a predetermined voltage (for example, 1 0 V-5 · 5 V = 4 · 5 V) 〇-Wire-printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, that is, the input voltage of the logic circuit 1 1 3 is higher than the logic circuit 1 1 3 When the threshold voltage is high, the transistor Q 1 02 is turned off, so the voltage at point b in FIG. 37 is set to be equal to the threshold voltage of the logic circuit 1 13. At this time, the point a in FIG. 3 is stabilized and maintained at 7 · V of the voltage set to the input video signal V i η via the capacitor C 104. To this end, the differential voltage between the threshold voltage (5.5 V) of the logic circuit 113 and the voltage (7.5 V) of the input image signal V i η is maintained in the capacitor C 1 0 1. Then, at time τ 1 3 5, the switch switching control circuit 1 1 2 turns on the switches SW 1 0 1 and SW 1 〇2, so that the paper size of the switch applies the Chinese National Standard (CNS) A4 specification (210 X 297). (Mm) -69- 476854 A7 B7 V. Description of the invention (67) (Please read the caution page on the back first) SW 1 〇3 ~ SW 1 Q, 7 are closed. At the time point T 1 3 5, the voltage of the signal line S is 5 V, and the voltage of the point a of the signal 37 is 7. 5 V, which is affected by the voltage of the signal line s. The voltage drops. The capacitor C 1 〇 1 keeps the above-mentioned differential voltage (2V), and follows the voltage drop at point a to reduce the voltage at the input terminal (point b in Figure 37) of the circuit 1 1 3. In summary, the voltage at the input terminals of the logic circuit 1 1 3 is below the threshold voltage of the logic circuit 1 1 3, and the output of the logic circuit 1 13 is at a low level (about 0 V). As a result, the transistor Q 1 Ο Γ is turned on, and the voltage of the signal line S (point d in FIG. 37) rises. Correspondingly, the voltages at points a, b, and e in FIG. 37 also increase. At the time T136, the voltage at the input terminal (point b in Fig. 37) of the logic circuit 113 exceeded the threshold of the logic circuit 1 1 3, and the logic circuit 1 1 3 The output terminals are at a high level (about 10 volts). As a result, the transistor Q 1 0 1 is turned off, and the voltage of the signal line S (point d in FIG. 7) gradually decreases through the discharge of the capacity C 1 0 2. However, when it drops to a certain level, the voltage in FIG. 3 7 The voltage at point d is lower than the threshold voltage of the logic circuit 113, and the output terminal of the logic circuit 113 is at a low level (about 0V). For this reason, the transistor Q 1 JCU 1 is turned on again, and the voltage of the signal line S rises again. During this series of operations, the capacitor CIO 1 keeps the above-mentioned differential voltage (2V). After the time T 1 36, by repeating this operation, the signal line S (point d in FIG. 37) is maintained at the voltage of the input image signal V i η (about 7 · 5 V). This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -70-476854 A7 B7 V. Description of the invention (68) However, the circuit diagram of the load driving circuit 1 lib for negative polarity is shown in Figure 3 9 . The negative load driving circuit 1 1 1 b is a buffer circuit that drives the signal line S in the range of 0 V to 5 V. To this end, the transistor Q 1 0 1 is an n-type M 0 S transistor. At the extreme, the sub-system is connected to the ground, and the transistors Q 1 0 2 and Q 1 0 3 are also replaced: in the N-type MOS transistor. The switch SW1 05 is connected to a voltage terminal of 10V, and the switch SW1 06 is connected to a voltage terminal of 0V. The source terminal of the transistor Q 1 0 2 is connected to the inversion cancel terminal C N R, and the drain terminal of the transistor Q 1 0 3 is connected to the cancel terminal C N. In addition, since the structure and operation are the same as those of the load driving circuit 1 1 1 a for positive polarity, the detailed description is omitted here. As described above, when the load driving circuit 1 1 1 a, 1 1 1 b according to this embodiment, when the voltage of the signal line S is higher than the voltage of the input image signal V i η, the transistor Q1 〇1 is represented as Turn off and pull down the voltage of the signal line S. When the voltage of the signal line S is lower than the voltage of the input image signal V i η, turn on the transistor Q 1 Ο 1 to control the voltage of the signal line S. Therefore, the voltage of the signal line S is set to be slightly equal to the voltage of the input image signal V i η and maintained. In addition, as shown in FIG. 37 and FIG. 38, the voltage of the input video signal V i η and the threshold limit of the logic circuit 1 1 3 are obtained during the period of the characteristic variation and the time period (time 1 313 to 1 315). The differential voltage of the voltage is held in the capacitor C 1 〇1, the differential voltage is held in the state of the capacitor C 1 0 1, the transistor Q 1 〇 1 is on / off controlled, and the threshold of the logic circuit 1 1 3値 In a staggered state, during the settling period (at this time, the paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -71--Ί!-装 f JI (Please read the precautions on the back page first ) Order---· Line-Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 476854 A7 B7 V. Description of Invention (69) D 1 36 and later), the voltage supplied to the signal line S can be maintained and input the image signal The voltage of V i η is slightly equal. illlllllllln ^ i — < Please read the caution page on the back first> i-line · Also: as shown in Figure 37 and Figure 38, the capacitor C 1 〇4 is connected at point a in Figure 37, the characteristics are different The voltage at point a during the cancellation period (time 1 3 3 to T 1 3 5) is kept stable .. The input image signal V i set during the writing period to the capacitor (time T 1 3 2 to T 1 3 3) η voltage. That is, at the time when there is no capacitor C 1 0 4, the characteristic point cancellation period (time T 1 3 3 to T 1 3 5) in FIG. 3 at point a of FIG. 3 is due to the capacity of the transistor Q 1 0 2 and Q 1 0 3 Wait 'somehow floating. For this reason, in this embodiment, at a point 'a' in FIG. 37 via the connection capacitor C 1 · 04, during the writing period to the capacitor (time T132 to T133), the voltage of the input image signal Vin and 0V The differential voltage is held in the capacitor C 104, and this is also maintained during the cancellation period of the characteristic difference (time T 1 3 to D 1 35), and the point a is stably maintained at the input image signal V i η. -However, the transistors Q 1 0 and Q 1 0 3 of this embodiment may be configured by the switching gate T G. Figure 4 0 is a circuit diagram of the transistor Q 1 0 2. The printed clothing Q 1 0 3 of the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs sets k as the load driving circuit 1 1 1 a for the positive polarity of the switching gate TG, Figure 4 1 is a circuit diagram in which the transistor Q 1 〇2, f Q 1 0 3 is replaced with a load driving circuit 11 1 lb for the negative polarity of the switching gate TG. As shown in FIG. 41 and FIG. 42, the switching gate TG is composed of a P-type MOS transistor Q 1 3′1 and an N-type MOS transistor Q 1 3 2, so that the P-type M 0 S The gate terminal of the transistor Q 1 3 1 is connected to the switch SW 1 〇7 through the inverter IV. The paper standard can also be used in China National Standard (CNS) A4 (210 X 297 public love) -72 · 476854: A7 B7 V. Description of the Invention (.70)-[16th Embodiment] The load driving circuit of the 16th embodiment is a simplified version of the load driving circuit of the 15th embodiment described above. II: · Fig. 4 The circuit of the 16th embodiment of the load driving circuit is the same as the above-mentioned 15th embodiment, for example, as the signal line driving circuit 3 of the liquid crystal display device shown in Fig. 4 The circuit of 42 is a feature that replaces the transistors Q 1 0 2 and Q 1 0 3 of the circuit of FIG. 37, and the transistor Q 1 0 4 is provided. One of the source / drain electrodes of the transistor Q 1 0 4 is connected between the capacitor C 1 0 1 and the switch SW 1 0 05, and the other is connected between the capacitor C 1 0 3 and the switch SW 1 0 5 between. The gate terminal of the transistor Q 1 0 4 is connected to one terminal of the switch SW 1 0 7. In FIG. 42, let the connection points of the switches SW101, SW103fc, capacitors C101, C103, and C104 be a, let the connection point of the capacitor C 1 0 1 and the logic circuit 1 1 3 be b, and let the logic circuit 1 1 3 and the electrical body Q The connection point of 1 0 1 is c, the connection point of switches SW101 and SW102 is d, and the connection point of capacitor _ C 1 0 3 and switch SW1 06 is e. However, the capacitor C 1 0 1 constitutes the differential voltage holding circuit of this embodiment, and the first voltage VDD constitutes the first voltage supply circuit of this embodiment. The switches SW 1 0 5 to SW 1 0 7 and the transistor Q 1 0 4 and capacitor C 1 0 3 constitute the threshold and voltage of this embodiment. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm). 73-ίι .--------- --- Install I * {Please read the note on the back page first) Order: --Line-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 5 8 7 --------- B7 ______ 5. Description of the invention (71) Setting circuit, capacitor C 1.0 4 constitutes the input voltage maintaining circuit of this embodiment. . Fig. 4 3 shows the parts Bf Η in the load driving circuit 1 1 1 a of Fig. 42. Hereinafter, using this timing chart, the operation of the load driving circuit 1 1 1 a of Fig. 42 will be described. First, during the period from time T 1 4 1 to T 1 42, the switch switching control circuit 1 1 2 only turns on the switch SW 1 04. Therefore, the voltage of the ft line S is the same voltage as the second voltage VD (for example, 5 V). ○ •-Then, during the period of time τ 1 4 2 to D 1 4 3, the switch switching control circuit 1 1 2 The switches SW 1 〇1, SW 1 〇2, SW 104, SW 107 are turned off, and the switches SW103, SW105, SW106 are turned on. Therefore, the voltage at point a in FIG. 42 is a voltage (for example, 7 · 5 V) of the input video signal V i η. During this period, because the switch SW101 is turned off, the voltage of the signal line S (point d in FIG. 42) is maintained at 5V. In addition, the switches SW 1 〇5 and SW 106 are turned on, the point b in FIG. 42 is 0 V, the point e is 10 V, the switch SW 1 〇 7 is turned off, and the transistor Q 1 0 4 is turned off. . In addition, the capacitor C 104 is selected to have a voltage of 7.5 V of the input signal Vi η. Then, during the period from time T 1 4 3 to time T 1 4 5, the switch switching control circuit 1 1 2 only turns on the switch S W 1 0 7. At this time, the transistor Q 104 is turned on, and points b and e in Fig. 42 are short-circuited, and the two voltages change in the same direction. To be specific, please read the notice at the point b. The size of the paper is bound to the Chinese National Standard (CNS) A4 (210 X 297 g t) -74- 476854 τ 'Α7 _ Β7 V. Description of the invention (72) The voltage system gradually rises from 0 V, and the voltage at point .e gradually decreases from 10 V. i III 1 --— — — — — — i — * ί Please read the Precautions on the back page first) At the time of T 1 4 4 > Input terminal of logic circuit 1 1 3 (point b in Figure 4 2) ) The voltage exceeds the threshold of the logic circuit 1 1 3. The output voltage of the logic circuit 1 1 3 changes to a high level (for example, 1 QV). As a result, the transistor Q 104 is turned off, and the voltage at b / point does not rise above this. Therefore, the voltage of the input terminal (point b in Fig. 42) of the logic circuit 1 13 is set to be slightly equal to the threshold voltage of the logic circuit 1 1 3. At this time, point a in FIG. 42 is stabilized and maintained at 7 · _5 V of the voltage of the input video signal V i η through the capacitor C 104. Therefore, the differential voltage (2V) between the threshold voltage (5 · 5 V) of the logic circuit 1 1 3 and the voltage (for example, 7 · 5 V) of the input image signal V i η is maintained in the capacitor C 1 0 4. Then, at time τ 1 4 5, the switch switching control circuit 1 1 2 causes the switches SW 1 〇1, SW 1 〇2 to be turned on, so that the switches-... '-one-one-line-the staff of the Intellectual Property Bureau of the Ministry of Economy Cooperative printed SW1 0 3 ~ SW1 07 are closed. Therefore, the capacitor c 1 01 is in a state of maintaining the above-mentioned differential voltage (2 V), and the voltages at points a and b in FIG. 4 are temporarily decreased, so that the transistor Q 1 〇1 is turned on, and the voltage of the signal line S is Slowly rising. Then, at time T1 46, the voltage of the input terminals of the logic circuit 1 1 3 (point b in Figure 4) exceeds the threshold voltage of the logic circuit 1 1 3, and the output terminals of the logic circuit 1 1 3 are high. Level (eg 10 V). As a result, the transistor Q 1 〇 1 is turned off, and the voltage of the signal line S (point d in FIG. 4) is discharged from the capacity C 1 02 and gradually decreases. However, when the voltage drops to a certain level, the voltage at point d in Figure 4 is higher than the logic voltage of -75. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 476854 ..... A7 B7 V. Description of the invention (73) {Please read the precautions on the back page first) The threshold of the circuit 1 1 3 is low, and the output terminals of the logic circuit 1 1 3 are at a low level (· about 〇 V) 4. "To this end, the transistor Q 1 0 1 is turned on again, and the voltage of the signal line S rises again. After time 1 D 6, by repeating this action, the signal line S (point d of Fig. 4 2) is maintained. The voltage at the input image signal V i \ n (approximately 7 · 5 V) ○ However, the circuit diagram of the load driving circuit 1 1 1 b for negative polarity is shown in FIG. 3 9. The load driving circuit 1 11 b for negative polarity It is a buffer circuit that drives the signal line S in the range of 0 V to 5 V. To this end, the transistor Q 101 is an n-type MOS transistor. The source terminal is connected to ground. The transistor Q 102, Q103 is also replaced by an N-type MOS transistor. In addition, the switch SW1 〇5 is connected to a voltage terminal of 10 V, and the switch SW 1 〇6 is connected to a voltage terminal of 0 V. In addition, it is used for the above positive polarity The load drive circuit 1 1 1 a has the same structure and operation, so detailed descriptions are omitted here. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs as described above, the load drive circuit 1 1 1 a When 1 1 lb, when the voltage of the signal line S is higher than the voltage of the input image signal V i η When the transistor Q1 0 1 is turned off, the voltage of the signal line S is pulled down, and the voltage of the signal line S is lower than the input image signal. When the voltage of the signal V i η is low, the transistor Q 1 〇 1 is turned on, and In order to control the voltage of the signal line S, the voltage of the signal line S is set to be slightly equal to the voltage of the input image signal V i η and maintained. Also, as shown in FIG. 4 2 and FIG. During the uneven cancellation period (times T143 to T145), the paper size of the input image signal V in shall apply the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -76- 476854-----r. ' A7 B7 V. Description of the invention (material) The differential voltage of the threshold voltage of the logic circuit 1 1 3 is maintained in the capacitor C 1 〇1, and the differential exposure voltage is kept in the state of the capacitor C 1 0 1. The transistor Q 1 0.1 has on / off control. When the threshold value of the logic circuit 1 1 3 is in a staggered state, 'the voltage supplied to the signal line S' can be maintained during the settling period (after time 1.46). The voltage of the input image signal V i η is slightly the same. Also, as shown in FIG. 4 2 and FIG. 4 ' At point a, the capacitor C 1 0 4 is connected, so that the voltage at point a at the time when the characteristic variation is cancelled (at time T 1 4 3 to T 1 4 5) is kept stable during the writing period to the capacitor (at time T 1 4 3 to T 1 4 5) Set the voltage of the input image signal V i η. That is, when the capacitor C 1 0 4 is not in use, the voltage at point a in FIG. 42 of the characteristic variation cancellation period (time T1 43 to T1 45) is due to electricity. The capacity of the crystals Q 1 〇2, Q 1 0 3, and the like are somewhat floating. For this reason, in this embodiment, at the point a of FIG. 4 ′ via the connection capacitor C 1 0 4 ′, the voltage of the input image signal Vin is summed with 0 during the writing period to the capacitor (time 142 to 143). The differential voltage of V is held in the capacitor C 10 4 ′. This is also maintained during the characteristic variation cancellation period (time T 1 4 3 to T 1 4 5), and point a is stably maintained at the input image signal V i η. < However, the transistor Q 104 of the present embodiment may be constituted by a switching gate T G. Figure 4 5 is a circuit diagram of a load driving circuit 1 1 a for replacing the transistor Q 1 〇4 with the positive polarity of the switching gate τ G, and Figure 4 6 is replacing the transistor Q 1 〇4 with the negative pole of the switching gate TG. Circuit diagram of the load driving circuit 1 1 1 b for sexual use. So Figure 4 5 and Figure 4 6 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210x 297 mm) -77-— — — — — — Ί — ···· (Please read the caution page on the back first). --Line-Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 476854 A7 B7 V. Description of the Invention (75) 111! 11 Packs! < Please read the Cautions on the back page) as shown in the figure below. The switching gate TG is composed of P-type M 0 S transistor Q 1 4 1 and N-type M 0 S transistor Q 1 4. In this aspect, the inverter IV may be connected to the switch SW 107-. However, the present invention is not limited to the above-mentioned 12th to 16th embodiments, and various changes can be made. For example, in the 12th to 16th embodiments described by Ji, an example in which the load driving circuit according to the present invention is applied to the signal line driving circuit 3 in a liquid crystal display device will be described. However, the present invention excludes signal lines. In addition to the drive circuit 3, it can be widely applied. Also, various open relationships shown in Fig. 22 and the like can be constructed using a transfer gate or an analog switch. In addition, in FIG. 22 and the like, although an inverter for inverting the amplified input signal has been described, two segments are connected in series to form a logic circuit 1 1 3, but as long as it is a combination transistor configuration There is no particular limitation on the internal configuration of the logic circuit 1 1 3. ~ Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. In the above 12th to 16th embodiments, the signal line S is set to 5 V in advance, and the input image signal V i η is higher than 5 V. At this time, the positive load driving circuit 1 1 1 a is driven, and the signal line S is raised from 5V to the input image signal V i η. When the input image it number V i η is lower than 5 V, the negative polarity is driven. The load driving circuit 1 1 1 b reduces the signal line S from 5 V to the input image signal V i η, which can improve the correct voltage set on the signal line S. However, it is not necessary to provide both of a positive load driving circuit 1 1 1 a and a negative load driving circuit 1 1 1 b. For example, the signal line S is set to 5 V in advance, and the Chinese National Standard (CNS) A4 specification (210 X 297 mm) is only applied to this paper size. -78-476854 A7 B7 V. Description of the invention (.76) Positive load The driving circuit may increase the electrical trend of the input image signal V i η from the signal line S to 0 V to 10 V. In the above-mentioned 12th to 16th embodiments, any one of the positive load driving circuit 1 1 1 a and the negative load driving circuit 1 1 1 b of FIG. 23 corresponds to the input image. The bee bee > i η is driven, and regardless of the voltage of the input image signal V in, both of the load driving circuits 1 1 1 a and 1 1 1 b may be driven simultaneously. As explained in detail above, according to the present invention, after the voltage of the input terminal of the logic circuit is set to be slightly equal to the threshold value of the logic circuit, the external input signal is supplied to the driving load. The threshold value varies, and the voltage supplied to the driving load does not accept its influence. Therefore, when the present invention is applied to, for example, a signal driving circuit of a liquid crystal display device, a liquid crystal display device of a driving circuit integrated type having excellent display quality without unevenness in brightness can be obtained. [17th embodiment] The load driving circuit according to the 17th embodiment is a differential voltage of the threshold voltage of the logic circuit that controls the voltage of the input image signal and the logic circuit that controls the voltage of the signal line to the transistor. After being kept at the capacitor and #, the voltage of the signal line is supplied to the ground, so that the threshold of the logic circuit will be absorbed by the capacitor. In addition, a constant current circuit ground is provided between the transistor and the voltage source, and the ratio of the voltage change of the signal line when the signal line is supplied with voltage is constant to ensure the linearity of the load amplification circuit. In more detail, the description is as follows: i This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -79-iln — 1 — ml! · I 1 »(Please read the precautions on the back page first ) Order ·. · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 476854 II. A7 B7 V. Description of the invention (77) Fig. 4 7 is a circuit team showing the structure of the main part of the load driving circuit of the 17th embodiment of the present invention. Fig. 48 is a schematic block diagram showing the structure of the load driving circuit body. Figures 4 to 9 are diagrams for explaining the operation of a load driving circuit for positive polarity and a load driving circuit for positive polarity. Fig. 4 is a signal line drive circuit 3, which is configured using a load drive circuit shown in Fig. 8. The load driving circuit of FIG. 8 has a load driving circuit 2 1 1 a for a positive polarity and a load driving circuit 2 1 1 b for a negative polarity corresponding to each signal line, and the load driving circuit 2 is switched and controlled. Switching control circuit for various switches in 1 1 a, 2 1 1 b 2 1 2 〇 Figure 4 9 is a diagram for explaining the operation of a load driving circuit for positive polarity and a load driving circuit for positive polarity. As shown in FIG. 4-9, in this embodiment, the input video signal V i η is a signal between 0V and 10V, and this input video signal V i η is divided into 0V to 5V and 5V to 12V. In the two cases, a load driving circuit for driving a positive polarity ~ 2 1 1 a and a load driving circuit for a negative polarity 2 1 1 b. That is, the load driving circuit 2 1 1 b for the negative polarity sets the signal line S at 0 V in advance, and when the input video signal V i η is between 0 V and 5 V, the voltage of the signal line S is reduced to the input video signal. Buffer of V i η and wing. The load driving circuit for positive polarity 2 1 1 a is to set the signal line S to 10 volts in advance, and when the input image signal V i η is 5 V to 10 volts, the voltage of the signal line S is reduced to the input image. A buffer circuit that operates on the voltage of the signal V i η. Driven by any of these load driving circuits 2 1 1 a, 2 1 1 b, the paper size is controlled by a switch to apply the Chinese National Standard (CNS) A4 specification (210 X 297 public love) · 80-I I- --- 1 ------- Install i — (Please read the note on the back page first) Order: Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 476854 A7 B7 V. Instructions (78) 2 1 2 to control. However, the center of this embodiment will switch the driving voltage of the load driving circuit 2 1 1 a for the positive polarity and the load driving circuit 2 1 1 b for the negative polarity to the input image having a voltage amplitude of 0 to 10 V. The signal V i η is 5 V at an intermediate voltage, but a voltage other than the intermediate voltage may be set. Figure 4 7 is a circuit diagram of a load driving circuit 2 1 1 b for positive polarity. Each load driving circuit 2 1 1 b is shown in FIG. 4 7, and includes a switch SW 2 0 1 to a switch SW 2 0 4 and a transistor Q 2 0 1 formed by a P M 0 S transistor and the aforementioned inverter. The logic circuit 2 1 3 formed by 2 1 4 and the post inverter 2 1 5, and the capacitor C 2 0 1, and the constant current circuit I 1. In the signal line S driven by the load driving circuits 2 1 1 a and 2 1 1 b, as shown in FIG. 4, the TFT for liquid crystal display, liquid crystal capacity, and auxiliary capacity are connected. FIG. 4 is simplified to make the signal The load of line S is equivalent impedance R and capacitor C 2 0 2. One terminal of the switches SW 2 0 1 and SW 2 0 2 is connected to the signal line S, and the other terminal of the switch SW 2 0 1 is connected to one terminal of the switch SW 2 0 3 and one terminal of the capacitor C 2 0 1 and is connected to the switch SW 2 0 3 At the other end, an input video signal V i η is supplied. The other end of capacitor C 2 0. is connected to the input terminal of logic circuit 2 1 3, and the output terminal of logic circuit 2 1 3 is connected to the gate terminal of transistor Q 2 0 1. The source terminal voltage V D D (for example, 10 V) of the transistor Q 2 0 1 is applied through the constant current circuit I 1, and the drain terminal is connected to the other end of the switch SW 2 0 2. Connect the signal to one end of switch SW2 0 4 This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) .81-!!! · Install i _ * (Please read the precautions on the back page first) -Ή. --Line-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 476854 A7 B7 V. Description of the Invention (79) Please read the precautions on the back page) Line S, switch SW 2 0. 4 and other Apply voltage VSS (for example 0 V) at one end. The switch SW 2 0 1 > SW 2 0 4 is switched and controlled by the switch switching control circuit 2 1 2 shown in FIG. 4 8. -In Fig. 4, let the connection point of switch SW2 0 1 and capacitor C 2 0 1 be a, let the connection point of capacitor C 2 0 1 and logic circuit 2 Γ.3 be b, and let logic circuit 2 1 3 and electrical The connection point of the crystal Q2 0 1 is c, and the connection point of the switches SW20 1 and SW202 is d. However, the capacitor C 2 0 1 constitutes a differential voltage holding circuit of this embodiment, and the voltage source of voltage VDD and the constant current circuit I 1 constitute a voltage changing circuit that changes the voltage of the signal line S of this embodiment by a certain ratio. The switch SW 203 constitutes the input voltage setting circuit of this embodiment. Fig. 50 is a timing chart of each part in the load driving circuit 2 1 1 b of Fig. 47. Hereinafter, using this timing chart, the operation of the load driving circuit 2 1 1 b of Fig. 4 will be described. First, during the time period T 2 1 1 to T 2 1 2 (reset period), the switch switching control circuit 2 1 2 is to switch SW 2 0 1 to SW 2 0 1 to print clothing for the cooperative of employees of the Intellectual Property Bureau of the Ministry of Economic Affairs. 0 3 is turned off, and the switch SW 2 0 4 is turned on. Therefore, the voltage of the signal line S (point d in FIG. 47) is the same voltage (for example, 0 V) as the voltage V S S Qin. Next, during the period from time T2 1 2 to T2 1 3 (writing period of the capacitor), the switch switching control circuit 2 1 2 only turns on the switch SW1 03. Therefore, the voltage at point a in Fig. 47 is equal to the voltage of the input video signal V i η. In Fig. 50, the input image signal is in accordance with the Chinese National Standard (CNS) A4 specification (210 X 297). -82 · 476854 A7 _ B7 V. Description of the voltage (BO) V i η voltage display 3 V example. However, because the switch S W 2 0 1 is turned off, the voltage of the signal line S (the point in FIG. 47) is maintained at 0v. Binding here 'When the threshold voltage of the front-stage inverter 2 1 4 is assumed to be 5 V, the voltage of the input terminal of the front-stage inverter 2 1 4 (point b in Figure 4 7) is determined by some means. , Set at the threshold voltage of the front-end inverter 2 1.4. The point b in FIG. 47 is set to the threshold of the front-stage inverter 2 1 4 and the method of the voltage is described in other embodiments described later. When the input terminal of the inverter 2 1 4 in the previous section is set to the threshold voltage, the voltage of the output terminal of the logic circuit 2 1 3 (point c in Fig. 47) is almost equal to 10 V of the power supply voltage. Therefore, the series transistor Q 2 0 1 is turned off during this period. At this time, the switch SW 2 0 3 is turned on, and the voltage at point a in FIG. 4 is 3 V of the voltage of the input image signal V i η. For this reason, a difference voltage (for example, 2 V) between the voltage of the input image signal V i η (for example, 3 V) and the threshold 値 (for example, 5 V) of the previous-stage inverter 2 1 4 is maintained in the capacitor C 2 0 1. ^ Then, after time T 2 1 3 (writing period, settling period), the switch switching control circuit 2 1 2 makes the switch SW 2 0 1. The SW202 printed by the employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Economy turns on, and the switches SW203, SW204 is closed. At time T 2 1 3, point a in Fig. 4 is for 31, and point d is 0V. When switch SW2 0 1 is turned on, the voltage at point a is continuously decreased by point d. Capacitor C 2 0 1 maintains the above-mentioned differential voltage (2V). The voltage at point b of the other end of this capacitor C 2 01 follows the voltage drop at point a. The output of logic circuit 2 1 3 is reversed. Turn to a low level (for example, 0 V). Therefore, the paper size of the transistor applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -83- 476854 A7 __B7___ V. Description of the invention (81) !! · Install i I (Please read the first Note on this page) Q 2 〇 1 is on, a certain current self-defining current circuit I 1 is connected to the transistor Q 2 Ο 1 and the switch SW 2 0 2 "for the signal line S, the signal line S (Figure 4 7 of The voltage at point d) rises with a certain slope. When the voltage of the signal line S rises with a certain slope, the voltages corresponding to points a and b in this figure 47 also rise with a certain slope, and then, At time T 2 1 4, the voltage of the signal line S is equal to 3 V of the voltage of the input image signal V i η, and the voltage at point a in Fig. 4 is also equal to 3 V. The capacitor C 2 0 1 maintains the above-mentioned differential voltage (2 V ) Therefore, the voltage at point b in Fig. 4 is 5 V of the previous-stage inverter 2 1 4. For this reason, the output of the logic circuit 2 1 3 is inverted to a high level (for example, 1 0 V). As a result, the transistor Q 2 Ο 1 is turned off, and the current supply from the self-defined current circuit I 1 to the signal line 8, that is, the supply of the voltage is cut off. Through this action, the signal line S is set to have a voltage slightly equal to the input image signal V i η. --Line · Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economy Figure 5 1 is a circuit diagram showing the detailed structure of a load drive circuit for positive polarity 2 1 1 a As shown in Fig. 51, the negative driving circuit 2 1 1 a for positive polarity Q 2 Ο 1 is η-type, and the constant current circuit I 1 is connected to the voltage VSS, and the negative electrode of Fig. 4 7 The load driving circuit 2 1 1 b for sexual use is different. Except for the point, the detailed description is omitted for the same reason as the load driving circuit 2 1 1 b for negative polarity described above. As described above, according to the first aspect of the present invention, 17 When the load drive circuit 2 1 1 b of the embodiment is implemented, the capacitor C 2 Ο 1 maintains a differential voltage state, and switches SW 2 Ο 1, SW 2 Ο · 2 and the logic circuit 2 1 3 and the transistor Q 2 〇 1To form a return loop, the voltage of the signal line S is set to OV in advance, and the voltage VDD is passed through the transistor Q20 1 • 84- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ) 476854 A7 —. ^ B7 V. Description of the invention (82) 'Supply signal line S, letter When the voltage of the line S is slightly equal to the voltage of the input image signal vi η, the snow crystal q 2 0 1 is turned off. Because the supply of the voltage VDD is cut off, the setting of the signal line S is slightly equal to the input image signal V The voltage of i η is maintained. The differential voltage of the threshold voltage of the preceding inverter 2 1 4 and the voltage of the input video signal V i η is held by the capacitor C 2 0 1 and then the input video signal is supplied to the signal line S. For the reason of V i η, when the threshold voltage of the previous-stage inverter 2 1 4 varies, the voltage of the signal line S is not affected. Furthermore, according to the load driving circuit 2 1 1 b according to this embodiment, when the signal line S is supplied with the voltage VDD, it is supplied through the constant current circuit I 1, regardless of the voltage of the input image signal V i η or The voltage of the signal line S changes with a certain slope, so that the voltage of the signal line S can be pulled up. That is, when the constant current circuit I 1 is not provided, as the voltage of the signal line S is close to the voltage VDD, the turn-on impedance of the transistor Q 2 0 1 will increase, and the signal line S will be generated. The phenomenon that the slope of the voltage rise becomes smaller. That is, the slope of the voltage rise of the signal line S is changed by the voltage set on the signal line S. 'Also, the logic circuit 2 1 3 has a circuit delay, so the input terminal of the good logic circuit 2 1 3 (the voltage at o'clock in b of Figure 4 7 reaches the threshold 値 until the transistor Q 2 0 1 is actually turned off. For a certain period of time, after careful consideration, the voltage set on the signal line S is slightly higher than the voltage of the input image signal Vin. Therefore, when the slope of the voltage rise of the signal line S changes, actually set this paper size to apply China National Standard (CNS) A4 Specification (210 X 297 mm) ~-85-： — 1! · Install i I 4 (Please read the precautions on the back page first) Order:-Line · Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the employee consumer cooperative 476854 A7 — B7 V. Description of the invention (83) The error between the voltage set on the signal line S and the voltage of the input image signal V i η is caused by the height of the voltage set on the signal line S. The phenomenon of non-uniformity. That is, the linearity of the load driving circuit 2 1 1 a is deteriorated. In this way, when there is a discrepancy between the voltage set on the signal line S and the voltage of the input video signal V i η, There is a risk of writing errors. In the load driving circuit 2 1 1 b related to this embodiment, there is no voltage on the signal line S, and the slope dt of the voltage rise of the signal line S is constant. Actually, the voltage and input image of the signal line S are set. The error of the voltage of the signal V i η can be a certain value. For this reason, the linearity of the load driving circuit 2 1 1 a can be ensured without causing a so-called write error. In addition, according to the load driving circuit of this embodiment When 2 1 1 b ', the differential voltage of capacitor C 2 0 1 is to be maintained, and when it is set to capacitor C 2 0 1, the threshold voltage of the front-end inverter 2 1 4 and the voltage of the input image signal V in, The & sampled in the same cycle can set the correct differential voltage when the setting of these two voltages is performed in separate cycles. [18th embodiment] _A eighth embodiment of the present invention The morphology is based on the voltage on the input terminal side of the front stage inverter 2 1 4 of the 17th embodiment (point b in FIG. 4). The specific method is shown in Fig. 5. 2 is for negative polarity of this embodiment. Load driving circuit according to China National Standard paper suitable scale (CNS) A4 size (210 X 297 mm) -86 - - i I Li mounted 11- < Please read the Precautions on the back page first) Order: i-line-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 476854 A7 B7 V. Circuit Description of Invention Note (β4) 2Γ1b. The load driving circuit 2 1 1 b according to this embodiment is shown in FIG. 47 described above, and the load driving circuit 2 1 1 b is configured by adding a switch SW 2 0 5 to a switch SW 2 0 8. One terminal of the switch SW 2 06 is connected to one terminal of the capacitor C 2 01, and the other terminal of the switch SW 2 06 is connected to the voltage VD D: (for example, 10). One end of the switch SW205 is connected to the input terminal of the front-end inverter 2 1 4, and the other end of the switch SW205 is connected to the output terminal of the front-end inverter 2 1 4. One end of the switch SW 2 〇7 is connected to the output terminal of the front-end inverter 2 1 4, the other end of the switch SW 2 0 7 is connected to the input terminal of the rear-end inverter 2 1 5, and one end of the switch SW 2 0 8 is Connected to the input terminal of the rear-stage inverter 2 1 5, and the other end of the switch SW 2 0 8 is connected to the voltage VSS (for example, 0λ). The switches SW 2 0 5 to SW 2 0 8 are also switched and controlled by the switching control circuit 2 1 2 shown in FIG. 4 8. In Fig. 52, let the connection point of the switch SW2 01 and the capacitor C 20 1 be a, let the connection point of the capacitor C 2 0 1 and the logic circuit 2 1 3 be b, and let the logic circuit 2 1 3 and the transistor Q 2 0 The connection point of 1 is c, and the connection point of switches SW 2 0 1 and SW 2 0 2 is d. However, the capacitor C 2 0 1 constitutes a differential voltage holding circuit, a voltage source of voltage VDD, and a constant current circuit. I 1 constitutes a voltage changing circuit that changes the voltage of the signal line S of this embodiment by a certain ratio, switch SW 2 0 3 constitutes the input voltage setting circuit of this embodiment, and the return loop structure of switch SW 2 0 5 This form of implementation — 1 !!! Install i 1 «Γ4 Read the precautions on the back ^^^ This page > Order *; Line · The paper printed by the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economy applies the Chinese national standard ( CNS) A4 specification (210 X 297 mm) -87 · 476854 A7 _ B7 V. Description of invention (85) Threshold voltage setting circuit, {Please read the precautions on the back page first) Figure 5 3 Series Figure 5 2 Load-Driver Circuit 2 lib Timing Chart 'Below, use this timing chart Description of the load driving circuit 52 in FIG. 2 1 1 b of operation. • First, during the period from time T 2 2 1 to T 2 2 2, (the reset period), the 'switch switching control circuit 2 1 2 turns on the switches SW2 04, SW206, and SW208, and switches SW201 to SW 2 0 3, SW 2 0 5, SW 2 0 7 are off. Therefore, the voltage of the signal line S (point d in FIG. 52) is the same voltage as the voltage V S S (for example, 0 V). In addition, the voltage of the input terminal of the front-stage inverter 2 1 4 is the same voltage as the voltage VDD (for example, 10V), and the voltage of the input terminal of the rear-stage inverter 2 1 5 is the same voltage as the voltage VSS ( (Eg 0 V). Here, the voltage of the input terminal of the front-end inverter 2 1 4 is a voltage VDD, and the voltage of the input terminal of the back-end inverter 2 1 5 is a voltage VSS. The Ministry of Intellectual Property Bureau employee consumer cooperatives printed the C MOS transistor of the garment phaser 2 15 and did not flow through the current. That is, the M 0S transistor, which is one of the P-type M 0S transistor and the n-type M0S transistor constituting the C M 0S transistor, is sufficiently closed to prevent the through current from flowing. As a result, it is possible to reduce the power consumption of the load driving circuit 2 1 1 b. Therefore, the voltage applied to the input terminal of the front-stage inverter 214 and the input terminal of the rear-stage inverter 215 may be any of the voltage V D D (for example, 10 V) and the voltage V S S (for example, 0 V). Then, at the time T 2 2 2 to T 2 2 3 (the paper size of the capacitor applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -88- •....... —. ·· *. ...- *. * — A7 ______ B7 _______ V. In the description of the invention (86) During writing), the switch switching control circuit 2 1 2 only makes the switches SW 2 0 3, SW 2 0 5 is turned on-, and switches SW 2 0 1, SW202, S204, SW0 6 to SW 208 are turned off. Therefore, the voltage at point a in FIG. 52 is equal to the voltage of the input image signal V in. In FIG. 53, the voltage of the input video signal V i η is an example of 3 V. However, because the switch S W 2 0 1 is turned off, the voltage of the signal line S (point d in FIG. 4) is maintained at 0 V. In addition, because the switch SW 2 0 5 is turned on, the voltage set at point b in FIG. 5 is set to be slightly equal to the threshold voltage (in this case, 5 V) of the inverter 2 14 in the previous section. That is, by feeding back the output of the front-stage inverter 2 1 4 to the input, the voltage of the input terminal and output terminal of the front-stage inverter 2 1 4 is set to be slightly equal to the threshold voltage of the front-stage inverter 2 1 4. Voltage. Therefore, the capacitor C20 1 maintains a differential voltage (for example, 2 V) between the voltage of the input image signal V i η (for example, 3 V) and the threshold 値 (for example, 5 V) of the previous-stage inverter 2 1 4. 1 After the time ′ T 2 2 3 (writing period, settling period), the switch switching control circuit 2 1 2 turns on the switches SW 2 0 1, SW202, SW207, and switches SW203 to SW206, SW208 turn off. At the time point T223, point a in Fig. 5 is 3 V, and point d is 0 V. For this reason, when the switch SW 2 01 is turned on, the voltage at point a is continuously decreased by point d. Capacitor C 2 0 1 maintains the above-mentioned differential voltage (2V). The voltage at point b on the other end of this electric valley isC 2 0 1 also follows the voltage drop at point a. The output of logic circuit 2 1 3 It is reversed, showing a low level. The paper size is applicable to China National Standard (CNS) A4 (210 X 297 public love) Tg9 · ~ (Please read the precautions on the back before filling this page) • Line. TL · A7 B7 V. Description of the invention (87) (e.g. 0 V). As a result, the transistor q 2 〇1 is turned on, and a certain current self-determined current circuit I 1 is supplied to the signal line S and the signal line s (point d in FIG. 5 2) through the transistor Q2 0 1 and the switch SW2 0 2. ) Voltage rises with a certain slope dt. When the voltage of the signal line S rises with a certain slope d t, the voltage corresponding to points a and b in this figure 52 also rises with a certain slope d t. Then, at time T224, the voltage of the signal line S is equal to 3 V of the voltage of the input image signal V i η, and the voltage at point a in Fig. 52 is also equal to 3 V. The capacitor C 2 0 1 maintains the above-mentioned differential voltage (2 V), and the voltage at the point b of the rigid 5 2 is 5 V of the previous-stage inverter 2 1 4. For this reason, the output of the logic circuit 2 1 3 is then inverted to a high level (for example, 10 V). As a result, the transistor Q 2 0 1 is turned off, and the current supply from the self-defined current circuit I 1 to the signal line S, that is, the supply of the voltage is cut off. After this action, the signal line S is set to-*-r 3 V which is slightly equal to the voltage of the input image signal V i η. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ----- I------ --Install i — •. (Please read the Precautions on the back page first) --Wire. Figure 5 4 is a circuit diagram showing the detailed structure of the load drive circuit 2 1 1 a for positive polarity. As shown in FIG. 5, the load driving circuit for positive polarity 2 1 1 a series transistor Q 2 0 1 is η-type, and the constant current circuit I 1 is connected to the voltage VSS, which is the same as the negative polarity of FIG. 5 2. Used · The load drive circuit 2 1 lb is different. Except for this point, it is the same as the load driving circuit 211b for the above-mentioned negative polarity, and its detailed description is omitted. As described above, according to the load driving circuit 2 1 1 b according to the eighteenth embodiment of the present invention, similarly to the aforementioned seventeenth embodiment, the setting of the signal line S is slightly equal to the input image signal V. i η voltage. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) .9〇. B7 V. Description of the invention (88) --------------- Packing · 1 ·鑤 (Please read the caution page on the back first) Also, keep the differential voltage between the threshold voltage of the front inverter 2 1 4 and the voltage of the input image signal V in after the capacitor c 2 0 1 and the signal line. Because S supplies the input image signal V i η-, when the threshold voltage of the previous-stage inverter 2 1 4 varies, the voltage of the signal line S is not affected by this. · 乂 · Furthermore, according to the load driving circuit 2 1 1 b according to this embodiment, when the voltage VDD is supplied from the signal line S, it is supplied through the constant current circuit I 1, regardless of the input image price number V i The voltage of η or the voltage of the signal line S changes with a certain slope dt, so that the voltage of the signal line S can be pulled up. For this reason, the linearity of the load driving circuit 2 1 1 a can be ensured, that is, a so-called write error does not occur. When the load drive circuit 2 1 1 b according to this embodiment is used, the differential voltage of the capacitor C 2 0 1 is to be set to the capacitor C 2 〇1, and the front-end inverter 2 1 4 The threshold voltage and the voltage of the input image signal V i η are sampled in the same cycle ^, and when the setting of these two voltages is performed in separate cycles, the correct differential voltage can be set. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs However, the present invention is not limited to the aforementioned 17th embodiment and the 18th embodiment, and various changes can be made. For example, in the aforementioned _17th embodiment and the 18th embodiment, examples in which the load driving circuit of the present invention is applied to the signal line driving circuit 3 in the liquid crystal display device will be described, but the present invention is in addition to In addition to the signal line driving circuit 3, it can be widely applied. In addition, the various paper sizes shown in the 17th and 18th embodiments described above are applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) -91-476854 A7 ______B7_____ V. Description of the Invention (89)- --------------- Equipment— (Please read the note on the back page first) The opening relationship can be constructed by using a transfer gate or analog switch. Moreover, in the above embodiment, although the inverter which inverts the signal of the amplitude input has been described, two segments are connected continuously in series to form a logic circuit 2 1 3. However, as long as it is a combination of a transistor, the logic The internal configuration of the circuit 2 1 3 is not particularly limited. / 2 · Line · In addition, in the 17th and 18th embodiments, when the input video signal V i η is higher than 5 V, a load driving circuit 2 1 1 a for driving positive polarity is used. When the signal line 8 rises from 10 to the input image signal V i η, and the input image signal V i η is lower than 5 V, the negative load driving circuit 1 1 1 b is driven, and the signal line S is shifted from 0 V Falling to the input image signal V ′ i η can improve the accuracy of the voltage set on the signal line S. However, it is not necessary to provide both of the positive load driving circuit 1 1 1 a and the negative load driving circuit 1 1 1 b. For example, the signal line S is set to 0 V in advance, and the circuit is driven only by a positive load, and the input image signal V i η voltage of the signal line S is raised to 0 V to 1 0 V. It can also be consumed by employees of the Intellectual Property Bureau of the Ministry of Economy Cooperatives print / Any one of the seventeenth and eighteenth embodiments described above, either of the positive load driving circuit 2 1 1 a and the negative load driving circuit 2 1 1 b of FIG. 48, The voltage corresponding to the input image signal V η is driven. Regardless of the voltage of the input image signal V i η, both of the load driving circuits 2 1 1 a and 2 1 1 b may be driven simultaneously. As explained in detail above, according to the present invention, the voltage constituting the input signal and the threshold voltage of the inverting amplifier circuit of the previous stage of the logic circuit are held behind the differential voltage holding circuit, and the voltage changing circuit is -92 -This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 4 5 8 6 7 A7 _______B7 ___ V. Description of the invention (90) The voltage of the signal line is changed by a certain proportion. For logic circuits When the threshold is different, the voltage of the signal line-can be set to be slightly equal to the voltage of the input signal. In addition, the error between the voltage of the input signal and the voltage of the actual set signal line is constant, which improves linearity. Therefore, when the present invention is applied to, for example, a signal driving circuit of a liquid crystal display device, a liquid crystal display device of a driving circuit integrated type having excellent display quality with no unevenness in brightness can be obtained. --------------- 装 i — 0 (Please read the note on the back page first)-• Line-Printed by the Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs This paper is applicable to China Standard (CNS) A4 size (210 X 297 mm) -93-

Claims (1)

476854 公告本丨_I__ 六、申請專利範圍 (請先閱讀背面之注意事項再填寫本頁) 1 · 一種信號增幅電路，屬於輸入以第1之寬度加以 振幅之數位輸入信號，增幅此數位輸入信號的振.幅，做爲’ 較前述第1之寬度爲大之第2之寬度加以振幅之數位輸出 信號加以輸出的信號增幅電路中，其特徵係具備 將以第1之寬度加以振幅之信號，增幅爲以較前述第 1之寬度爲大之前述第2之振幅加以振幅的信號，做爲前 述數位輸出信號加以輸出的振幅增幅用邏輯電路， 和一端連接於前述振幅增幅用邏輯電路的差分電壓保持電 路中，暫時保持前述數位輸入信號之高和低之切換的基準 電壓，和略等於切換前述振幅增幅用邏輯電路之高和低之 邏輯的臨限値電壓的差分電壓的差分電壓保持電路， 和將前述差分電壓保持電路所欲保持之前述差分電壓，設 定於前述差分電壓保持電路之時，將前述差分電壓保持電 路之另一端設定爲前述數位輸入信號之高和低之邏輯會切 換的基準電壓的基準電壓設定電路， 經濟部智慧財產局員工消費合作社印製 和前述差分電壓保持電路保持前述差分電壓之後，於前述 差分電壓保持電路之前述另一端輸入前述數位輸入信號的 數位信號輸入電路者。 2 .如申請專利範圍第1項之信號增幅電路，其中， 前述差分電壓保持電路係具備一端連接於前述振幅增幅用 邏輯電路之輸入端子，另一端係連接於前述基準電壓設定 電路和前述數位信號輸入電路的第1電容器。 3 ·如申請專利範圍第2項之信號增幅電路，其中， 前述臨限値電壓設定電路係具備一端連接於即述第1電容 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） "" — -94- 476854 B8 C8 __ _ D8__ 六、申請專利範圍 器之前述一端，另一端連接於設定前述差分電壓時，自第 1電壓向第2電壓直線變化“的取消端子的第1開關中，於 前述第-1電容器在設定前述差分電壓時呈開啓，前述第1 電容器之前述一端略等於前述振幅增幅用邏輯電路之前述 臨限値電壓的電壓之時點呈關閉的第1開關者。‘/· 4 ·如申請專利範圍第3項之信號增幅電路，其中， 前述臨限値電壓設定電路係具備一端連接於前述第1電容 器之前述另一端的第2電容器， 和一端連接於前述第2電容器之另一端，另一端連接 於設定前述差分電壓時，自前述第2電壓向前述第1電壓 直線變化的取消端子的第2開關中，於前述第1電容器在 設定前述差分電壓時呈開啓，前述第1電容器之前述一端 略等於前述振幅增幅用邏輯電路之前述臨限値電壓的電壓 之時點呈關閉的第2開關者。 -' 一- 5 ·如申請專利範圍第4項之信號增幅電路，其中， 更具備於前述第1電容器設定前述差分電壓之時，將前述 第1電容器之前述另一端之電壓維持於前述基準電壓的基 準電壓維持電路。 6 ·如申請專利範圍第5項之信號增幅電路其中， 前述第1開關和前述第2開關係各具有p型Μ〇S電晶體 和η型Μ〇S電晶體的轉換閘者。 7 .如申請專利範圍第2項之信號增幅電路，其中， 前述臨限値電壓設定電路係具備一端連接於前述第1電容 器之前述另一端的第3電容器， 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） (請先閎讀背面之注意Ϋ項再4476854 Bulletin 丨 _I__ VI. Patent Application Scope (Please read the notes on the back before filling this page) 1 · A signal amplifier circuit, which belongs to the digital input signal whose amplitude is increased by the first width, and this digital input signal is amplified The amplitude of the signal is a signal amplification circuit that outputs a digital output signal having an amplitude that is larger than the first width and a second width that is second. The signal amplification circuit is provided with a signal that amplitude is amplified by the first width. The amplification is a signal with an amplitude that is greater than the width of the first one and that is the second, and is used as the digital output signal to output the amplitude amplification logic circuit, and a differential voltage connected at one end to the amplitude amplification logic circuit. In the holding circuit, a differential voltage holding circuit that temporarily holds the reference voltage for switching the high and low of the aforementioned digital input signal, and a differential voltage that is slightly equal to the threshold voltage of the logic for switching the high and low of the amplitude increase logic circuit, And setting the differential voltage to be held by the differential voltage holding circuit to the differential voltage holding At the time of the circuit, the other end of the aforementioned differential voltage holding circuit is set as the reference voltage setting circuit of the reference voltage where the high and low logic of the digital input signal is switched. It is printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs and the aforementioned differential voltage. After the holding circuit holds the differential voltage, the digital signal input circuit inputs the digital input signal to the other end of the differential voltage holding circuit. 2. The signal amplifier circuit according to item 1 of the scope of patent application, wherein the differential voltage holding circuit is provided with one end connected to the input terminal of the amplitude amplification logic circuit, and the other end is connected to the reference voltage setting circuit and the digital signal. The first capacitor of the input circuit. 3. If the signal amplification circuit of item 2 of the patent application scope, wherein the threshold voltage setting circuit is provided with one end connected to the first capacitor, the paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) " " — -94- 476854 B8 C8 __ _ D8__ VI. The aforementioned one end of the patent application range device and the other end are connected to the first voltage to the second voltage when the aforementioned differential voltage is set. In the first switch, the first switch that is turned on when the first differential capacitor is set to set the differential voltage, and the first end of the first capacitor is slightly equal to the voltage at the threshold voltage of the threshold voltage of the amplitude increase logic circuit. "/ · 4 · According to the signal amplification circuit of the third patent application range, wherein the threshold voltage setting circuit includes a second capacitor connected at one end to the other end of the first capacitor, and connected at one end to When the other end of the second capacitor is connected to the other end of the second capacitor, the second capacitor changes linearly from the second voltage to the first voltage. In the second switch of the canceling terminal, the first capacitor is turned on when the differential voltage is set, and the first end of the first capacitor is slightly equal to the voltage of the threshold voltage of the amplitude increase logic circuit. The second switcher.-'-1-The signal amplifier circuit according to item 4 of the scope of patent application, further comprising: when the first capacitor sets the differential voltage, the voltage of the other end of the first capacitor is set. A reference voltage maintaining circuit maintained at the aforementioned reference voltage. 6 · The signal amplifier circuit of item 5 of the patent application range, wherein each of the first switch and the second open relationship has a p-type MOS transistor and an n-type MOS. Switcher of S transistor. 7. The signal amplifier circuit according to item 2 of the scope of patent application, wherein the threshold voltage setting circuit includes a third capacitor connected at one end to the other end of the first capacitor. Paper size applies to Chinese National Standard (CNS) Α4 specification (210 × 297 mm) (Please read the note on the back first, then 4 I 經濟部智慧財產局員工消費合作社印製 -95- 申請專利範圍 和一端連接於前述第1電容器之前述一端，另一端連 胃&設定前述第3電容器之-另一端的第3開 胃1電容器在設定前述差分電壓時，該第3 端則連接於第3電壓，該第3開關之前述另 第4電壓的同時，於前述第χ電容設定前述 Μ開啓’前述第1電容器之前述一端略等於 邏輯電路之前述臨限値電壓的電壓之時點 開關者。 8 ·如申請專利範圍第2項之信號增幅 前述臨限値電壓設定電路係具備一端連接於 器之前述一端的第4·開關中，於前述第1電 述差分電壓時，該第4開關之前述一端則連 ’該第4開關之前述另一端則連接於第4電 前述第1電容設定前述差分電壓之時呈開啓 容器之前述一端略等於前述振幅增幅用邏輯 限値電壓的電壓之時點呈關閉的第4開關者。 經濟部智慧財產局員工消費合作社印製 關中，於前述 開關之前述一 一端則連.接於 _分電壓之時 前述振幅增幅 呈關閉的第3 電路，其中， 前述第1電容 容器在設定前 接於第3電壓 壓的同時，於 ，前述第1電 電路之前述臨 電路，其中， 之時，將前述 基準簟-壓的基 幅電路，其中 型Μ〇S電晶 幅電路，其中 請 先 閲 讀 背 面 之 注 9 ·如申請專利範圍第7項之信號增幅 更具備於前述第1電容器設定前述差分電壓 第1電容器之前述另一端之電壓維持於前述 準電壓維持電路。 1 0 .如申請專利範圍第9項之信號增 ，前述第4開關和前述第2開關係各具有P 體和η型Μ〇S電晶體的轉換閘者。 1 1 .如申請專利範圍第2項之信號增 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） -96- 476854 A8 B8 D8 六、申請專利範圍 經濟部智慧財產局員工消費合作社印製 ’ 述基準電壓設定電.路係具備一端連接於前述第i電容 器之前述另一端，另一端連-接於前述基準電壓之供給端子 的第5開關中，於差分電壓保持電路設定前述差分電壓時 呈開啓的第5開關者。 1 2 ·如申請專利範圍第2項之信號增幅.¾路，其中 ’前述數位信號輸入電路係具備一端連接於前述第1電容 器之前述另一端，另一端連接於前述數位輸入信號之輸入 端子的第6開關中，於差分電壓保持電路輸入前述數位輸 入信號時呈開啓的第6開關者。 1 3 · —種液晶顯示裝置，屬於具有形成於透明基板 上之畫素陣列部中，具有縱橫地形成信號線及掃瞄線，列 設於此等各線之交點附近的畫素電極之畫素陣列部， 和形成於前述透明基板上，進行前述信號線和前述掃 瞄線中至少一方之驅動的驅動電路中，具有將數位影像信 號變換呈類比影像信號之機能的驅動電路的液晶顯示裝置 中，其特徵係 ' 前述驅動電路係輸入以第1之寬度加以振幅之數位輸 入信號，增幅此數位輸入信號的振幅，做爲較前述第1之 寬度爲大之第2之寬度加以振幅之數位輸出信號旭_以輸出 的信號增幅電路中，將以第1之寬度加以振幅之信號，增 幅爲以較前述第1之寬度爲大之前述第2之振幅加以振幅 的信號，做爲前述數位輸出信號加以輸出的振幅增幅用邏 輯電路， 和一端連接於前述振幅增幅用邏輯電路的差分電壓保 請先W讀背面之注意事項再ijlRx> -裝· 訂 • l·· 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） •97- 5 8 6 7 經濟部智慧財產局員工消費合作社印製 ' A8 ' B8 C8 __ D8>、申請專利範圍 持電路中，暫時保持前述數位輸入信號之高和低之切換的 基準電壓，和略·等於切換前-述振幅增幅用邏輯電路之高和 低之邏輯的臨限値電壓的差分電壓的差分電壓保持電路， 和將前述差分電壓保持電路所欲保持之前述差分電壓 ’設定於前述差分電壓保持電路之時，將前述‘差分電壓保 持電路之前述一端設定爲略等於前述振幅增幅用邏輯電路 之前述臨限値電壓的電壓的臨限値電壓設定電路， 和將前述差分電壓保持電路所欲保持之前述差分電壓 ’設定於前述差分電壓保持電路之時，將前述差分電壓保 持電路之另一端設定爲前述數位輸入信號之高和低之邏輯 會切換的基準電壓的基準電壓設定電路， 和前述差分電壓保持電路保持前述差分電壓之後，於 前述差分電壓保持電路之前述另一端輸入前述數位輸入信 號的數位信號輸入電路者。 - …- · * 1 4 . 一種負荷驅動電路，屬於輸入所定之電壓振幅 之輸入信號，將此輸入信號之電壓供予連接負荷之信號線 的負荷驅動電路中，其特徵係具備 變更前述信號線之電壓之電壓變更電路， 和將前.述電壓變更電路和前述信號線間之導通— 呈關閉 /開啓的第1開關， 和輸入電壓呈所定之臨限値電壓時，反轉輸出邏輯， 控制前述第1開關之關閉/開啓的邏輯電路， 和保持略等於前述邏輯電路之前述臨限値電壓的電壓 和前述輸入信號之電壓的差分電壓的差分保持電路， 請 先 閲 讀 背 面 之 注 項 再 填I Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs-95- The scope of the patent application and one end is connected to the aforementioned one end of the first capacitor, and the other end is connected to the stomach & the third appetizer is set to the third capacitor-the other end of the first capacitor When the aforementioned differential voltage is set, the third terminal is connected to the third voltage, while the other fourth voltage of the third switch is set, and the aforementioned one end of the aforementioned first capacitor is set to be equal to the aforementioned χ capacitor. The logic circuit is switched at the time point of the threshold voltage. 8 · If the signal amplitude of the second patent application range is increased, the threshold voltage setting circuit is provided with a fourth switch with one end connected to the one end of the device. When the differential voltage of the first electric circuit is described above, The one end is connected to the other end of the fourth switch, and the other end of the fourth switch is connected to the fourth capacitor. When the first capacitor sets the differential voltage, the voltage at the first end of the container is slightly equal to the voltage at which the amplitude limit is logically limited. Closed 4th switcher. The third part of the circuit printed by the Intellectual Property Bureau of the Ministry of Economic Affairs ’s Consumer Cooperative is connected to the aforementioned one end of the switch. When it is connected to the sub-voltage, the third amplitude circuit is closed, and the first capacitor container is set before the setting. At the same time connected to the third voltage, at the same time, the aforementioned first circuit of the first electric circuit, wherein, at this time, the aforementioned reference voltage-voltage base-amplitude circuit, the medium-type MOS electric crystal amplitude circuit, among which please first Read Note 9 on the back side. If the signal increase of item 7 in the scope of patent application is more equipped with the aforementioned first capacitor, the voltage of the other end of the aforementioned first differential capacitor is maintained in the aforementioned quasi-voltage maintaining circuit. 10. If the signal of item 9 of the scope of patent application increases, the aforementioned fourth switch and the aforementioned second open relationship each have a switching body of a P body and an n-type MOS transistor. 1 1. If the signal increase in the scope of patent application No. 2 is used, the paper size shall be in accordance with Chinese National Standard (CNS) A4 specification (210 × 297 mm) -96- 476854 A8 B8 D8 The reference voltage setting circuit is printed. The circuit is provided with a fifth switch with one end connected to the other end of the i-th capacitor and the other end connected to the supply terminal of the reference voltage, and the differential is set in a differential voltage holding circuit. The fifth switch that is turned on at the time of voltage. 1 2 · If the signal increase range of the second item of the patent application is ¾ way, the aforementioned digital signal input circuit is provided with one end connected to the other end of the first capacitor and the other end connected to the input terminal of the digital input signal. The sixth switch is a sixth switch that is turned on when the differential voltage holding circuit inputs the aforementioned digital input signal. 1 3 · A liquid crystal display device, which belongs to a pixel having a pixel array portion formed on a transparent substrate, having pixel and electrode lines formed horizontally and vertically, and pixel electrodes arranged near the intersections of these lines An array section and a driving circuit formed on the transparent substrate and driving at least one of the signal line and the scanning line, and a liquid crystal display device having a driving circuit capable of converting a digital video signal into an analog video signal Its characteristic is that the aforementioned drive circuit inputs a digital input signal with an amplitude of a first width and amplifies the amplitude of the digital input signal as a digital output of a second width and an amplitude that is larger than the first width. Signal Xu_In the output signal amplification circuit, the signal with the amplitude of the first width is amplified, and the signal of amplitude is the signal with the amplitude of the second amplitude that is larger than the first width, as the digital output signal. The output logic circuit for amplitude amplification and the differential voltage with one end connected to the above-mentioned logic circuit for amplitude amplification Remarks ijlRx >-Binding · Binding · l · · This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) • 97- 5 8 6 7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs “A8” B8 C8 __ D8 > In the patent application range holding circuit, temporarily maintain the reference voltage of the high and low switching of the aforementioned digital input signal, and is slightly equal to the pre-switching logic of the high and low logic of the amplitude increase logic circuit When the differential voltage holding circuit that limits the differential voltage is set, and when the differential voltage to be held by the differential voltage holding circuit is set to the differential voltage holding circuit, the one end of the differential voltage holding circuit is set to be slightly When the threshold voltage setting circuit of the voltage equal to the threshold voltage of the amplitude increase logic circuit is set, and when the differential voltage 'to be held by the differential voltage holding circuit is set in the differential voltage holding circuit, the aforementioned The other end of the differential voltage holding circuit is set to a base where the logic of high and low of the aforementioned digital input signal is switched. The quasi-voltage reference voltage setting circuit and the differential voltage holding circuit hold the differential voltage, and then input a digital signal input circuit of the digital input signal to the other end of the differential voltage holding circuit. -…-· * 1 4. A load drive circuit is a load drive circuit that inputs an input signal of a predetermined voltage amplitude and supplies the voltage of the input signal to a signal line connected to the load. The voltage change circuit of the voltage, and the conduction between the aforementioned voltage change circuit and the aforementioned signal line — the first switch that is turned on / off, and when the input voltage is a predetermined threshold voltage, the output logic is reversed and controlled The logic circuit for closing / opening the first switch and the differential holding circuit that maintains a voltage slightly equal to the threshold voltage of the logic circuit and the differential voltage of the input signal, please read the note on the back before filling 訂 本紙張尺度適用中國國家標準（CNS ) A4规格（210><297公釐） -98 - 六、申請專利範圍 / (請先閲讀背面之注意事項再填 和將前述差分電壓.保持電路所欲保持之前述差分電壓 ’設定於前述差分電壓保持-電路之時，令前述差分電壓保 持電路的一端設定呈略等於前述邏輯電路之臨限値電壓的 電壓的臨限値電壓設定電路， .和將前述差分電壓保持電路所欲保持之前述差分電壓 ’設定於前述差分電壓保持電路之前，令前述差分電壓保 持電路之另一端設定於前述輸入信號之電壓的輸入電壓設 定電路者。 1 5 ·如申請專利範圍第1 4項之負荷驅動電路，其 中，前述差分電壓保持電路係具備一端連接於前述邏輯電 路，另一端連接於前述輸入電壓設定電路的第1電容器者 C . 1 6 ·如申請專利範圍第1 5項之負荷驅動電路，其 中， - —- 前述臨限値電壓設定電路係具備 一端連接於前述第1電容器之'前述另一端的第2電容 器， 經濟部智慧財產局員工消費合作社印製 和一端連接於前述第2電容器之另一端，另一端連接 於設定前述差分電壓時，自前述第1電壓向前述箄_2電壓 直線變化的反轉取消端子的第2開關中，於前述第1電容 器在設定前述差分電壓時呈開啓，前述第1電容器之前述 一端略等於前述振幅增幅用邏輯電路之’前述臨限値電壓的 電壓之時點呈關閉的第2開關， 和一端連接於前述第1電容器之前述一端’另一端連 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -99- 六、申請專利範圍 接於設定前述差分電壓時，自前述第2電壓向前述第2電 壓直線變化的取消端子的第《3開關中，於前述第1電容器 在設定前述差分電壓時呈開啓，前述第1電容器之前述一 端略等於前述振幅增幅用邏輯電路之前述臨限値電壓的電 壓之時點呈關閉的第3開關者。 · ' 1 7 ·如申請專利範圍第1 6項之負荷驅動電路，其 中’前述第2開關和前述第3開關係各具有p型MO S電 晶體和η型Μ〇S電晶體的轉換閘者。 1 8 ·如申請專利範圍第1 5項之負荷驅動電路，其 中’前述臨限値電壓設定電路係具備一端連接於前述第1 電谷益之則述另一端的第3電容器，和一端連接於前述第 1電容器之前述一端，另一端連接於前述第3電容器之另 一端的第4開關中，於前述第1電容器在設定前述差分電 壓時’該第3開關之前述一端則連接於第3電壓，該第3 開關之前述另一端則連接於第4電壓的同時，於前述第1 電容設定前述差分電壓之時呈開啓，前述第1電容器之前 述一端略等於前述振幅增幅用邏輯電路之前述臨限値電壓 的電壓之時點呈關閉的第4開關者。 1 9 ·如申請專利範圍第1 7項之負荷驅動電-路，其 中，前述第4開關係具有Ρ型Μ〇S電晶體和η型Μ〇S 電晶體的轉換閘者。 2 0 ·如申請專利範圍第1 6項之負荷驅動電路，其 中，更具備於前述第1電容器設定前述差分電壓之時，將 前述第1電容器之前述另一端之電壓維持於前述輸入信號 本紙張尺度適用中國國家標準（CNS ) Α4規格（21〇χ297兮釐）' (請先閱讀背面之注意事項再填* 百 ). 經濟部智慧財產局員工消費合作社印製 -100- 476854 A8 B8 C8 D8 、申請專利範固 經濟部智慧財產局員工消費合作社印製 之電壓的輸入電壓維持電路。 2 1 ·如申請專利範圍-第2 中’前述第2開關及第3開關係 和η型μ 0 s電晶體的轉換閘者 .2 2 ·如申請專利範圍第1 中’更具備於前述第1電容器設 前述第1電容器之前述另一端之 之電壓的輸入電壓維持電路。 2 3 ·如申請專利範圍第2 中’前述第4開關係具有ρ型Μ 電晶體的轉換閘者。· 2 4 ·如申請專利範圍第1 中’前述電壓變更電路係將前述 加以變化者。 2 5 ..如申請專利範圍第2 中，前述差分電壓保持電路係具 路之輸入端子，另一端連接於前 4電容器。' 2 6 ·如申請專利範圍第2 中，具備一端連接於前述第4電 0項之負荷驅動電路，其 各具有Ρ型Μ 0 S電晶體 ) 8項之負荷驅/動電路，其 定前述差分電壓之時，將 電壓維持於前述輸入信號 2項之負荷驅動電路，其 〇S電晶體和η型Μ〇S 4項之負荷驅動電路，其 信號線之電壓以一定比例 4項之負荷驅動i路，其 備一端連接於前述邏輯電 述輸入電壓設定電路的第 5項之負荷驅動羣J各，其 容器之前述另一端，另一 端連接於前述輸入信號之輸入端子的第5開關’ 將欲保持前述第4電容器之前述差分電壓設定於前述 第4電容器之時’前述第5開關呈開啓’前述第4電容器 之前述另一端則略等於前述輸入信號之電壓地加以設定者 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填Ϊ頁) Γ -101 - 476854 B8 C8 D8 、申請專利範圍 2 7 ·如申請專利範圔-第2 6項之負荷驅動電路，其 中， 前述臨限値電壓設定電路係具備連接於一端構成前述 邏輯電路之反轉增幅電路中之最前段之反轉增幅電路之輸 入端子’另一端連接於前述前段之反轉增幅電路之輸出端 子的第6開關， 3寸保持則述第4電容器之則述差分電壓設定於前述 第4電容器之時，前述第6開關呈開啓，前述第4電容器 之前述另一端則略等於前段之反轉增幅電路之臨限値電壓 地加以設定者。 2 8 ·如申請專利範圍第2 7項之負荷驅動電路，其 中’前述輸入信號之電壓振幅係自第5電壓至第6電壓之 間者。 2 9 ·如申請專利範圍第2 8項之負荷驅動電路，其 中，前述電壓變更電路係一端連接於前述第5電壓或第6 電壓之供給端子，另一端連接於前述第1開關之一端的定 電流電路者〇 3 〇 ·如申請專利範圍第2 9項之負荷驅動ttJ各，其 中，於將欲保持前述第4電容器之前述差分電壓設定於前 述第4電容器前之階段中，於構成前述邏輯電路的反轉增 幅電路之輸入端子，施加前述第5電壓或前述第6電壓者 〇 3 1 ·如申請專利範圍第3 〇 .項之負荷驅動電路’其 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填· ml - IK瓦 訂 經濟部智慧財產局員工消費合作社印製 -102- 六、申請專利範圍 中’更具備一端連接於.前述信號線，另一端連接於前述第 5電壓或前述第6電壓之電4壓源的第7開關的同時， (請先閲讀背面之注意事項再填9頁)* 前述第7開關憬於前述信號線供給前述輸入信號之電 壓之前’暫時呈開啓狀態，將信號線設定於前述第5電壓 或前述第6電壓者。·… 3 2 · —種液晶顯示裝置，屬於具有形成於透明基板 上之畫素陣列部中，具有縱橫地形成信號線及掃瞄線，列 設於此等各線之交點附近的畫素電極之畫素陣列部， 和形成於前述透明基板上，進行前述信號線之驅動的 信號線驅動電路 和形成於前述透明基板上，進行前述掃瞄線之驅動的 掃瞄線驅動電路的液晶顯示裝置中，其特徵係前述信號線 驅動電路係複數具備包含輸入所定之電壓振幅之輸入信號 ，將此輸入信號之電壓供予連接負荷之信號線的負荷驅動 電路中， 變更前述信號線之電壓之電壓變更電路， 經濟部智慧財產局員工消費合作社印製 和將前述電壓變更電路和前述信號線間之導通呈關閉 /開啓的第1開關， 和輸入電壓呈所定之臨限値電壓時，反轉輸出輯， 控制前述第1開關之關閉/開啓的邏輯電路， 和保持略等於前述邏輯電路之前述臨限値電壓的電壓 和前述輸入信號之電壓的差分電壓的差分保持電路， 和將前述差分電壓保持電路所欲保持之前述差分電壓 ，設定於前述差分電壓保持電路之時，令前述差分電壓保 本紙張尺度適用中國國家揉準（CNS ) A4規格（210X297公釐）' 一 -103- 476854 A8 B8 C8 D8 _ 六、申請專利範圍 (請先閱讀背面之注意事項再填寫本頁) 持電路的一端設定呈略等於前述邏輯電路之臨限値電壓的 電壓的臨限値電壓設定電路， 和將前述差分電壓保持電路所欲保持之前述差分電壓 ，設定於前述差分電壓保持電路之前，令前述差分電壓保· 持電路之另一端設定於前述輸入信號之電壓的輸入電壓設 定電路的負荷驅動電路者。 3 3 .如申請專利範圍第3 2項之液晶顯示裝置，.其 中，爲前述輸入影像信號之電壓於第1電壓和第2電壓間 加以振幅的信號，包含前述信號線驅動電路之複數前‘述負 荷電路中/具有 前述輸入影像信號之電壓爲前述第1電壓和前述第2 電壓中之高電壓側時，向前述信號線供給電壓的高壓側之 負荷驅動電路， 和前述輸入影像信號之電壓爲前述第1電壓和前述第· 2電壓中之低電壓側時，向前述信號線供給電壓的定壓側 之負荷驅動電路； 前述信號線驅動電路係具備 經濟部智慧財產局員工消費合作社印製 驅動前述第1負荷驅動電路和第2負荷驅動電路中之 一方地加以控制的切換控制電路者。 3 4 ·如申請專利範圍第3 3項之液晶顯示裝置，其 中，前述電壓變更電路係將前述信號線之電壓以一定比例 加以變化者。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -104-The size of the paper is applicable to the Chinese National Standard (CNS) A4 specification (210 > < 297 mm) -98-Sixth, the scope of patent application / (Please read the precautions on the back before filling and the aforementioned differential voltage. Hold the circuit When the aforementioned differential voltage to be held is set in the aforementioned differential voltage holding circuit, one end of the aforementioned differential voltage holding circuit is set to a threshold threshold voltage setting circuit which is slightly equal to a threshold threshold voltage of the aforementioned logic circuit, and An input voltage setting circuit that sets the differential voltage 'to be held by the differential voltage holding circuit before the differential voltage holding circuit, and sets the other end of the differential voltage holding circuit to the voltage of the input signal. 1 5 · 如The load driving circuit of the scope of patent application No. 14 in which the aforementioned differential voltage holding circuit is provided with a first capacitor C. 16 connected at one end to the aforementioned logic circuit and connected at the other end to the aforementioned input voltage setting circuit. The load driving circuit in the range of 15 items, where---the aforementioned threshold voltage setting The circuit is provided with a second capacitor connected at one end to the other end of the first capacitor, printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, and connected at one end to the other end of the second capacitor, and at the other end to set the differential voltage. At this time, in the second switch of the reverse cancellation terminal that changes linearly from the first voltage to the 箄 _2 voltage, the first capacitor is turned on when the differential voltage is set, and the one end of the first capacitor is slightly equal to the foregoing. The second switch which is closed at the time point of the voltage of the aforementioned threshold voltage of the logic circuit for amplitude amplification, and one end is connected to the aforementioned one end of the first capacitor, and the other end is connected to this paper. The Chinese standard (CNS) A4 specification applies. (210X297mm) -99- VI. When the patent application scope is set to the aforementioned differential voltage, the "3rd switch of the cancellation terminal that changes linearly from the aforementioned second voltage to the aforementioned second voltage, is set in the aforementioned first capacitor. The differential voltage is turned on, and the one end of the first capacitor is slightly equal to the logic circuit for amplitude increase. The third switch that is turned off at the time point of the aforementioned threshold voltage. · '1 7 · The load driving circuit according to item 16 of the patent application scope, wherein the aforementioned second switch and the aforementioned third open relationship each have p The switching gate of the MO MOS transistor and the η MOS transistor. 1 8 · For example, the load driving circuit of the 15th patent application scope, wherein the aforementioned threshold voltage setting circuit is provided with one end connected to the aforementioned 1 The third capacitor at the other end of Denki Masanori, and the fourth switch with one end connected to the first end of the first capacitor and the other end connected to the other end of the third capacitor, are set in the first capacitor. In the case of the differential voltage, 'the one end of the third switch is connected to the third voltage, and the other end of the third switch is connected to the fourth voltage, and it is turned on when the first capacitor sets the differential voltage. The one end of the first capacitor is slightly equal to the fourth switch that is turned off at the voltage point of the threshold voltage of the amplitude increase logic circuit. 19 • The load driving circuit of item 17 in the scope of patent application, wherein the aforementioned fourth open relationship has a switching gate of a P-type MOS transistor and an η-type MOS transistor. 2 0. The load driving circuit according to item 16 of the scope of patent application, which further includes maintaining the voltage at the other end of the first capacitor at the input signal when the first capacitor sets the differential voltage. Standards are applicable to China National Standard (CNS) Α4 specifications (21〇χ297 兮) (Please read the notes on the back before filling * hundred). Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -100- 476854 A8 B8 C8 D8 Application for patent: Fangu's input voltage maintenance circuit for the voltage printed by the Intellectual Property Bureau of the Ministry of Economic Affairs' employee consumer cooperatives. 2 1 · As in the scope of the patent application-the second switch of the aforementioned second switch and the third open relationship and the η-type μ 0 s transistor. 2 2 · As in the scope of the patent application-the first paragraph is more equipped in the aforementioned first The 1 capacitor is provided with an input voltage maintaining circuit for the voltage of the other end of the first capacitor. 2 3 · As described in the second of the scope of the patent application, the above-mentioned 4th switching relationship has a switch of p-type M transistor. · 2 4 · The aforementioned voltage change circuit is the one in which the aforementioned voltage change circuit is changed in the first patent application scope. 2 5 .. As in the second patent application, the aforementioned differential voltage holding circuit is an input terminal of the circuit, and the other end is connected to the first 4 capacitors. '2 6 · As in the second scope of the patent application, there is a load driving circuit with one end connected to the aforementioned item 4 electric 0, each of which has a P-type M 0 S transistor) of the item 8 load driving / driving circuit, which determines the foregoing At the time of differential voltage, the load driving circuit that maintains the voltage at the aforementioned two items of the input signal, the 0S transistor and the load driving circuit of the n-type MOS 4 item, the voltage of the signal line is driven by a certain proportion of the 4 item load In the i-channel, its one end is connected to each of the load driving group J of the fifth item of the aforementioned logic input voltage setting circuit, the other end of the container, and the other end is connected to the fifth switch of the input terminal of the aforementioned input signal. If the differential voltage of the fourth capacitor is to be set to the fourth capacitor, the aforementioned fifth switch is turned on. The other end of the fourth capacitor is set to be slightly equal to the voltage of the input signal. Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the notes on the back before filling in the title page) Γ -101-476854 B8 C8 D8, patent application scope 2 7 · If applied Please refer to the patent for the load driving circuit of item 26, in which the threshold voltage setting circuit is provided with an input terminal connected to one end of the inverting amplifier circuit of the inverting amplifier circuit that constitutes the foregoing logic circuit. When the other end is connected to the sixth switch of the output terminal of the inverting amplifier circuit of the preceding paragraph, when the 3-inch hold is set to the fourth capacitor, and the differential voltage is set to the fourth capacitor, the sixth switch is turned on, and the first 4 The other end of the capacitor is slightly equal to the threshold and voltage of the inverting amplifier circuit in the previous section. 2 8 · The load driving circuit according to item 27 of the scope of patent application, wherein the voltage amplitude of the aforementioned input signal is between the fifth voltage and the sixth voltage. 2 9 · The load driving circuit according to item 28 of the scope of patent application, wherein the voltage change circuit is connected at one end to the supply terminal of the fifth or sixth voltage, and at the other end is connected to one of the ends of the first switch. The current circuit 〇3 〇 · If the load range of the patent application No. 29 is to drive each of ttJ, in which the aforementioned differential voltage to maintain the aforementioned fourth capacitor is set before the aforementioned fourth capacitor, the aforementioned logic is constituted The input terminal of the inverting amplifier circuit of the circuit is the one who applies the aforementioned 5th voltage or the aforementioned 6th voltage. 0 1 1 · If the load driving circuit of the patent application No. 3 0. ', this paper size applies to the Chinese National Standard (CNS) A4 specification (210X297mm) (Please read the notes on the back before filling in ml-IK Wading printed by the Intellectual Property Bureau Employees Consumer Cooperatives of the Ministry of Economics -102- VI. In the scope of patent application, there is a connection at one end. The other end of the signal line is connected to the 7th switch of the 4th voltage source of the 5th or 6th voltage, (Please read the precautions on the back before filling 9 Page) * The aforementioned seventh switch is expected to be temporarily turned on before the aforementioned signal line supplies the voltage of the aforementioned input signal, and the signal line is set to the aforementioned fifth voltage or the aforementioned sixth voltage .... 3 2 · — a kind of liquid crystal display The device belongs to a pixel array section having a pixel array section formed on a transparent substrate, having pixel and electrode lines formed horizontally and vertically, and pixel electrodes arranged near the intersections of these lines, and formed in the foregoing The signal line driving circuit for driving the signal line on the transparent substrate and the liquid crystal display device formed on the transparent substrate and scanning line driving circuit for driving the scanning line are characterized in that the signal line driving circuit is It is a load driving circuit including a plurality of input signals including a predetermined voltage amplitude and supplying the voltage of the input signal to a signal line connected to a load. The voltage changing circuit for changing the voltage of the aforementioned signal line is consumed by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs. Cooperative printed and switched the first switch to turn on / off the conduction between the voltage change circuit and the signal line When the input voltage is at a predetermined threshold voltage, the output circuit is reversed, the logic circuit that controls the closing / opening of the first switch, and the voltage and the input signal that are slightly equal to the threshold voltage of the logic circuit are maintained. The differential voltage holding circuit of the differential voltage and the differential voltage to be held by the differential voltage holding circuit are set in the differential voltage holding circuit, so that the paper standard of the differential voltage maintenance is applicable to China National Standards (CNS) A4 specifications (210X297 mm) '-103-476854 A8 B8 C8 D8 _ VI. Patent application scope (please read the precautions on the back before filling this page) The setting of one end of the holding circuit is slightly equal to the threshold of the aforementioned logic circuit临 Threshold of voltage 値 Voltage setting circuit and the differential voltage to be held by the differential voltage holding circuit are set before the differential voltage holding circuit, so that the other end of the differential voltage holding circuit is set to the foregoing The load driver of the input voltage setting circuit of the input signal voltage. 33. The liquid crystal display device according to item 32 of the scope of the patent application, wherein the voltage of the aforementioned input image signal is a signal with an amplitude between the first voltage and the second voltage, including before the plural of the aforementioned signal line driving circuit. In the load circuit, when the voltage of the input video signal is the high voltage side of the first voltage and the second voltage, a load drive circuit on the high voltage side that supplies voltage to the signal line, and the voltage of the input video signal When it is the low voltage side of the first voltage and the second voltage, the load driving circuit on the constant voltage side that supplies voltage to the signal line; The signal line driving circuit is printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs A switching control circuit that drives one of the first load driving circuit and the second load driving circuit and controls them. 34. The liquid crystal display device according to item 33 of the scope of patent application, wherein the voltage change circuit is a device that changes the voltage of the signal line by a certain ratio. This paper size applies to China National Standard (CNS) A4 (210X297 mm) -104-
TW88119492A 1998-05-11 1999-11-08 Circuit for increasing signal amplitude, circuit for driving load and liquid crystal display apparatus TW476854B (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP12751298A JP4542633B2 (en) 1998-05-11 1998-05-11 Load drive circuit and liquid crystal display device
JP11031795A JP2000231089A (en) 1999-02-09 1999-02-09 Signal amplifier circuit and liquid crystal display device using the circuit
JP30595299A JP4535537B2 (en) 1999-10-27 1999-10-27 Load drive circuit and liquid crystal display device
JP30594299A JP4515563B2 (en) 1999-10-27 1999-10-27 Load drive circuit and liquid crystal display device

Publications (1)

Publication Number Publication Date
TW476854B true TW476854B (en) 2002-02-21

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TW88119492A TW476854B (en) 1998-05-11 1999-11-08 Circuit for increasing signal amplitude, circuit for driving load and liquid crystal display apparatus

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Country Link
TW (1) TW476854B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI386890B (en) * 2004-05-11 2013-02-21 Samsung Display Co Ltd Analog buffer, display device having the same, and method of driving the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI386890B (en) * 2004-05-11 2013-02-21 Samsung Display Co Ltd Analog buffer, display device having the same, and method of driving the same

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