JPS58186215A - High speed conparator circuit - Google Patents

Abstract

PURPOSE:To obtain a high speed comparator circuit, by using a pulse having a period shorter than that of the pulse controlling an offset voltage reduction circuit and decreasing the waiting time of a differential amplifier in comparison with a control pulse of a latch circuit. CONSTITUTION:A switch 10 is controlled with a control signal (a) from a control signal generator 70, and a control signal (b) is impressed to switches 11-13 via an inverter. Thus, an offset voltage of a differential amplifier 30 at the region I is stored in capacitors 20, 21, and the analog amplification of the input signal impressed to an input terinal 1 is performed at the region II. The time of the region II is made longer as twice as that of the region I . The signal analog- amplified is inputted to a latch circuit 31, where it is sampled and latched. A control signal (c) is impressed to the latch circuit 31, allowing to attain multiple sampling.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a high-speed comparator circuit consisting of a differential amplifier circuit and a latch circuit having an input offset voltage reduction circuit that reduces manual offset voltage by utilizing the voltage storage function of a capacitor. Conventionally, in this type of humparator circuit, the input offset voltage of the first-stage differential amplifier circuit determines the accuracy. Sometimes, the voltage stored in the capacitor is subtracted from the signal voltage, amplified, and input to the latch circuit, where the signal is latched.

Normally, the signal latching operation and the differential amplifier operation are performed in a complementary manner, and when the differential amplifier is in a standby state, the latch circuit operates, and No. 48 amplified in the previous cycle is latched. In such conventional comparator circuits, the pulse period of the control signal that controls the switch used to charge the offset voltage to the capacitor is the same as the pulse period of the control signal that controls the sub-circuit. As a result, the sampling period is determined by the speed of the offset voltage reduction circuit, and the drawback is that the high speed of the latch circuit cannot be utilized. In other words, increasing the capacitor's offset voltage charging time increases accuracy, but the drawback is that the sampling period is similarly long and high-speed performance is lost.If the sampling period is shortened to increase speed, the capacitor's offset This has the disadvantage that the voltage charging time has to be shortened and the accuracy decreases, making it impossible to obtain a high-speed and high-precision comparator circuit.

An object of the present invention is to use a short 171-cycle pulse voltage in the latch circuit for the pulse voltage that controls the offset voltage low-band circuit, It is possible to provide a high-speed and highly accurate comparator circuit by making the period sufficiently long compared to the voltage period.

According to the present invention, there is provided a differential amplifier circuit having a manual offset voltage reduction circuit for reducing the input voltage of a DC restorer circuit using capacitive coupling, and a latch whose output from the differential amplifier circuit is manually powered. circuit, a control signal generating circuit for generating a first control signal for controlling the differential amplifier circuit so that the operating time is at least twice as long as the standby time, and the latch circuit. A second control No. 1- generation circuit that generates a second trit+m signal having a shorter period than the control signal of the control signal Ayu I and the differential amplifier circuit are connected to the differential amplifier circuit.
1 characterized in that it has a status signal generation circuit that notifies the outside whether it is in a state of failure or in an operating state.
A terror speed comparator circuit can be provided.

Next, the present invention will be explained using figures.

FIG. 1 is a schematic diagram of a conventional humpator circuit. An IK signal voltage is applied to the input terminal 2, and a reference voltage is applied to the input terminal 2. The switch 10 is shown in FIG.
It is controlled by a pulse voltage φ generated in the time domain, and is turned on during time domain IO and turned off when time domain noise is generated. switch 11
．． 12.13 is injected with a pulse voltage φ shown in Fig. 2 (-). The state of the switch shown in Fig. 1 shows the state between regions. The input terminals of the differential amplifier 30 are short-circuited by the switch ]l, and a reference voltage is applied.At this time, the offset voltage of the differential amplifier 30 appears as a voltage difference at the output terminals 40.41.The switch 12.13 The voltage at the small output terminals 40 and 41 that are turned on is charged to the capacitors 20 and 21. Information regarding the offset voltage is also
0 and 21 as a voltage difference.

The latch circuit 31 is in a standby state in region 1 because a control signal φ indicated by - is applied to the terminal 501C in FIG. The output signal is outputted from the output terminal 3 in the region -.

In this conventional circuit, V has a capacity of 20 which determines the speed and accuracy.
.
In the opposite case, the speed increases but the accuracy decreases, making it impossible to have the two characteristics of 76 speed and high accuracy at the same time.

FIG. 3 is a schematic diagram of a comparator circuit according to the present invention. The switch IO connects the amm signal half 47 via the wiring 60.
Controlled by 0. The control signal generator 70 generates a control signal such as aJo in FIG. Delivery @61
The control signal *m is applied via.

The control signals applied are shown in FIG.

In region 1, these switches are on; in region 2, they are open. As can be seen from these relationships, the offset voltage of the differential amplifier 30 in region I is equal to the capacitor 20.2.
1K storage and analog multiplication of the input signal between regions. Area I! Set to obtain the required accuracy, taking into consideration the degree of charging required.

The region II can be made long as long as the information described above regarding the offset voltage stored in the capacitor 20, 2iK maintains the required accuracy. Usually, when such a circuit is integrated, the p-n! I! Although information is lost due to leakage current in the case of the circuit, it is generally very small, so region 1 can be made extremely large compared to the region IK. The resolution is shorter than Area 1; it needs to be at least twice as long.

The analog amplified signal in the region - is input to the latch circuit 14=531 from the terminal 42.43 and sampled.
Latched. A control signal as shown in FIG. 4(C) is generated from the control tξ signal generation circuit 71 to the latch circuit 31,
The voltage is applied via the wiring 50. The latch time wr31 is usually fast and tough iη uJ , 112 /, c G
'i allows you to sample multiple times at Cheoseongguchi.

In Figure 4 fc), 4 +1. Since the final pulse of the latch 'i' is output, by sampling 4F, it is possible to sample the number of times according to the operating speed of the latch circuit generally used. By the way,
Output terminals 'f-3t' of the latch circuit 31 also produce an output in region 1, but since this is meaningless, it is necessary to teach the external circuit to iterate the output of region 1. This waste signal is transmitted through the buffer 81 in FIG. 4 (bJ
It is sufficient to output No. 1d of the terminal Jffi as output 17.As is clear from the above explanation, in the humpator circuit according to the present invention, the control signal for sampling and latch is generated independently of the control signal for reducing the offset voltage. Since this signal is applied to the latch circuit, sampling can be performed at high speed without damaging the required Mlf, that is, a high-speed humparator can be obtained.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of a conventional comparator circuit.
is a differential amplifier ma, 20.21 is a coupling capacitance, 31 is a latch circuit, 10.11.12.13 is a switch circuit, which is a schematic diagram of a comparator circuit according to the invention, 30 is a differential amplifier a, 31 is a latch circuit, 7071 is a control signal generation circuit 11, a leap is an inverter circuit, and 81 is a buffer circuit. Figure l114 ((transfer), (bl.) (C) shows the high-speed comparator 3 of the present invention shown in Figure 3.
In the figure, l is a signal input terminal, 2 is a reference voltage input terminal,
3 is output end F, 40.41.42.43.60.61
4 is a wiring, and 4 is a status signal output terminal. Figure 1 t Figure 2 Figure 3

Claims (1)

[Claims] A differential amplifier circuit having an input offset voltage reduction circuit that reduces an input offset voltage using a DC restorer circuit by capacitor 1it coupling, a latch circuit that uses the output of the differential amplifier circuit as human power, and the differential amplifier circuit. The operating time is less than the standby time (both are more than twice as long)
! The first it to do! A second control signal having a shorter period of time than the first control signal which controls the first control i# signal generation circuit which generates the 1lili signal and the first control signal control circuit. M
The differential amplifier circuit is characterized by comprising a 2-1 signal generation circuit that generates a J signal, and a status note generation circuit that informs the outside whether the differential amplifier circuit is in a standby state or an operating state. LA, fiSI records 2 pieces 1.