JP3468502B2 - comparator - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to first and second input means to which two voltages to be compared are input, the input voltage, and an inverted voltage of the input voltage, which are amplified and output. And a comparator having amplification means for
In particular, it relates to a comparator having a highly accurate comparison function for voltage.

[0002]

2. Description of the Related Art Conventionally, in a comparator using a switched capacitor circuit, in a voltage comparator of an analog-digital converter for converting an analog input signal into a digital signal, whether the analog input voltage is higher than a designated reference voltage, It is used as a circuit to determine if it is low. There is a demand for higher accuracy in the comparison between the reference voltage of the comparator and the analog input voltage, and various means for solving the problems relating to this have been proposed so far.

As an example of a conventional comparator, its circuit configuration is shown in FIG. The circuit of this comparator is provided with an input terminal of an analog input voltage (or a reference voltage, here an analog input voltage) VIN1 and an input terminal of a comparison reference voltage (or an analog input voltage, here a comparison reference voltage) VIN2. The inputs are connected to the capacitors C1 and C2 via SW (switch circuits) 1 and 2, respectively, and the outputs of the SW1 and 2 are connected via SW3,
The outputs from the capacitors C1 and C2 are input to INVs (inverters) 1 and 2 in which SW7 and 8 are connected to the input and output ends, and the outputs of these INV1 and INV2 are INV1 and INV2, respectively.
Output terminal of INV via SW9 and SW10 respectively
2. The positive circulating circuit configured by being connected to the input terminal of INV1 is further inverted and amplified to the logic voltage level, and the output logical value is latched by the SR latch of the next stage, and the comparator is operating. This logical value does not change.

The operation of this circuit will be described with reference to the timing chart shown in FIG. When the timing CLK1 input to SW1 and SW2 is high, SW1 and SW2
Closes and opens during the low period. Further, at the same timing as the timing CLK1 input to SW1 and SW2, SW4,
SW4 and SW5 are closed while the timing CLK2 input to S5 is high and open during a low period. SW3 is closed during the period when the timing CLK3 input to SW3 is high and opened during the period when it is low. SW9 and 10 are closed while the timing CLK4 input to SW9 and 10 is high, and opened during the period of low.

Although the above operation is repeated, the sampling mode is set during the period in which the timing CLK2 (CLK1) is high. During the period of this sampling mode, SW7 and SW8 are closed and are in the ON state, and therefore INV1 and INV2 are passed through SW7 and SW8.
Each input and output are short-circuited, INV1, INV2
Operating point voltages VX1 and VX2 are output. Also, during this period, SW1 and SW2 are closed and are in the ON state, so that the analog input voltage VIN that is the two voltages to be compared is used.
1 and the reference comparison voltage VIN2 are input. At this time, the analog input voltage VIN1 is applied to the input terminal of the capacitor C1 and the reference comparison voltage VIN2 is applied to the input terminal of the capacitor C2. Therefore, the capacitance C1 samples the difference voltage between VIN1 and VX1, and the capacitance C2 samples the difference voltage between VIN2 and VX2.

Next, the timing CLK2 (CLK1) input to SW7, 8 (SW1, 2) becomes low,
The period in which the timing CLK3 input to SW3 is high is set to the amplification mode. During this amplification mode period, SW4, which was in the ON state in the sampling mode,
5 and SW1, 2 are opened and turned off, and SW3
Is closed and turned on, the VI of the capacitors C1 and C2
The input terminal side of N is short-circuited, and the charges stored in the capacitors C1 and C2 are redistributed. Then, at this time, the potential fluctuation generated on the output terminal side of INV1 and 2 of the capacitors C1 and C2 is
Input 1 and 2.

Therefore, for example, if VIN1> VIN2, the potential of the terminal of the capacitor C1 on the INV1 side decreases, and conversely, the potential of the terminal of the capacitor C2 on the INV2 side increases, so that the output potential of INV1 rises. The output potential drops.

After that, the timing CLK4 input to SW9, 10 becomes high, but during this period, SW9, 10 are closed and turned on, and INV1
The positive feedback circuit is configured by INV1 and INV2 by connecting the output terminal of INV2 to the input terminal of INV2 and the output terminal of INV2 to the input terminal of INV2. As a result, positive feedback is applied to the output voltages of INV1 and INV2, and the output voltages of INV1 and INV2 are rapidly amplified.

The output voltage from INV1, 2 amplified by the positive feedback circuit composed of INV1 and INV2 is the INV of the next stage.
It is inverted and amplified to the logic voltage level by 3 and 4, and the logic value that becomes the output is latched by the SR latch of the next stage,
The output value of the comparator does not change during the operation of the comparator.

The above conventional comparator solves the problem caused by the fluctuation of the operating point voltage of the inverter caused by the fluctuation of the power supply voltage supplied to the comparator due to noise or the like in the comparison between the reference voltage and the analog input voltage. It is supposed to be possible.

This is because the positive feedback circuit composed of INV1 and INV2 amplifies the output voltage of INV1 and INV2 sufficiently large so that the operation point voltage in the sampling mode caused by noise of the power supply voltage or the like operates in other periods. Even when the fluctuation of the point voltage becomes larger than the difference voltage between the analog input voltage and the comparison reference voltage, INV
This is because the vertical relationship between the output voltage of 1 and the output voltage of INV2 does not change, and the output of the positive feedback circuit composed of INV1 and INV2 does not invert.

[0012]

However, there are other problems relating to the accuracy of comparison between the reference voltage and the analog input voltage in the comparator, and the inverter amplifier and switch circuit in the comparator have gate capacitance and parasitic capacitance. The value is set to a value sufficiently smaller than the sampling capacity of the capacitor, but the gate capacity and parasitic capacity of the capacitor also affect the potential difference transmitted to the gate of the inverter amplifier.

The voltage V input from the input terminal shown in FIG.
If the change in the voltage of IN is ΔVIN and the change in VOUT output from the output terminal at that time is ΔVOUT, then ΔVOUT = CIN / (CIN + COUT) × ΔVIN, and due to the influence of parasitic capacitance such as gate capacitance, COU
No matter how small T is, in the conventional circuit, ΔVOUT <input differential voltage (= ΔVIN).

Explaining using the above conventional chopper type comparator, first, in the sampling mode,
The operating point voltage VX1 of INV1 obtained by short-circuiting the output terminal and the input terminal of INV1 by closing SW7 and turning on the input terminal of INV1, and SW1 being closed and turned on, the capacitance C1
Difference voltage VIN1 from VIN1 applied to the input terminal side of
If −VX1 is sampled in C1 and the charge stored in C1 is Q1, then Q1 = (VIN1-VX1) C1.

At the same time, on the other hand, in the sampling mode, SW8 is closed and turned on, and the operating point voltage VX2 of INV2 obtained by short-circuiting the output terminal and the input terminal of INV2 and SW2 are closed and turned on, and the capacitance C2
Difference voltage VIN2 from VIN2 applied to the input terminal side of
If −VX2 is sampled by C2 and the charge stored in C2 is Q2, then Q2 = (VIN2-VX2) C2.

Next, during the amplification mode period, the SW
Since 1 and SW2 are opened and turned off and SW3 is closed and turned on, the charges Q1 and Q2 stored in C1 and C2 during the sampling mode are redistributed. When the charge accumulated in C1 and C2 after being redistributed is Q, Q = Q1-Q2 Therefore, the voltage V applied between the input terminals of the inverters 1 and 2
Is C1 = C2 = C, Q = C ((VIN1-VX1)-(VIN2-VX2)) V = (VIN1-VX1)-(VIN2-VX2) where the inverters 1 and 2 are actually Even if the shape is the same, the operating point voltages are not exactly equal because they are affected by manufacturing variations, but if they are made equal for convenience, VX1 =
From VX2, V = VIN1-VIN2.

During the amplification mode period, the inverter amplifier IN
The voltage difference between VX1 and VX2 between the input terminals of V1 and INV2 is ideally (VIN1-VIN2), but in an actual circuit, the charge is distributed to the gate capacitance of the inverter, the parasitic capacitance of SW, etc. As the difference voltage, the difference voltage <(VIN1-VIN2), which deteriorates the accuracy of the comparator.

The present invention has been made in view of the above problems, and by adding a circuit using a switch and a capacitor, the voltage applied between the input terminals of INV1 and INV2 is actually added by this added circuit. Since it is twice the difference voltage of
Provide a comparator with higher precision comparison function, avoiding deterioration of precision in comparison function caused by difference voltage input to two inverters being less than actual difference voltage due to influence of parasitic capacitance in actual device The purpose is to

[0019]

In order to achieve such an object, the invention according to claim 1 in the present invention is compared.
First and second input means for receiving two voltages, and
1 and a second inverter, including the first inverter
Input the output to the second inverter,
By inputting the output to the first inverter, the first and second
With an amplifier that amplifies the voltage input to the inverter
In the comparator, the means for outputting the voltage to the amplifying means includes the input terminal of the first input means and the first inverter.
The input voltage of the first inverter , which is connected to the input terminal of
First operating point voltage and a first capacitor for sampling the differential voltage between the voltage input by the first input means is, connected to the input terminal and the input terminal of the second inverter of the second input means is a second capacitor for sampling the differential voltage of the voltage and entered in the second dynamic <br/> operation point voltage is a second inverter input voltage and the second input means, both ends first A third capacitor connected to the input terminal of the second input means and sampling a difference voltage between the voltage input by the first input means and the voltage input by the second input means, , Second, third
When the capacitance of 1 is short-circuited, the voltage input by the first input means and the voltage input by the second input means between the terminal on the amplification means side of the first capacitance and the terminal on the amplification means side of the second capacitance It is characterized in that a voltage obtained by doubling the difference voltage of 2 appears.

According to a second aspect of the present invention, in the first aspect of the invention, the means for outputting the voltage to the amplifying means connects the first input means and the first capacitor, and A first switch circuit for turning on / off the input to the first capacitance, a second input means and the second capacitance are connected,
Turn on the input from the second input means to the second capacitor
A second switch circuit for turning on / off, a third switch circuit for connecting the first input means and one end of the third capacitor, and turning on / off the input from the first input means, The second input means and the other end of the third capacitor are connected to turn on / off the input from the second input means.
Connecting a fourth switch circuit, an output end of the first switch circuit and an output end of the fourth switch circuit,
A short circuit between the first capacitance and the third capacitance is turned on / off.
The fifth switch circuit that performs F, the output end of the second switch circuit and the output end of the third switch circuit are connected to turn on / off the short circuit between the second capacitance and the third capacitance.
A sixth switch circuit that is turned off, and the first, second, third, fourth, fifth, and sixth switch circuits operate at a predetermined timing, so that the first capacitance amplifying means side terminal and said amplifying means side of said second capacitor
A voltage that doubles the difference voltage between the voltage input by the first input means and the voltage input by the second input means appears between the terminal and the terminal .

[0021] According to a third aspect, the invention of claim 2 wherein the first, second, third, fourth, fifth, predetermined timing switch circuit of the sixth to work, first, The first, second, third, and fourth switch circuits are turned on, and the first, second, third, and fourth switch circuits are turned from the on state to the off state, and then the fifth, It is characterized in that the sixth switch circuit is turned on.

According to a fourth aspect of the present invention, in the third aspect of the invention, the amplifying means includes a ninth switch circuit for connecting the output terminal of the first inverter and the input terminal of the second inverter, The positive feedback circuit has a tenth switch circuit that connects the output terminal of the second inverter and the input terminal of the first inverter, and the ninth and tenth switch circuits operate at predetermined timings. It is characterized by turning on / off the positive feedback operation by the.

[0023] According to a fifth aspect, in the invention of claim 4, wherein the predetermined timing ninth, tenth switch circuit operates, the fifth switch circuit of the sixth becomes the ON state Then, the 9th and 10th switch circuits are both turned on.
It is characterized by being in the N state.

According to a sixth aspect of the invention, in the invention according to any one of the first to fifth aspects, the amplifying means is the first.
Connecting an output terminal and an input terminal of the second inverter, and connecting a seventh switch circuit for turning on / off a short circuit between the connected output terminal and the input terminal, and connecting an output terminal and an input terminal of the second inverter And an eighth switch circuit for turning on / off a short circuit between the connected output terminal and input terminal, wherein the seventh and eighth switch circuits operate at predetermined timings to cause the first switch to operate . And obtaining the second operating point voltage.

According to a seventh aspect of the invention, in the sixth aspect of the invention, the predetermined timings at which the seventh and eighth switch circuits operate are in the first, second, third and fourth switch circuits. At the same time as the ON / OFF operation timing,
The seventh and eighth switch circuits are both turned on / off.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing a configuration example of an embodiment of a comparator according to the present invention. According to FIG. 1, the circuit of the comparator according to the present invention comprises an input terminal of an analog input voltage (or a reference voltage, here an analog input voltage) VIN1 and a comparison reference voltage (or an analog input voltage, here a comparison reference voltage). Yes) V
SW each one input from the input terminal of IN2
(Switch circuits) 1 and 2 are connected to the capacitors C1 and C2, the outputs of the respective SW1 and 2 are connected via SW5, C3 and SW6, and the other of the input terminals of the VIN1 and VIN2 is connected. The input is connected to the capacitor C3 via SW3 and SW4, respectively.

The outputs from the capacitors C1 and C2 are S
W7 and SW8 are input to INVs (inverters) 1 and 2 having input and output ends connected to them, and inputs to INVs 1 and 2 are input to INVs 1 and 2 via SWs 10 and 9, respectively. The output of INV1 and INV2 is further amplified to the logic voltage level by INV3 and INV2 by the inverting amplification which is rapidly performed by the positive circulation circuit configured by being connected to the ends. The output logical value is latched by an SR latch composed of a NAND gate in the next stage, so that the logical value does not change during the operation of the comparator.

The operation of this circuit will be described with reference to the timing chart of FIG. While the timing CLK1 input to SW1 and SW2 is high, SW1, SW2, and S
W3 and SW4 are closed and opened during the low period. Also, SW
Timing C input to 1, SW2, SW3, SW4
SW7 and SW8 are input while the timing CLK2 input to SW7 and SW8 is high at the same timing as LK1.
Closes and opens during the low period. While the timing CLK3 input to SW5 and SW6 is high, SW5 and S
W6 closes and opens during the low period. SW is input while the timing CLK4 input to SW9 and SW10 is high.
9. SW10 closes and opens during the low period.

The above operation is repeated, but the period in which the timing CLK2 (CLK1) is high in this operation is set to the sampling mode. During the period of this sampling mode, SW7 and SW8 are closed and are in the ON state, and therefore INV1 and INV2 are passed through SW7 and SW8.
Each input and output are short-circuited, INV1, INV2
The operating point voltages VX1 and VX2 that enable the operation are output.
Also, during this period, SW1, SW2, SW3, SW
Since 4 is closed and in the ON state, two voltages to be compared, the analog input voltage VIN1 and the reference comparison voltage VIN
2 and the analog input voltage VIN1 at this time
Is applied to the input terminal of the capacitor C1 and the reference comparison voltage VIN
2 is applied to the input terminal of the capacitor C2. Therefore, the capacity C
1 is the voltage difference between VIN1 and VX1, and C2 is VIN
The difference voltage between 2 and VX2 is sampled.

Further, in the present invention, during the sampling mode, the input voltages VIN1 and VIN2 are set to SW3,
It is applied to C3 via SW4, and the capacitance C3 samples the difference voltage between VIN1 and VIN2.

Next, SW7, 8 (SW1, 2, 3, 4)
CLK2 (CLK1) input to
And timing CLK input to SW5 and SW6
The period in which 3 becomes high is set to the amplification mode. In the period of this amplification mode, SW7, SW8 and SW1, SW2, SW3, which were in the ON state in the sampling mode,
Since SW4 is opened and turned off, and SW5 and SW6 are closed and turned on, the input voltage terminal side of the capacitors C1 and C2 and the capacitor C3 are short-circuited, and the charges stored in the capacitors C1, C2, and C3 are stored. Redistribute. And at this time, the capacity C
The potential fluctuations occurring on the input terminal side of INV1 and INV2 of C1 and C2 are input to INV1 and INV2.

After that, the timing CLK4 input to SW9 and SW10 becomes high, but during this period, SW9 and SW10 are closed and turned on, and I
By connecting the output terminal of NV1 to the input terminal of INV2 and the output terminal of INV2 to the input terminal of INV2, IN
A positive feedback circuit is composed of V1 and INV2. This result IN
Positive feedback is applied to the output voltage of V1 and INV2,
The output voltage of 1 and 2 is rapidly amplified.

The output voltage from INV1 and INV2 amplified by the positive feedback circuit composed of INV1 and INV2 is inverted and amplified to the logical voltage level by INV3 and INV4 of the next stage, and the logical value to be output is SR of the next stage. It is latched by the latch so that the output value of the comparator does not change during the operation of the comparator.

By the above operation of the comparator according to the present invention, the capacitance in the circuit and the differential voltage input to the inverter are as follows.

First, in the sampling mode, SW
7 is closed and turned on, and the operating point voltage VX1 of INV1 obtained by short-circuiting the output terminal and input terminal of INV1 and SW1 are closed and turned on, and are applied to the input terminal side of the capacitor C1. Voltage difference with VIN1 (V
If IN1-VX1) is applied to C1 and the charge stored in C1 is Q1, then Q1 = (VIN1-VX1) C1.

On the other hand, in the sampling mode, the SW8 is closed to be in the ON state, and the INV2 obtained by short-circuiting the output terminal and the input terminal of the INV2 is obtained.
The differential voltage (VIN2-VX2) between the operating point voltage VX2 of No. 2 and the ON state by closing SW2 and applied to the input terminal side of the capacitor C2 is applied to C2, and the electric charge stored in C2 is Q2. Then, Q2 = (VIN2-VX2) C2.

Further, in the present invention, in the sampling mode, SW3 and SW4 are closed to be in the ON state, and the capacitance C3 has a difference voltage (VIN) between the input voltages VIN1 and VIN2.
1-VIN2) is sampled and the charge stored in C3 is Q3, then Q3 = (VIN1-VIN2) C3.

Next, during the amplification mode period, SW
Since 1, SW2, SW3, and SW4 are open and in the OFF state, and SW5 and SW6 are closed and are in the ON state, the charges Q1, Q2, and Q3 stored in C1, C2, and C3 during the sampling mode period are Redistributed. If the charge accumulated in C1, C2, and C3 after being redistributed is Q, then Q = Q1-Q2 + Q3 Therefore, the voltage V applied between the input terminals of the inverters 1 and 2
Is C1 = C2 = C3 = C, Q = C ((VIN1-VX1)-(VIN2-VX2) +
(VIN1-VIN2)) V = (VIN1-VX1)-(VIN2-VX2) + (VI
N1-VIN2) Here, even if the inverters 1 and 2 have the same shape, they are affected by manufacturing variations and the like, so that the operating point voltages are not exactly equal, but if they are equal, VX1 =
From VX2, V = 2 (VIN1-VIN2).

From the above results, the differential voltage appearing in the conventional circuit can be doubled. Therefore, the accuracy as a comparator can be improved and a highly accurate comparator can be realized.

That is, assuming that the voltage change of the voltage VIN input from the input terminal shown in FIG. 4 is ΔVIN and the change of VOUT output from the output terminal at that time is ΔVOUT, ΔVOUT = CIN / (CIN + COUT) × ΔVIN, and due to the influence of parasitic capacitance such as gate capacitance, COU
In the conventional circuit, no matter how small T is, ΔVOUT <input difference voltage (= ΔVIN), but since the difference voltage applied to the sampling capacitor in the comparator according to the present invention is 2 × ΔVIN, ΔVOUT = CIN / (CIN + COUT) × 2 × ΔV
It becomes IN, and ΔVOUT> input difference voltage (= ΔVIN).

FIG. 4 shows the results of the difference potential appearing at the gates of INV1 and INV2 in the amplification mode of the comparator of the present invention and the difference potential appearing at the gates of INV1 and INV2 in the amplification mode of the comparator of the prior art. There is.

It is assumed that the difference between the input voltages from the two input terminals in the comparator of the present invention and the prior art, that is, the input difference voltage is 2 mV, and I is actually in the amplification mode.
The differential potential appearing at the gates of NV1 and INV2 is 1.86 mV in the prior art, which is lower than the input differential voltage of 2 mV, whereas it is 3.27 mV in the present invention, which is the input differential voltage. 2 mV above.

[0044]

As is apparent from the above description, according to the present invention, by adding a circuit using a switch and a capacitor, the input differential voltage applied to the comparator is theoretically 2 compared to the conventional circuit. It is possible to apply double voltage,
It is possible to provide a comparator that realizes higher determination accuracy.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration in an embodiment of a comparator according to the present invention.

FIG. 2 is an example of a timing chart of a clock signal input to each switch circuit of the present invention and the prior art.

FIG. 3 is a diagram for explaining the influence on the inverter amplifier due to the gate capacitance and parasitic capacitance of the inverter amplifier and the switch circuit.

FIG. 4 is a diagram showing a result of a difference potential appearing at gates of INV1 and INV2 in an amplification mode in the comparator of the present invention and the prior art.

FIG. 5 is a circuit diagram showing an example of a conventional comparator.

[Explanation of symbols]

SW1 to SW7 switch circuit C1, C2 capacity INV1 to INV4 inverter

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03M 1/00 H03K 5/08

Claims (7)

(57) [Claims] 1. A first and a second voltages to which two voltages to be compared are input.
And second input means and first and second inverters.
The output of the first inverter to the second inverter.
To the first inverter, and the output of the second inverter is input to the first inverter.
By inputting to the inverter, the first and second inverters are
The amplifier having an amplifying means for amplifying the voltage input by the controller.
In the palator, the means for outputting a voltage to the amplifying means includes an input terminal of the first input means and the first inverter.
Input terminal of the first inverter connected to
A first capacitance for sampling a difference voltage between a first operating point voltage which is a voltage and a voltage input by the first input means, an input terminal of the second input means, and the second inverter
Input of the second inverter connected to the input terminal of
A second capacitor for sampling a difference voltage between a second operating point voltage, which is a voltage, and a voltage input by the second input means, and both ends thereof are connected to input terminals of the first and second input means. , A third capacitor for sampling a difference voltage between the voltage input by the first input means and the voltage input by the second input means, the first, second, and third capacitors being provided. When short-circuited, the first
A difference voltage between the voltage input by the first input means and the voltage input by the second input means between the terminal on the side of the amplification means and the terminal on the side of the amplification means of the second capacitance. Two
A comparator characterized by the appearance of doubled voltage . 2. A means for outputting a voltage to the amplifying means connects the first input means and the first capacitance, and turns on an input from the first input means to the first capacitance. / O
An FF first switch circuit is connected to the second input means and the second capacitance, and an input from the second input means to the second capacitance is turned ON / O.
A second switch circuit that performs FF; a third switch circuit that connects the first input unit and one end of the third capacitor and turns ON / OFF the input from the first input unit; A fourth switch circuit for connecting the second input means and the other end of the third capacitor to turn on / off the input from the second input means; and an output end of the first switch circuit. A fifth switch circuit which is connected to the output end of the fourth switch circuit and turns ON / OFF the short circuit between the first capacitance and the third capacitance; and an output end of the second switch circuit. A sixth switch circuit which is connected to the output end of the third switch circuit and which turns on / off a short circuit between the second capacitor and the third capacitor; The third, fourth, fifth, and sixth switch circuits can operate at predetermined timing. Accordingly, the first
The difference between the voltage input at said voltage input at the first input means a second input means between the amplifying means side terminal and said amplifying means side terminal of said second capacitance of the capacitor of comparator according to claim 1, characterized in that the voltage twice the voltage appearing. 3. The predetermined timing at which the first, second, third, fourth, fifth, and sixth switch circuits operate is as follows: first, the first, second, third, and fourth switches. O circuit
After setting the N state and turning the first, second, third, and fourth switch circuits from the ON state to the OFF state,
The comparator according to claim 2 , wherein the fifth and sixth switch circuits are turned on. 4. The amplifier means includes a ninth switch circuit connecting an output terminal of the first inverter and an input terminal of the second inverter, an output terminal of the second inverter and the first switch circuit. ON / OFF of the positive feedback operation by the positive feedback circuit by operating the ninth and tenth switch circuits at a predetermined timing. The comparator according to claim 3, wherein: 5. The predetermined timing at which the ninth and tenth switch circuits operate is set so that the ninth and tenth switch circuits are turned on after the fifth and sixth switch circuits are turned on. 5. The comparator according to claim 4 , wherein both are turned on. 6. The amplifying means connects an output terminal and an input terminal of the first inverter and turns on / off a short circuit between the connected output terminal and the input terminal.
A seventh switch circuit that is turned off is connected to an output terminal and an input terminal of the second inverter, and a short circuit between the connected output terminal and the input terminal is turned on / off.
An eighth switch circuit that is turned off, and the seventh and eighth switch circuits operate at predetermined timings to cause the first and second switch circuits to operate .
Comparator claimed in any one of claims 5, characterized in that to obtain the operating point voltage. 7. The predetermined timing at which the seventh and eighth switch circuits operate is O in the first, second, third and fourth switch circuits.
7. The comparator according to claim 6 , wherein both the seventh and eighth switch circuits are turned ON / OFF at the same time as the N / OFF operation timing.