RU2018980C1 - Analog memorizing unit - Google Patents

Abstract

FIELD: test equipment. SUBSTANCE: opposite sign additive error is supplied to output voltage circuit to compensate the error completely. Compensation of additive error permits to reduce capacitance of store capacitors and to improve speed of operation of the device. Device has the first and the second analog commutators, sample-store units, memorizing capacitors, control unit, analog switches, buffer amplifier. EFFECT: improved precision; improved stability; improved speed of operation. 5 dwg

Description

 The invention relates to instrumentation and can be used in devices for processing or converting analog information.

 Known analog storage device [1], containing two sampling and storage devices on specialized integrated circuits, analog keys, a buffer amplifier and a control unit.

 The known device has a large additive error, which does not allow its use in the ADC of high accuracy. In addition, the additive error has a large temperature drift, which makes it difficult to use it as part of equipment operating in a wide temperature range.

 The purpose of the invention is to improve the accuracy, stability and speed of the device.

 The goal is achieved by the fact that the third and fourth analog keys, the first and second storage elements on the capacitors, the first information input are introduced into the known analog storage device containing a control unit, first and second blocks of sampling and storage, the first and second analog keys and a buffer amplifier the third analog key is the information input of the device, the second information input of the third analog key is connected to the zero potential bus, and the output is connected to the information inputs of the first о and the second sampling and storage units, the outputs of which are connected to the first plates of the first and second capacitors, respectively, the second plates of the capacitors are connected to the information inputs of the first and second analog keys, respectively, to the first and second information inputs of the fourth analog key, the output of which is connected to the input of the buffer amplifier, the output of which is the output of the device, the outputs of the first and second analog keys are connected to the zero potential bus, and the control inputs are connected to the first m and second outputs of control unit, third and fourth outputs of which are connected to the control inputs of the third and fourth analog switches respectively, the fifth and sixth outputs of the control unit connected to inputs of the sampling resolution of the first and second sample and hold blocks.

 Figure 1 presents a block diagram of an analog storage device; in FIG. 2 is a timing diagram of the operation of the device; figure 3 is an example implementation of a control unit; figure 4 is a timing diagram of the operation of the control unit; figure 5 is a coding table of ROM.

 The analog storage device contains a third analog key 1, a first sampling and storage unit (BVX) 2, a control unit 3, a second sampling and storage unit (BVX) 4, the first and second memory elements on the capacitors 5 and 6, the first and second analog keys 7 and 8, a fourth analog switch 9 and a buffer amplifier 10.

 As BVH 2 and 4, specialized ICs of the KR1100SK2 type were used [2].

 The control unit 3 is an integral part of the control unit of the analog information processing system, which includes the proposed device. In addition to signals A, B, C, D, E, and F, it also generates control signals for other system units (not shown in the diagram).

 An example of a practical implementation of the control unit 3 is shown in Fig.3.

Here, the functions of the combinational circuit are performed by the read-only memory chip (ROM), and the memory of the variable states is an 8-bit register. The chip K155REZ is used as a ROM. The information outputs of this chip are made according to the open collector circuit. Therefore, to obtain logical unit levels, load resistors (R1: R8) are connected to them, the second terminals of which are connected to the power supply of the microcircuit (E _n ). The outputs (D0: D7) of the ROM are connected to the inputs of the same register RG. At the input from the register, clock pulses Φ from the quartz generator G are received, which is used as a quartz multivibrator. The register is executed on triggers with recording information on the edge of the pulse at input C. In this case, the register K555IR23 is used. In order for its outputs Q0: Q7 to be open, the input of the permission E _{о is} connected to the ground potential. Some of the outputs of the register (Q4: Q7) are connected to the address inputs of the ROM (A0: A3). The address input F4 ROM and the enable input V ROM are connected to ground potential. Some of the outputs of the register (Q4: Q7) are connected to the address inputs of the ROM (A0: A3). Address input A4 ROM and input permission V ROM connected to the ground potential. From the outputs of the register Q7, Q6, Q3, Q2, Q1 and Q0, signals A, B, D, E and F are removed, which control the operation of the analog storage device (see figure 2).

 The timing diagram of the operation of the control unit is shown in figure 4. It shows the clock signal Ф arriving at the C register input, and the signals at the outputs Q0: Q7 of the register changing along its rising edge in accordance with the information recorded in the ROM. The contents of the ROM are shown in the table in FIG. 5. The hexadecimal digits below the time chart indicate the number of the current clock cycle, the binary code of which is read from the output of the register Q7, Q6, Q5, Q4 and fed to the address inputs of the ROM. In parentheses near the name of the output of the register on which this signal is generated, the corresponding control signal of the analog storage device is indicated.

 As can be seen from the timing diagram (figure 4), the operation cycle of the control unit consists of 16 cycles. In each cycle, at the output of the register, control signals and address signals for ROM are generated. In this case, from the outputs of the ROM to the input of the register receives information about the signals that should be generated at the output of the register in the next clock cycle. With the arrival of the leading edge of the clock pulse Ф, this information is recorded in the register and a new clock cycle begins.

 The measurement time T (see figure 2) is set by the requirements for a system for collecting and processing analog information. In the proposed version of the control unit, the time T takes 8 clock cycles of the unit. Therefore, the pulse period Φ should be 1/8 T. Therefore, the frequency of the crystal oscillator: f = 8 / T.

 The proposed embodiment of block 3 is convenient in that it allows you to easily change the temporal relationship between the signals A: F, depending on the specific requirements for the analog storage device. This is achieved by reprogramming the ROM and increasing its information capacity.

 Signals A: F can be used for the interaction of the analog storage device and other nodes of the system for collecting and processing analog information. So, a signal slice B can be used to start an analog-to-digital converter.

 In complex systems, the control unit 3 can be made on the basis of a microprocessor.

The device operates as follows. The signal at the output of the BVH can be represented by the following expression:
E = E _c + E _cm + E _q (1) where E _c is a useful signal;
E _cm is the bias voltage;
E _q is the voltage due to the phenomenon of charge transfer.

E _cm and E _q are the components of the additive error of BVH. Their exclusion from the output signal is made by storing the value (E _cm + E _q ) on the capacitor and then subtracting the stored voltage from the output voltage of the BVX. To do this, at certain points in time, a signal equal to zero is stored in the BVX, and at the output of the BVX, when the device enters the storage mode, the signal Ea will be equal to: E _a = E _cm + E _q .

This signal is stored on the capacitor, one lining of which is connected to the BVH output, and the second to the ground potential. Then the second lining of this capacitor is disconnected from the ground, and the BVH is switched to the sampling mode of the input signal, which at the same time enters the input of the BVH. After storing the input signal, the BVH is transferred to the storage mode. In this case, the voltage E at its output will be equal to:
E = E _c + E _cm + E _q , and on the second lining of the capacitor E _o :
E _out = E - E _a = E _s + E _cm + E _q - E _cm - E = E _s
It is seen that the voltage stored on the capacitor compensates for the additive error of the BVC. Since the second capacitor plate is connected to the output of the device through a buffer amplifier, we get a signal at the output without the components of the additive error.

 Control signals are generated in the control unit 3.

 Conventionally, the device circuit can be divided into two channels operating in turn.

 Consider the operation of the channel, including BVH 2, capacitor 5, key 7. The zero level of signal B generated by block 3 puts key 1 into a state when its output is connected to its second information input connected to the zero potential bus. This potential is fed to the information inputs of the BVH. A single signal level C from block 3 is received at the input of sample permission BVX 2, which puts the BVX 2 into the sampling mode, and the signal with a zero value is stored in the BVX 2. After the end of this process, the BVX 2 signal C (zero level) is transferred to storage mode and at its output the signal includes only the components of the additive error. A single state of the signal D puts the key 7 in the closed state, so that the capacitor 5 is charged to the voltage at the output of the BVX 2. Then the key 7 is opened (signal D goes into the "zero" state). The signal B goes into a single state, connecting the analog input BVX2 to the first analog input of key 1, which is the input of the device. The input signal is stored in BVX 2 by a single state of signal E, after which BVX 2 is transferred to storage mode (C = 0). Then the signal A = 1 puts the key 9 in a state in which the input of the buffer amplifier 10 is connected to the second plate of the capacitor 5. In this case, the signal from the output of the BVX 2 without the components of the additive error enters through the buffer amplifier 10 to the output of the device, and the process described above repeated in the channel containing BVX 4, the capacitor 6 and the key 8.

The proposed device is compensated drift error addition CVS first and second, reducing the requirements for them, in particular, to exclude from their schemes balancing resistors, and also can reduce the requirements for the C _xp comprising the CVS. Compensation E _q can significantly reduce the value of the capacitance C _xp and thereby increase the speed of the device.

 In order that the inclusion of keys 7 and 8 in the device circuit does not lead to an increase in the error due to charge transfer from the control circuits to capacitors 5 and 6, their capacities are selected significantly more than the capacities of the storage capacitors that are part of BVX 2 and 4. This does not lead to a malfunction of the device, since changes in the time of the additive error of the CVC (temperature drift, drift of the bias voltage, etc.) have a low speed and, despite the large capacitances of capacitors 5 and 6, the voltage on them will track the changes error.

Claims (1)

 ANALOGUE REMEMBERING DEVICE, comprising a control unit, first and second sampling and storage units, first and second analog keys and a buffer amplifier, characterized in that the third and fourth analog keys, the first and second storage elements on the capacitors are inserted into it, the first information input of the third the analog key is the information input of the device, the second information input of the third analog key is connected to the zero potential bus, and the output is connected to the information inputs of the first and second about sampling and storage units, the outputs of which are connected to the first plates of the first and second capacitors, respectively, the second plates of capacitors are connected to the information inputs of the first and second analog keys, respectively, to the first and second information inputs of the fourth analog key, the output of which is connected to the input of the buffer amplifier, the output of which is the output of the device, the outputs of the first and second analog keys are connected to the zero potential bus, and the control inputs are connected to the first and second m outputs of the control unit, the third and fourth outputs of which are connected to the control inputs of the third and fourth analog keys, respectively, the fifth and sixth outputs of the control unit are connected to the sampling enable inputs, respectively, of the first and second sampling and storage units.

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