SU1495853A1 - Analog memory - Google Patents

Abstract

The invention relates to computing, namely, storage devices and can be used as analog storage devices in data acquisition systems for microprocessor systems. The purpose of the invention is to improve the accuracy - by introducing into the device an additional three switches, three passive elements, a storage element on the capacitor, a key and two voltage followers. The switches 1-4 and the keys 12 and 13 provide four stages of operation of the device, in which the current zero offset voltages of the amplifier 11 and the voltage followers 16 and 17 are compensated. 1 il.

Description

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And: commemoration relates to computing, namely, to remembering devices, and can be used as an analogue-nominal device in data acquisition systems for microprocessor-based devices.

The purpose of the invention is to improve the accuracy of the device.

The drawing shows a functional diagram of the proposed device.

The device contains switches 1-4, passive elements 5-10, operational amplifier 11, switches 12 and 13, storage elements on capacitors 14 and 15, voltage followers 16 and 17, zero potential bus 18, inputs 19 and 20, and outputs 21 and 22, Passive elements 5-10 are made on resistors.

The device works as follows

i The inputs 19 and 20 of the device receive 1 two input voltages i and, In the first stage, the switches I 1–4 are closed on the bus 18, the key 12 i is closed, the key 13 is open. If all the resistors are 5-10, at the first output of 2 G, the devices are received;

P7 P7 (1+ | g +, -mc "r3Uc4 ,,

where Uc / 4, H VcHi) is the bias voltage; zero amplifiers 16 and

17 respectively.

In the second stage, the key 12 opens, the key 13 closes, the switch 2 connects the first output 21 of the device through the element 6 to the inverting input of the amplifier 11. The switches 1, 3 and 4 remain closed 1 1 to bus 18,

Then, at the second output, 22 devices receive a voltage

R7

R7, R7,

 - g well, L (1 R y5 -is "1 H kg

 -UcH, + lbij, 50

-de Uebi, 3UcM (+ U (-. M, stage 2); UcAf. - zero bias voltage

amplifier 17,

In the third step, the key 13 pasMbJKa-a, the key 12 closes, the switch 3 connects the output of the amplifier 17 through element 8 to the non-inverting Bxoiy amplifier 11, the switches and 4 remain closed to the bus 18, the switch 2 closes to the bus 18,

Then at the first output 21 devices get voltage

T, - (R9JLBI22P4 + L.

Willow.R8 + (R9 II RIO) R6 R5

R7 R7 g + 5) UcM + U H5 3lfc ", + Uc" j,

where UftH) (g -Uc / 4, + Uc ",,, (previous step); R91IR10 - Resistance value formed by parallel connection of elements 9 and 10.

At the fourth stage (the actual sampling mode), the key 12 is closed, the key 13 is closed, the switch 2

 Connects the first vyhbd 21 devices through the element 6 to the inverting input of the amplifier 11. Switches 1 and 4 connect the inputs 19 and 20, respectively, switch 3 is closed to the zero bus. Then on the second output of the device receive

(R8M R102. ,,. R7 R7. UBHX, - Kd + daT RTO) R6 R5

R7 R7 /, R7 R7v 5 h y 5th willow ,, + (1+ p7 + gr) x

R5

R6

R6 R5

"UuR, + UcjM5 Ue; j-U i (,

where UjSb (t, 3Uu4t + UcJHi, (previous step);

R8IIR10 - resistance value

formed by parallel connection of elements 8 and 10.

The bias voltage of the zero amplifier 11 and the repeaters 16 and 17 of the analogue storage device is compensated.

When the key 13 is opened, the device goes into storage mode.

UftxcrUen.

The considered zero offset voltages of the repeaters 16 and 17 and the amplifier 11 are the current zero offset voltages of these amplifiers, including both the constant components of these voltages and their temporal and temperature drift.

The device also makes it possible to compensate for the switching errors of the keys 12 and 13, in whole or in part. If the switching tolerance of the keys 12 and 13 is constant for all recorded on capacitors

5l /

14 and 15 voltages, it can be considered as an additional (additive) error to the bias voltage of the zero repeaters 16 and 17, respectively, which is fully compensated for during the four indicated stages of operation of the device. If the switching error of the keys 12 and 13 is a signed (but not constant) function of the capacitors written on the capacitors 14 and

During the four stages of work, it is partially compensated. The specific level of compensation for commutation error depends on the nature of the sign-based function of commutation error.

Claims (1)

Formula An analog storage device containing an operational actor, the inverting input of which is connected to the first terminals of the first and second passive elements, the output of the operational amplifier is connected to the information input of the first key, the first voltage follower, the input of which is connected to the output of the first key, the first storage element on the first capacitor, one of the plates of which is connected to the zero potential of the device, the first switch, the output of which is connected to the second output of the first passive element, a first input of the first switch is the first data input device, the third passive element of h and T l and Yu-o f e to the fact that, in order to increase the accuracy of the device introduced into it a fourth, fifth and sixth pass 0 five 53i The second element, the third, third, third, and fourth group.);) Teli, the second key, the second memory element on the second controller, and the second voltage follower, whose input is connected to one of the plates of the second capacitor and with the output of the second key, whose information input connected to the output of the operational amplifier; another plate of the second capacitor is connected to the zero potential bus ycrpoi icTBa; the output of the first voltage follower is the first output of the device and is connected to the first input of the second switch; which is connected to the second output of the second passive element, the first output of the second passive element is connected to the first output of the third passive element, the second output of which is connected to the output of the operational amplifier, the input of the first voltage follower is connected 5 with another plate of the first capacitor, the output of the second voltage follower is the second output of the device and is connected to the first input of the third switch, the output of which is connected to the first output of the fourth passive element, the second output of the fourth passive element is connected to the first conclusions of the fifth and sixth passive elements and c with a non-inverting input of the operational amplifier, the second output of the fifth passive element is connected to the output of the fourth switch, the first input of which is the second 0 information input device, the second inputs of the switches and the second output of the sixth passive element connected to the bus zero potential.