SU711674A1

SU711674A1 - Synchronous detector

Info

Publication number: SU711674A1
Application number: SU782664343A
Authority: SU
Inventors: Олег Леонидович Николайчук; Юрий Васильевич Рево
Original assignee: Специальное Конструкторское Бюро Микроэлектроники И Приборостроения
Priority date: 1978-09-15
Filing date: 1978-09-15
Publication date: 1980-01-25

Description

II

Изобретение относитс к области радио- и электроизмерительной техники и может быть использовано в фазочувствительных, амплитудных вольтметрах, в устройствах выделени синфазной и квадратурной составл ющих напр жени переменного тока.The invention relates to the field of radio and electrical measuring equipment and can be used in phase-sensitive, amplitude voltmeters, and in-phase and quadrature separation devices for alternating current voltage.

Известен синхронный детектор, содержащий последовательно соединенные первый ключ, усилитель и второй ключ, а также запоминающие конденсаторы, подключенные к выходам ключей , и формирователь, вход которого соединен с источником опорного сигнала, а также триггер , вход которого соединен с выходом формировател , а выходы подключены соответственно к входам ключей 1.Known synchronous detector containing serially connected first key, amplifier and second key, as well as storage capacitors connected to the outputs of the keys, and a driver, the input of which is connected to the source of the reference signal, as well as a trigger, the input of which is connected to the output of the driver, and the outputs are connected respectively to the inputs of the keys 1.

Его недостатком вл етс низкое быстродействие , а также больша погрешность измерени Its disadvantage is the low speed, as well as the large measurement error

Цепью изобретени вл етс повышение быстродействи и точности измерени .The chain of the invention is to increase the speed and accuracy of measurement.

Это достигаетс тем, что в устройство, содержащее последовательно соединенные формирователь и триггер, один выход которого соединен с управл ющим входом первого ключа, а другой выход - с управл ющим входом второго ключа, а также усилитель и два конденсатора , у каждого из которых одна обкладка соединена с общей шиной, введены третий и четвертый ключи, управл ющие входы каждого изThis is achieved in that a device containing a serially connected driver and a trigger, one output of which is connected to the control input of the first key, and the other output - to the control input of the second key, as well as an amplifier and two capacitors, each with one facing connected to the common bus, the third and fourth keys are entered that control the inputs of each of the

которых соединены с управл ющими входами соответственно второго и первого ключей, причем выход первого ключа соединен с входом второго ключа, а выход третьего ключа соединен с входом четвертого ключа и с второй обкладкой второго упом нутого конденсатора, при этом входы первого и третьего ключей соеДннены с входной клеммой, а выходы второго и четвертого ключей соеданены со входом усилител , выход которого подключен к выходной клемме.which are connected to the control inputs of the second and first keys, respectively, the output of the first key is connected to the input of the second key, and the output of the third key is connected to the input of the fourth key and the second lining of the second mentioned capacitor, while the inputs of the first and third keys are connected to the input terminal, and the outputs of the second and fourth keys are connected to the input of the amplifier, the output of which is connected to the output terminal.

На чертеже приведена схема синхронного детектора .The drawing shows a diagram of a synchronous detector.

Синхронный детектор содержит последовательно соединенные формирователь 1 н - триггер: 2,The synchronous detector contains a serially connected driver 1 n - trigger: 2,

Claims

one output of which is connected to the control input of the key 3, and the other output to the control input of the key 4, as well as the amplifier 5, and capacitors 6 and 7, each of which has one lining connected to the common bus, as well as the keys 8 and 9 , the control inputs of each of which are connected to the control inputs of the key 4 and the key 3, respectively, the output of the key 3 is connected to the input of the key 4 and the second plate of the capacitor 6, and the output of the key 8 is connected to the input of the key 9 and the second plate of the capacitor 7 while the input (Key 3 and key 8 are connected to the input terminal mine, and in The keys of key 4 and key 9 are connected by the input of amplifier 5, the output of which is connected to the output terminal. The synchronous detector operates as follows: Shaper 1 generates rectangular pulses from the reference voltage, which arrive at the counting input of the trigger

2. At outputs of flip-flop 2, square wave pulses with a duration equal to the period of the support voltage are forlted. The analog keys 3, 4 and 8 are controlled, 9, from the outputs of Figger 2, so that when the keys 3 and 9 are open, the keys 8 and 4 are closed. When the switch 3 is open, the capacitor 6 capacitor 6 repeats the input voltage, while the switch 4 is closed and the capacitor 6 circuit is connected — the input of the amplifier 5 is open. At this time, the switch 9 is open and the voltage from the capacitor 7, corresponding to the amplitude of the input voltage and phase shift between the reference and input voltages, is fed to the input of the amplifier 5. The key 8 is open. In the next period of the reference voltage on the capacitor 6, the voltage is remembered and through the public key 4 is fed to the input of the amplifier 5. At this time, the key 9 is open and the input voltage through the public key 8 is fed to the capacitor 7. Thus, in the code of the amplifier the voltage corresponds to the amplitude and phase: the basic shift of the voltage measured by the voltage relative to the reference. As a result of the insertion into the synchronous detector of two analog switches, its performance is twisted, since with a change in the amplitude or phase of the input voltage, the output voltage of the detector changes already in the next period of the reference voltage. The accuracy of the device offered is higher than that of the known device, since there is no consistent rewriting from one memory capacitor to another. Claims of the invention A synchronous detector comprising a serially connected driver and a trigger, one output of which is connected to the control input of the first key and the other output to the control input of the second key, as well as an amplifier and two capacitors, each of which has a first plate bus, and the second plate of the first capacitor is connected to the output of the first key, which is characterized by the fact that, in order to improve speed and accuracy, the third and fourth keys, the control inputs of each of which are connected There are control inputs of the second and first keys, respectively, the output of the first key is connected to the input of the second key, and the output of the third key is connected to the input of the fourth key and the second plate of the second capacitor, the inputs of the first and third keys are connected to the input terminal, and the outputs of the second and the fourth key is connected to the input of the amplifier, the output of which is connected to the output terminal. Sources of information taken into account during the examination 1. USSR Author's Certificate No. 5412182, cl. H 03 K 9/04, 1975.