SU1272272A2 - Amplitude-phase harmonic analyzer - Google Patents

Abstract

This invention relates to electrical measuring technology. It is additional to auth. USSR № 815669. The purpose of the invention is the expansion of functionality. A device containing a sine-cosine voltage generator 1, an operational amplifier 3, a digital controlled resistance unit 4, a digital controlled conductivity unit 5, analog switches 7-11, an analog switch 12, a resistor 13, a comparator 14 are entered to achieve the target. , trigger 15, one-shot 16, AND-NOT gate 17, counter 18, registers 19, 20. The device allows, in addition to analogous values, to present the results of measuring amplitude and phase in digital form. When using the device as an autonomous measuring instrument, the presence of code outputs allows the use of digital with indicator and memory devices, which leads to an expansion of the field of application. 5 il. 1Du Yu go yu IsP

Description

Wo / i FIG. This invention relates to electrical measuring technology. The purpose of the invention is to expand the functional capabilities by obtaining, in addition to analog values of amplitude and phase, also digital values of amplitude and phase. FIG. 1 shows a schematic diagram of the proposed device; Fig. 2 illustrates the principle and functional scheme of a sine-cosine voltage generator; in fig. 3 circuit implementations of the digital controlled conductivity unit and its equivalent circuit; in fig. 4 - circuit implementations of the digital controlled resistance unit; in fig. 5 timing diagrams explaining the operation of the device. The amplitude-phase harmonic analyzer contains (Fig. 1) sine-cosine voltage generator 1 comparator 2, operational amplifier 3, digital controlled resistance unit 4, digital controlled conductivity unit 5, capacitor 6, analog switches 7-12, resistor 13 , comparator 14, trigger 15, one-shot 16, logic element AND-NOT 17 counter iSj registers 19 and 20. The input of the analog switch 7 is connected to the first input of the device, the first output of which is connected via the analog switch 8 to the first output of the generator I of sine-cosine voltage wives you The analog key 7 in the block 4 of the digital controlled resistance is connected to the first input of the sine-cosine voltage generator 1, the second input of which is connected to the second input of the device and the first input of the digital controlled conductivity block 5, the second input of which through the analog switch 9 connected to the third input of the device, the output of the digital controlled conductance unit 5 is connected to the input of the operational amplifier 3, the output of which is connected through an analog switch 10 in parallel and a capacitor 6 connected to the output of the unit 4 digital controlled conductivity and via analog switch I1 to the second output of the device, the second output of sine-cosine voltage generator 1 is connected to the input of comparator 2, the third input of the device through serially connected analog terminal 12 and resistor 13 is connected to the first input of generator 1 sine - cosine voltage, the first output of which is connected to the input of the comparator 14, the output of which is connected to the first input of the register 20, the second input of which is connected to the output of the trigger 15, the output of the comparator 2 is connected to the first inputs mi register 19 and trigger 15 and the input of the one-shot 16, the output of which is connected to the first input of the logical element EIA 17, the output of which is connected to the first input of the counter 18, the fourth input of the device is connected to the second inputs of the trigger 15, register 19 and the logical element AND-NOT 17 The fifth input of the device is connected to the second input of the counter 18, the output of which is connected to the third inputs of registers 19 and 20, the output of the register 20 is connected to the third output of the device, the output of the register 19 is connected to the fourth output of the device, the third tripper input 15, the second the input of the comparator 2 and the second input of the comparator 14 are connected to a common bus. The sine-cosine voltage generator 1 (Fig. 2q) contains operational amplifiers 21 and 23, analog switches 24-28, blocks 29 and 30 of digital-controlled conductance, resistors 31 and 32, capacitors 33 and 34, block 35 | of the controlled resistance, a resistor 36 and an analog switch 37. The keys 24 and 26 allow for disconnecting the input circuits of the integrators, switching them to storage mode, the keys 25 and 28 are designed to set zero initial conditions on the integrators, the key 27 commutes the input signal. In the device, the generator operates in two modes. Fla concept of the generator (Fig. 2S), the first integrator 38 is formed by an operational amplifier M 21, a capacitor 33 and a digital controlled conductivity unit 29, a second integrator 39 an operational amplifier 22, a capacitor 34 and a digital controlled conductivity unit 30, the adder 40 operational amplifier 23, resistors 3 and 32, i.e. the generator can be implemented using standard electronic products. 3 The digital controlled conductivity unit 5 is a common element of analog-digital computing devices, the canonical scheme of which is shown in FIG. Behind. However, to build such blocks, it is more convenient to use (by virtue of being able to manufacture them in an integrated design) R-2R decoding resistive matrices. For the output voltage of the decoding matrix R-2R (Fig. 3). Record eb, s R + R where and ", and the input and output voltage of the decoding matrix R-2R; n is the matrix size; N is the control code supplied to the matrix; R is the output impedance of the grid; R {j is the load resistance. The equivalent decoding circuit based on the R-2R matrix from the input terminal side is shown in FIG. 3 B. If the output of the R-2R matrix is a potentially instance point, and it is precisely this case that it is used as an element of the input power of the decision amplifier, then the equivalent YN is determined by expressing Y --BblK 1 and; r where it follows from On the basis of the R-2R grid, it is possible to build the equivalent of digital controlled conductivity. The transmission coefficients of operational amplifiers 21 and 22 at the same time (Fig. YH, N,. C ,, C ,,. R-Z

At Y, the conductivity of the digital controlled conductivity blocks 29 and 30 is equivalent (Fig. 2o ();. Capacitor capacitance 33 55

GG - and 34 (Fig. 28) ,. Thus, the transfer coefficients of integrators a, and a can, with, with

T is the period of the input signal, s; k is the harmonic number. The calculated amneshtud and phase are represented in the device in a voltage:

(12;

IL C, "72" is affected by the control code. The circuit of the digital discharge unit 4 of the digital-controlled resistance (Fig. 4) can be implemented using discrete resistors and analog switches such as those indicated. The resistance of block 4 is described by the expression, (5) R where N is the control code (inverse) of block 4 of the digital controlled resistor; m is the block size. The transition to the reverse code in expression (3) is related to the fact that for modern integral analog switches, the closed state is provided at the level of logical I at the input of the key control. The transfer coefficient of the adder a (Fig. 2a, B), taking into account expression (5), is equal to i. may be affected by the control code of the digital control resistance unit 4. The transfer coefficient of the adder (Fig. 2a, 5) i: The device determines the amplitude CK and phase Cfi for the harmonic of the input signal U (t) in accordance with the expressions: C, -Ja cp arctg - + n IU (t) I dt ; (10) ||, Kt) si sin2ffk, (K. where the phase scale factor for the analog output, V / rad, and additionally in the form of a code: NcrMeC, -, where Mj, is the scale factor for the amplitude of the digital output, 1 / V; M (is the phase scale factor for the digital output. 1 / rad. The device works as follows. The entire linear amplitude-phase spectrum is calculated during the cycle time. The cycle consists of K subsequences executed sequentially in time, each of which the amplitude and phase of the alternate harmonics are calculated. Each sub-cycle contains four cycles of different The operation of the proposed device in the first and second cycles is the same as known. The designation of the type O corresponds to the beginning of the time in the i-th stage. In the first cycle, all initial integrators are set to zero (Fig. 5 , interval 0, -Oj, which is achieved by closing the keys 10 (fig. l) and 25, 28 (fig. 2a) for a time sufficient for complete discharge of the capacitors 6 (fig. 1) and 33, 34 (Fig. 2a), keys 7, 9, 12 (Fig. 1), 24 and 26 (Fig. 2o are open. In the second cycle, the decomposition coefficients in the Fourier series aj are calculated, and b, i.e., relations (10) and (P) are realized. For this purpose, the input signal U (t) is fed to the input of the sine-cosine voltage generator 1 through the closed key 7 (Fig. 1) Keys 24 and 26 (Fig. 2a a) close, connecting the integrator and the adder to the closed ring, the keys 25 and 28 (Fig. 2a) are open. The equation for the output voltage of the first integrator (Fig. 26) in the operator form -b - ". Ujp) -a, U ( p), (15) 1 72f where and (p) is the input voltage of the device in operation Athorne form, considering that the output voltage of the second integrator, and (p) .- tiu (p). substitution of the expression (16) in the formula (15) gives the closure equation:) and, (p) 4 and (p) (17) Similarly, for the output voltage of the second integrator: .. (P) - p - i, . (p) 9. 9.2 9-4 --pz - From expressions (17) and (18), a system of equations is obtained: and (p), (19a) and „(p) - a. r (196) Let us put P expressions (19) WIK P and „(p) k7 p + Jf СCOfJic. VP) - R (p) From the table of Laplace-transformed functions, extract: () coscj, t Use the folding theorem, (p) -F (p) ./ f () -f, (tt) d: (26) and transform expression (23), taking into account expressions (24) and (25), into the time domain: and, (t) if --- f U (r) cosO, (tl) dt. about. KGI U (7r) ce; ci; - cosu t c sc sco tdc + t1 + sino, t i u (t) sinw,;: dt; J; u (t) - I u (e) sinwK (tt) d -X -, - cosw, t U (i:) sinw odt L0, -sina t 1 U (o) cosu, i: dtj, (27b Let the duration the cycle is equal to the period of the input signal T. At the end of the cycle, the output voltages of the integrators are: u (T) - fcoscj.T f U (C) coscJ, rdC- +. 2iKIT Iej + sincj, T / U (r) sinco, and (T) f U (e) sinu d I0 -sinOjTJ U (t) cosu rdtj. Taking into account expressions (21) and (22), we obtain: WK 2hk 2. kf cosoKT cos2lIk l; sinO T sin2fi-k 0. Finally, U2, (T) | U () cosu, Td7..U ,; (29a U (T) j U (t). (296 oi) Thus, in the considered mode, generator 1 of sine-cosine voltage realizes a pair of formations of Fourier (Yu) and (P). In the second cycle, the additional circuit elements of the slave It is not accepted. The fourth input of the device (input Resolution) is supplied with the voltage of logic O. This signal acts directly on the data receive control input DE (data enable with the connected inputs 1 and 23 of the register) of the second register 19, putting it into data storage mode. In addition, this signal, affecting the setup input into 1 flip-flop 15 (input S), sets this flip-flop to a state of logical O on the inverse output that is connected to the DE input of the first register 20. Thus, in the second clock, the register 20 also saves em: previously recorded information. Finally, the Account Resolution signal sends the output of the NAND 17 logic element to state 1, which ensures the installation of the counter 18 in the second cycle to the initial zero state. As a signal, the resolution of the count can be used, for example, the inverted control signal of the analog key 7 from the scheme of a known device. In the third cycle, the known device implements relations (8) and (9), i.e. performs an operation of building a vector over two components (converting coordinates from a rectangular system into a polar one. In this cycle, the analyzed signal at the input of the sine-sinus voltage generator 1 is not applied (key 7 is open, keys 24 and 26 are closed, keys 25 and 28 are open In this case, the generator goes into free oscillation mode, simulating the law of variation of the rectangular components of the vector U, given by the initial coordinates Ug and U in the rotating with the angular velocity about the system of rectangular coordinates (Fig. 5a, &); U. (t ) -U (0,) cosot + U, (0,) sinot (ЗОа) U (t) -U, (03) sinut + U (0,) costot, (306) where ω is the oscillator natural frequency, taking into account that the beginning of this measure corresponds to the ending of the preceding (its, i.e. Uz, (03) Ua,; r / 0}) U8, the expression (DA) is reduced to the form Uj., (t) (ot + U sinut- (31 a) U., ( t): -Ug sincjt + U, coswt. (316) At some point in time 0.t T, the voltage at the output of the second integrator (Fig. 2) is zero Ujt), and from the equation (31 b) get tg.t ; jb .. t, ;; tot:. (32) Equation (32) has on the segment 0, Tj, and the solution:

t ;. 1 arctg be (33a)

.WUg

t l (arct.g. Hi-Hir). (336) Physically, this means that the output voltage of the second integrator during the period of free oscillations passes through zero twice. In accordance with equation (9) with Ua, the equation (ЗЗа) should be adopted as a solution, with equation (ЗЗб). Knock out the scheme. It is the correct solution to automatically, if it is additionally required that in MOMfeHT the solution t the output voltage of the second integrator, the zero-crossing, changes from minus to plus. At this point, the time -t is indicated by a positive voltage drop () in (Fig. 5e), and the output of the comparator is 2 ti (arctg - L - + nf), (34), - as at U (j O and at. Thus , the interval from the beginning of the clock to the specified time is proportional to the desired phase of the analyzed harmonic. This interval is converted to voltage as in the known device and additionally to code. The interval-voltage conversion is performed in the same clock by the third integrator based on operational amplifier 3 ( Fig. 1), key 9 is closed, key 10 is open): Uj, U) a, Ut, the voltage is source of DC voltage, V; .Chg Transmission coefficient of the third integrator, c,: Equivalent Conductivity of block 5 and. Of the digital controlled conductivity determined from Dither (-2), Cm; capacitor capacitance, F. At time t, the output voltage of the third integrator from expressions (35) and (34) arctg () + t 2-2 Uz, () Uo.

1272272

ten

 -Uc

(37)

proportional to Cfij,.

Claims (1)

From the comparison of expressions (12) and (37) the scale factor for analogue output in phase 1 0 The oscillation frequency of the generator (Fig 2) Q l | a, a. a, (20) and (21) and under the conditions of (AO) Q, aj ,. In view of formulas (2) - (4), (Zb), we have: ,, N9 YNIO UJ - ... b | Hz. Cf g Y o k - ftt Expression (42) allows determining the phase scaling factor for the analog output, it also implies that, for independence of m. (F from the harmonic number, it is sufficient to feed to the control inputs of blocks 5 and 29, 30 identical codes N. In the proposed device in the third cycle the code N is supplied to the input N, which provides the setting of the generator for the first harmonic (,), From equations (2) and (41), .21 | PC „„ 2ЯВС, n I. -. d --- .. .. At time t, key 9 is opened, and key 11 is closed, transferring Uy, to the second output of the device. the value of the phase is determined in digital form. The signal of the counting resolution takes the value of logical I (FIG. 56) The voltage at the output of the one-shot 16 normally has a value of logical 1, respectively, the output of the logical element AND-NOT 17 becomes logical O. At In this case, the counter 18 counts the reference frequency pulses fon (Fig. 5 g). At the time t, the number accumulated in the counter is equal (fon f N (t) t. arctg (r. + P or. yYY f T From comparison of expressions (14) and (44) the scaling factor for the phases for the digital output f. F m about f 21 G Positive difference to the output of the comparator 2 at time t (Fig. 5e) entering the clock input of the register 19 dynamically provides the reading of the N code (. from the counter 18 to the register 19. In addition, the indicated differential triggers the one-shot 16, the output of which produces a short pulse of negative polarity and (FIG. 5e). This pulse inverts the logical element AND-NOT 17 (at the second input, the element of logical 1) and resets the counter 18 to the initial zero state is prepared for its operation in a new cycle. In the third cycle, the value of the amplitude in the analog form is also determined. We transform equation (31a) to into.,) U cosot + U sinat | Ua, + and cos (cot -q)), and, d-- o. According to expression (32) at time t. Ubk tgcrt-, whence it follows, 4Totot and Uj, / t); iu ,. r 2 -k Ck i.e. at time t. the output voltage of the first integrator (Fig. 2) is equal to the amplitude of the kth harmonic of the signal under study. The closure at a specified time of the key 8 allows the amplitude value to be transmitted in the form of voltage to the registering device. The duration of the third cycle is a variable that varies and ranges from 0 to T depending on the initial phase of the kth harmonic. The fourth cycle in the proposed device is required to determine the amplitude value numerically. The beginning of the fourth cycle is indicated by a change in the state of trigger 15 under the influence of a positive differential at the output of comparator 2 to the synchronization input (clock) of the trigger. The state of logical 1 at the inverse output of the trigger 15 permits the recording of information into the register 20. The keys 7, 9, 10 are open (Fig. 1), the key 9 (Fig. 1) is closed. In the sine-cosine voltage generator 1 (Fig. 2), the keys 25, 26 and 28 are open, the keys 24 and 26 are closed. In this cycle, a voltage equal to the amplitude of the kth harmonic (47) is transformed as a result of its write-off by the voltage of the reference source into a proportional time interval. The voltage at the output of the first integrator varies linearly to zero according to the law: U. (t) Uj ,, (04) -aga ,, Ue. t, (48) where Uj / O) is the voltage at the output of the first integrator at the beginning of the first cycle. AT; R4 d, d, a. rg- is the transfer coefficient of the adder (FIG. 2) at the third input; 1 transfer coefficient of the first integrator, s, defined by the formula (3); Up - voltage of the reference source, V.. At the instant -time t, the voltage at the output of the first integrator is zero, while from expression (47); "Y ,, (oj Uc.,. And; ha7Ha; u ;, At the beginning of the fourth cycle, the counter 18 is reset to the initial zero state, therefore the number Accumulated in the counter 18 at the time j to t:., M, .U , N,. (50) The scale factor for the pietrovou output and a: a: - E; 13: at the moment the output voltage of the first integrator goes through zero, t, the comparator 14 changes its state from 0 to 1 (Fig. 5g). This differential, arriving at the synchronization input (clock) of register 20, provides the reading of the W. code from counter 18. This cycle ends the cycle, then, if necessary, a new cycle begins, in which the other harmonic is calculated. In the practical implementation of a specific element base, some additional elements can be excluded. For example, an entry in the counter of the number 0000 (in binary number system) using the corresponding inputs of the microcircuit can be additionally used to reset the setting in О of the counter. When I do this, the logical element; AND-NOT is excluded. A single vibrator can be implemented based on unused trigger, logic elements, comparator, i.e. the attraction of additional hardware. Thus, obtaining measurement results - in the form of a code, is achieved practically only by introducing a counter and two registers. When using one analog-digital converter for storing code, registers must also be used. As a result, we have instead of; analog-digital; a converter, a counter that is much more efficient, more reliable and more reliable. In addition, the well-known single-crystal analog-digital converters require significant additional hardware costs for generating control signals, a hundred ample reference voltage, etc. . The proposed device allows, in addition to analog values, to present the results of measurement, nor amplitude and phase in digital form. In this case, it becomes possible to use a known device in control and measurement systems 12 with a digital form of information representation, which significantly extends its scope. When using the device as an autonomous measuring device, the presence of code outputs allows the use of digital indicator and memory devices, which also leads to the expansion of the field of application. Invention Amplitude-phase harmonic analyzer according to auth.St. No. 815669, which is based on the fact that, in order to expand its functionality, it additionally introduces an analog switch, a resistor, a comparator, a trigger, a single-oscillator, an NAND gate, a counter, the first and second registers, and the third input of the device Analog switch and resistor connected in series are connected to the first input of a sine-cosine voltage generator, the first output of which is connected to the input of an additional comparator, the output of which is connected to the first input of the first register, the second input of which connected to the trigger output, the comparator output is connected to the first inputs of the second register and the trigger and the one-shot input, the output of which is connected to the first input of the NAND logic element, the output of which is connected to the first input of the counter, the fourth input of the device is connected to the second inputs of the trigger, the second register and logical element AND-NOT, the fifth input of the device is connected to the second input of the counter, the output of which is connected to the third inputs of the first and second registers, the output of the first register is connected to the third output of devices a, the output of the second register is connected to the fourth output of the device, the third input of the trigger, the second input of the comparator and the second input of the additional comparator are connected to the common input. il29 (t} .Z 2fJ HZ 2f I cp lr A / L- / W / V / V   , R FI GL dJ CZD1 -cmi JFig. but) 6) Oh qz t (K- llJWSUUKK 5