SU1335935A1 - Device for measuring frequency characteristics - Google Patents

Abstract

The invention relates to automation, measuring and computer technology and can be used to determine the frequency characteristics of dynamic objects. The purpose of the invention is to improve the accuracy and expansion of functionality. A device for measuring frequency characteristics contains a digital harmonic generation unit 1, a digital-to-analog converter 2, the first 3 and second 4 digital-analog multipliers, the first 5 and second 6 discrete integrators, the first 7 and second 8 counters, unit 9 measuring the module and phase, element 10 delays. Unit 1 has the first and second code outputs, the first and second sign outputs, and the pulse output. The first discrete integrator has information, sign and control inputs. The second discrete integrator has information, sign and control inputs. Unit 9 has first, second informational and control inputs. The input and output of the object are connected to the test object. The purpose of the invention is achieved by introducing the first 7 and second 8 counters, block 9 and delay element 10. The device for measuring the frequency characteristics carries out the determination with high accuracy, since allows you to measure the required number of ordinates, equivalent to their set, located on the interval of one period, and at the same time provides the use of equipment with a sufficient measurement and data conversion. 2 hp f-ly, 5 ill. (L oo oo JV SO oo sd

Description

one

The invention relates to automation, measuring and computing technology and can be used to determine the frequency characteristics of dynamic objects.

The purpose of the invention is to improve the accuracy and expansion of functionality.

FIG. 1 shows a block diagram of an instrument for measuring frequency characteristics; in fig. 2 is a block diagram of a digital harmonic generation unit; in fig. 3 is a discrete integrator block diagram; in fig. 4 - graphs explaining the principle of operation of the device; in fig. 5 - graphs explaining the operation of the digital harmonic generation unit.

The device contains a digital harmonic generation unit 1, a digital-to-analog converter 2, the first 3 and second 4 digital-analog multipliers, the first 5 and the second 6. Discrete integrators, the first 7 and second 8 counters, the module 9 measuring the module and phase, delay element 10 , the first 11 and second 12 code outputs, the first 13 and second 14 sign outputs and pulse output 15 of a digital harmonic generation unit, information 16, sign 17 and control 18 inputs of the first discrete integrator, information 19, sign 20 and control 21 inputs of the second discrete integrator, the first information 22, the second information 23 and the control 24 inputs of the measuring unit module and phase. Position 25 marked the object of the test.

The digital harmonic generation unit 1 (Fig. 2) contains a clock generator 26, an n-bit argument counter 27, a first logic block 28, a memory 29, a first logic element 30, a second logic element 31, an inverter 32, a first buffer register 33, second buffer register 34.

Discrete integrators 5 and 6 (Fig. 3) contain analog-to-digital converter 35, second logic unit 36, accumulating adder 37, RS-flip-flop 38, second delay element 39, input 40 of starting analog-digital converter, recording input 41, input 42 switching modes and input 43 transfer accumulating adder. FIG. 4 are designated: signal plots 44 at output 15, signal plots 45 at counter 7 output, signal plots 46 at first digital-analogue multiplier output, signal plots 47 at output 13, signal plots 48 at second output, signal plots 49 at electrical output 10 delays.

FIG. 5 denotes: plots of signals 50 at the outputs (p-2) of the lower bits of the argument counter, plots of signals 51 at the outputs of the first logic unit, plots of signals 52 at the output of the memory device, plots of signals 53 at the output (p-1)

bit counter argument.ment, signal plots 54 at the output of the first logic element, signal plots 55 at output 11, signal plots 56 at output 12.

The operation of the device involves the calculation of the Fourier coefficients ai and bi, which determine the first harmonic component of the reaction F (t) (where t is time) of the object 25 tests for the harmonic effect of a fixed frequency w (where T is the period of the acting harmonic) and the subsequent determination of the frequency response from derived coefficients. For this, the instrument generates two signals:

15

F (t) sin.t; F (t) cos% -t,

(2)

as well as a sequence of pulses, the frequency of which D1 is such

that the period T places exactly 2 such D1-intervals in itself, i.e.

T 2 At, where n const. At the same time, the interval At is assigned sufficiently small so that the sum of the ordinates of the signal (1) and the signal (2) located on a segment of one period T with this interval determines the Fourier coefficients with the necessary accuracy.

The peculiarity of the technique implemented by the device is that, using the interval At as a measure of time, it performs the registration of ordinates (1) and (2) with a step kAt (K is integer) at a time interval equal to QD. In this case, each of the registered sequences contains ordinates, the values of which coincide with the values of the ordinates of the corresponding signal, located on a site of the same period with the gap At.

The equality of the values of the ordinates of these sequences, and hence the corresponding sums, is:

(j KAt) k At

Mr. N

. 2n.,

 (i At) sin4piAt;

(j-k-At) cos25 .kit .and

50

 2 - SF (i-At) AI,

(four)

and takes place when the values of the period of the discretization step, and accordingly the values 2 and K, relate to each other as mutually simple numbers.

The right-hand sides of expressions (3) and (4) determine the values of the corresponding Fourier coefficients (bi and ai) of the first harmonic of the periodic signal F (t), calculated using the approximate Bessel formulas.

Such registration of the ordinates of signals (1) and (2), implemented by the proposed device and their subsequent summation, provides the necessary data to calculate the Fourier coefficients. In this case, the possibility of choosing the value of K, at which the step of registration exceeds the time constant of the equipment used, allows one to register the necessary number of addends of the left parts of expressions (3) and (4) to determine the Fourier coefficients with the required accuracy.

The device works in the following way.

A sequence of pulses 44 is formed with a frequency At at the pulse output 15 of the digital harmonic generation unit 1. On the first and second code outputs 11 and 12 of this block, codes are formed that approximate the absolute values of the sinusoidal and cosine-sinusoidal functions of time, respectively, in the form of step curves.

The code of the absolute value of the sinusoidal signal formed on. output 11, and the binary signal 47 of the first sign output 13, affect the outputs of the digital-to-analog converter 2, which forms a sinusoidal analog signal, exciting the test object 25. The test object 25 responds to this excitation by forming a periodic signal F (t) at its output.

This periodic signal is fed to the analog inputs of digital-analog multipliers 3 and 4, the digital inputs of which simultaneously perceive the codes of the absolute values of the sinusoidal and cosine signals, respectively, from the outputs 11 and 12 of digital block 1.

Due to this, the outputs of the first and second digital-analog multipliers 3 and 4 form the signals of the products

F (t) and F (t)

A graph 46 of a signal of this type, formed at the output of the first digital-analogue multiplier 3, is shown in FIG. four.

The signals formed by digital-analog multipliers 3 and 4 are transmitted, respectively, to the information inputs 16 and 19 of discrete integrators 5 and 6. Sign inputs of these integrators from the sign outputs 13 and 14 of digital block 1 are simultaneously affected by signals whose playback logic levels t signs, respectively, of sinusoidal and sinusoidal harmonics. One of these signals, namely the output signal GZ of the digital unit 1, determining the sign of the sinusoidal harmonic, is represented by the graph 47 in FIG. four.

0

Discrete integrators 5 and 6 when summing the values of the ordinates of the signals arriving at their information inputs 16 and 19. take into account the polarity of these signals, as well as the logical levels of the signals at their sign inputs 17 and 20, (harmonics signs).

Discrete integrators 5 and 6 at the moment of affecting their control inputs 18 and 21 of the latter, i.e. the pulse of the counter 7 formed by him on the time interval K.T. (plot 45) performs the last registration of the ordinates of the signals of the digital-analog multipliers 3 and 4, which are necessary to calculate the Fourier coefficients. At this point in time, on the falling edge of the K-th pulse of the sign output 13 of digital block 1 (chart 47), i.e. after the K periods of duration T expire, the second counter 8 forms a signal 48 at its output. This signal, acting on the delay element 10, causes its output at time 6t. at the signal level 49.

The signal 49 received at the control input 24 of the module 9 measuring the module and phase initiates it for sensing through the information inputs 22 and 23 of the codes generated at the outputs of discrete integrators 5 and 6 and reproducing the sum of the ordinate signals (1) and (2 ), recorded with a discretization step of m CL1 on a time interval equal to K.T.

The excitation delay of control input 24 of measurement unit 9 after the occurrence of signal 48 is necessary to wait for the completion of transients in discrete integrators 5 and 6. associated with the last summation cycle.

The correspondence between the values of the arguments of the ordinates recorded by discrete integrators 5 and 6, as well as the values of the arguments of the ordinates located in the same period for the case when T 16At (Fig. 4) is illustrated by the following relations:

0

five

Z.M.Z.D (;

6.At 6.At;

9.At 9.At; 12.At 12.At; 15.At 15.At; 18.At 2.At + T: 21.At 5.At + T; 24.At 8.At + T;

27.At 11 .At + T;

30.At 14.At + T;

33.At l.At + 2T;

36.At 4.At + 2T;

39.At 7.At + 2T; 42.At 10.At + 2T; 45.At 13.At + 2T;

48.At O.At + 3T.

The module 9 measuring the module and the phase, fixing through its information inputs 0 DL1 22 and 23 codes of numbers defining the sums of the ordinates of signals (1) and (2), multiplies the fixed sums by the scale factors, thus forming the first harmonic Fourier coefficients object response 25 tests for harmonic effects from the digital-to-analog converter 2:

B, (j KAt) .K-.t;

five

a, (jKAt)

 To At.

By calculating the coefficients a nb, block 9 determines, using known relations, the amplitude B and the phase angle f of the first HARMONIC of the signal F (t):

B (oj) Va1 + bT;

(n ((l) arcig-r-.

    bi

The amplitude-frequency characteristic of the test object 25 is detected by block 9 by determining the ratio of the obtained amplitude value B (s) to the known amplitude value of the harmonic effect generated by the digital-to-analog converter 2. Since the moment corresponding to the zero phase of the harmonic effect is taken as the time reference at registration of the ordinates of the output signal of the test object 25, the calculated value of the phase angle cp (co) is taken as the phase response.

The data calculated by unit 9, the measurement of the module and phase, characterizing the frequency properties of the test object 25, are performed on the output device of this unit.

Fir charts. 5 depicts the signals acting in time in the first two and partly in the third period of the generated harmonics. In doing so, they depict a variant of the digital block 1 of the generation of harmonics 1, in which the width of the argument counter 27 is shch, and the width of the logic block 28, the memory 29 and the buffer registers 33 and 34 are four.

Digital block 1 generates a sinusoidal and cosine wave function as a sequence of codes representing the absolute values of these functions (graphs 55 and 56) and signals whose logic levels correspond to their signs (the signal whose logic level reproduces the sinusoidal harmonic sign is represented by the graph 47 in Fig. 4).

Digital unit 1 contains a clock generator 26, which forms U-shaped impulses (plot 44) designed to clock the operation of the digital unit 1 and the entire instrument.

These pulses go to the pulse output 15 of digital block 1, to one of the inputs of the first logic element 30 and to the input of the argument counter 27, the contents of which due to this evenly vary over time, and the filling of all the bits of the counter occurs during a time equal to the period of the generated harmonics .

Consequently, the frequency of these harmonics is determined by the frequency of the pulses 44 and the width of the counter 27 of the argument.

five

0

0

five

0

five

0

five

0

The outputs (n-2) of the lower bits of the argument counter 27, the contents of which are shown by the graph 50, bitwise affect the first inputs of each element of the logic block 28. Since the combined second inputs of these elements receive pulses of the clock generator 26, then they perform a logical equivalence operation , each element of the logic unit 28 at the time of the pulse of the clock generator 26 reproduces the logical level of the signal arriving at its first input, and in the phase of the pause between pulses forms a signal this logic level. Thus, at the outputs of logic block 28, two interleaved code sequences are formed (chart 51), one of which displays a sequence of numbers increasing from zero to a maximum value equal to (), and the other one decreasing from this value to zero.

The output codes of the logic unit 28 affect the address inputs of the storage device 29. This device stores, at evenly increasing addresses, a sequence of numbers approximating a sinusoidal function in the form of a stepped curve in the interval of change of the argument value equal to a quarter of the period.

As a result of the effect of the code messages of the logic unit 28 on the address inputs of the storage device 29, the latter at their outputs forms the codes of two interlaced sequences of sinusoidal and cosine functions, reproducing them as step curves in the first quadrant (plot 52). This process repeats cyclically as the contents of the (n-2) low bits of the argument counter 27 change (Figure 51).

Codes generated at the outputs of the storage device 29, bitwise, arrive at the first inputs (D-inputs) of the same-named bits of both the first and second buffer registers 33 and 34. The second inputs (C-inputs) of the buffer register 34 are affected by the signals formed at the output of the first logic element 30. Changing their logic levels on the inverter 32, these signals arrive at the second inputs (C-inputs) of the buffer register 33.

The signals acting on the second inputs of the buffer registers 33 and 34 have opposite logic levels, and the phase alternation of the pulse and the pause of both of them changes every quarter of the period due to the fact that every quarter of the period of the generated harmonics the logical level of the signal acting on one of the inputs of the logic element 30 from the side (n-1) of the discharge of the counter 27 of the argument.

Such an organization of influence leads to the fact that the first buffer register 33 is perceived by the memory

7

device 29 is a sequence of codes that reproduce the absolute value of the sine wave, and the second buffer register 34 accepts codes that represent the absolute value of the cosine curve. Moreover, each code value sensed by the buffer registers 33 and 34 is memorized until the next moment of influence on their second pulse inputs of the logic element 30 and inverter 32, respectively. At these moments, a bump converter 35, which is from the moment of the ordinate of the signal 46 at the mapping input 16. In addition to these pulses 47, excites the elements, and the first of these pulses the trigger 38 in the forward state remains unchanged.

A single logical level of 38 transmitted to the input of 42 n modes of operation translates

Fern registers 33 and 34 take 10 adder 37 to the operating mode.

through its first inputs, the next value corresponds to a harmonic signal generated at the output of the memory device 29.

The formation of the absolute value of the cosinusoidal function on the buffer register 34 (plot 55) is illustrated by the coincidence of the unitary logic levels of the output signal of the logic element 30 (plot 54) and the corresponding cosine codes chosen at the same time from the two interleaved code sequences at the output of the memory 29 (plot 52 ).

The formation of absolute sinusoidal harmonic codes (plot 55) on the buffer register 33 is performed similarly when the unit logical signal levels at the output of the inverter 32 and the corresponding sinusoid codes within the signal at the output of the storage device 29 (plot 52) coincide.

15

The code of the measured ordinate of the signal 46 (direct, if it is positive and reverse if it is negative) is generated at the output of the analog-digital conversion of the body 35.

At zero logic level of the signal 47 at the sign input 17 (positive value of the sinusoidal harmonic), the output of the logic unit 36 reproduces the 20 output code of the analog-to-digital converter 35.

With a single logical level of the signal 47 at the sign input 17, the logic unit 36 forms at its output a code opposite to the code generated by the analog-to-digital converter 35.

This is due to the fact that each element of the logic unit 36 performs a logical EXCLUSIVE OR operation.

The delay element 39 triggered by

Signal showing the sign of the sinusoidal side of the control input 18 pulses

harmonics, is formed as a logical signal level of the direct output of the high bit of the argument counter 27. This signal is output to the first sign output 13 of digital block 1.

The signal representing the sign of the cosine harmonic is formed by the second logic element 31 (equivalence), the inputs of which are fed to the direct outputs of the n-th and (n-1) -th bits of the argument counter 27.

The operation of discrete integrators 5 and 6 is illustrated by the example of the operation of the first discrete integrator 5 using the block diagram (FIG. 3) and the graphs shown in FIG. four.

35

45 after a fixed delay time, initiates through the input 41 of the recording an accumulating adder 37, which by virtue of this registers the code generated at the output of the logic unit 36, and adds it to the previously obtained sum of the code values recorded at the previous moments of the signals from element 39 entry delay 41 entries.

Since the input 43 of the transfer of the accumulating adder 37 through the sign input 17 receives signals 47, the logic levels of which reproduce sine-wave harmonic signs in time, the sum is performed by accumulating adder 37 as algebraic. - 45 something, which takes into account both the polarity of the signal, the extrusion of the accumulating adder 37, the zero-stroke of the object 25 of the study, is reproduced in the zero state of the RS-triggered polarity of the signal 46, and the sign

harmonic signal (in this case

38, acting on the input 42 of the switching modes.

The signal 46, representing the product of the output signal of the object 25 of the study by the absolute value of the sinusoidal harmonic, is fed to the information input 16 of the analog-to-digital converter 35.

Each pulse 45 acting on the control input 18 from the side of the first counter 7 initiates an analog-digital

sine wave), reproduced by the logic level of the signal 47.

The delay element 39 performs the time delay before the start of the summation performed by the accumulation adder 37.

This delay is necessary to wait - 55 for the completion of the transient process in the analog-to-digital converter 35.

The second discrete integrator 6 works in a similar way.

eight

Converter 35, which measures the ordinate of signal 46 at its information input 16 at this time. In addition, each of the pulses 47 excites a delay element 39, and the first of these pulses converts the flip-flop 38 into a single state, which forward remains unchanged.

A single logic level of the trigger 38 transmitted to the mode switching input 42 translates the accumulated

adder 37 in operating mode.

The code of the measured ordinate of the signal 46 (direct, if it is positive and reverse if it is negative) is generated at the output of the analog-digital conversion of the body 35.

At zero logic level of the signal 47 at the sign input 17 (positive value of the sinusoidal harmonic), the output of the logic unit 36 reproduces the output code of the analog-to-digital converter 35.

At a single logic level of the signal 47 at the input input 17, the logic unit 36 forms at its output a code opposite to the code generated by the analog-to-digital converter 35.

This is due to the fact that each element of the logic unit 36 performs a logical EXCLUSIVE OR operation.

The delay element 39 triggered by

control input side 18 pulses

control input side 18 pulses

45 after a fixed delay time, initiates through the input 41 of the recording an accumulating adder 37, which by virtue of this registers the code generated at the output of the logic unit 36, and adds it to the previously obtained sum of the code values recorded at the previous moments of the signals from element 39 entry delay 41 entries.

Since the input 43 of the transfer of the accumulating adder 37 through the sign input 17 receives signals 47, the logic levels of which reproduce sine-wave harmonic signs in time, the sum of the summation performed by accumulating adder 37 is algebraic, taking into account the polarity the output signal of the object of study 25, reproduced sine wave), reproduced by the logical level of the signal 47.

The delay element 39 performs the time delay before the start of the summation performed by the accumulation adder 37.

This delay is necessary to wait - 5 the completion of the transition process in the analog-to-digital converter 35.

The second discrete integrator 6 works in a similar way.

9

A device for measuring frequency characteristics performs their determination with high accuracy, since it allows you to measure the required number of ordinates, equivalent to their set located on the interval of one period, and at the same time ensures the use of equipment with a sufficient size of data measurement and transformation.

In addition, the logic of the instrument operation reduces the requirements for the dynamic characteristics of the equipment used (constant measurement times, transformations, and computational operations) without reducing the accuracy of the results.

Claims (3)

1. An instrument for measuring frequency characteristics, containing a digital harmonic generation unit, a digital-to-analog converter whose output is an instrument output, first and second digital-analog multipliers connected by analog inputs to the instrument input, and outputs from the first and second discrete integrators, characterized by the fact that, in order to improve accuracy and) aspirin functional 1P) 1x vozm () the first, the first and second counters are introduced, e.: delay and measurement unit module and phase The first and second inputs and format of the inputs of which are connected to the outputs of the first and second discrete integrators respectively, the sign input of the first discrete integrator is connected to the input of the second counter, the digit input of the digital converter. generation of harmonics connected by a second sign-based signal with a sign input of the second discrete integrator, a pulse output through the first counter - - with the control inputs of the first and second pulse integrators, the first m code output - with digital inputs tsnfroapalogovogo irsobra- zovatel and a first digital to analog multiplier, a second code output from the digital input of the second multiplier tsifroapalogovogo, the output of the second counter via a delay element connected to the control input of the Yu-ilemu modulation and phase measurement. 2. Instrument on n. 1, characterized in that the digital harmonic generation unit contains a clockwise pj-generator TO) argument counter, first logic block, first and second logic elements, memory, inverter, first and second buffer registers, outputs (n-2) low-order bits of n-bit argument counter are connected bitwise to the first inputs of the first logical block , the second inputs of which are connected to the output of the clock generator, the input of the n-bit argument counter, the pulse output of the digital harmonic generation unit and the first input of the first logic element, and the outputs are stored with address inputs connected to the first inputs of the first and second buffer registers, the high bit of the p-bit argument counter is connected to the first sign output of the digital harmonic generation unit and the first input of the second logic element connected by the second input 0 with the output (n-1) of the p-bit argument argument counter and the second input of the first logic element, whose output is the key to the second inputs of the second buffer register and through the inverter to the second inputs of the first buffer register,  the outputs of the first and second buffer registers and the second logic element are respectively the first code, second code, and second sign outputs of the digital harmonic generation unit. 3. The device according to claim 1, characterized by the fact that each discrete integrator contains an analog-digital converter that accumulates an adder, an RS flip-flop, a second delay element, and a second logic block, i the first inputs of which are connected in parallel with the outputs of the analog-digital converter, the second inputs with the sign input of the discrete integrator and the transfer input of the accumulating adder connected by the information inputs to the outputs of the second logic unit, the control input of the discrete integrator is connected with the start input of the analog-digital converter, through the second delay element - with the recording input of the accumulating adder, and with the S input of the RS flip-flop connected by the output to the switching input of the slave modes Since it accumulates across the adder, the information input of the analog-to-digital converter is the informational 1 input of the discrete integrator. five 27 sh 54 I 28 29 ) // // 17 (20) 16 (19 ABOUT J5 5J -0/5 / 5 FIG. 2 6 t 4 j 37 -  / t8 (2i o- FIG. 7 6ut "" 2Gt / l.aЛrlrlлllallllllЛJlJ шJUL JlГJ LI LTLR   if, ft "4 lp lllllllplg shshshllllllllppll g 5 "f. f pJuigldllJVllll jggullJVUulnllllll JgdJg guig g 0 55 Fig 5