US5970432A - Apparatus and method for measuring displacement - Google Patents
Apparatus and method for measuring displacement Download PDFInfo
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- US5970432A US5970432A US08/922,527 US92252797A US5970432A US 5970432 A US5970432 A US 5970432A US 92252797 A US92252797 A US 92252797A US 5970432 A US5970432 A US 5970432A
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- 238000006073 displacement reaction Methods 0.000 title claims abstract description 119
- 238000000034 method Methods 0.000 title claims abstract description 11
- GNFTZDOKVXKIBK-UHFFFAOYSA-N 3-(2-methoxyethoxy)benzohydrazide Chemical compound COCCOC1=CC=CC(C(=O)NN)=C1 GNFTZDOKVXKIBK-UHFFFAOYSA-N 0.000 claims description 2
- 230000000052 comparative effect Effects 0.000 description 8
- 230000004044 response Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000012935 Averaging Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
- G01D5/00—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable
- G01D5/12—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means
- G01D5/244—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing characteristics of pulses or pulse trains; generating pulses or pulse trains
- G01D5/24409—Interpolation using memories
Definitions
- the present invention relates to apparatus and method for detecting (measuring) a displacement.
- two equilibrium modulated signals representing a result of displacement measurement are converted into a phase modulated signal, a period of the phase modulated signal being compared with that of a reference signal so as to detect the displacement of the measured object.
- a difference in period of both phase modulated signal and reference signal represents the displacement of the measured object.
- Previously proposed methods of outputting an interpolation data include: an outputting method of a clock pulse and a direction discrimination signal and an outputting method using a two-bit Gray code (A/B phase).
- the interpolated displacement is achieved for each period of the phase modulated signal.
- the A/B phase is varied at a period of the phase modulated signal multiplied by an integer.
- the A/B phase is varied at a period of a clock inputted into a pulse train converter.
- the clock inputted into the pulse train converter is set such that a frequency of the clock is set to that of the pulse modulated signal multiplied by several tens, namely, a period of the clock is set to that of the pulse modulated signal multiplied by several tenths.
- a movement speed of a scale used to measure the displacement of the object to be measured exceeds a certain speed, a period of the clock pulse is abruptly short, and a phase difference time of the A/B phase signal is abruptly short, and a higher frequency clock is furthermore needed.
- the period of the clock pulse needs to be made shorter so that a processing capability more than necessary is required for a receiving side of the clock pulse and direction discrimination signal.
- a displacement measuring apparatus comprising:
- a reference signal generator for generating a reference signal
- a displacement sensor for generating a displacement signal indicative of a relative displacement of an object to be measured to a reference position at which the reference signal generator generates the reference signal indicating the reference position
- phase modulated signal generator for generating a phase modulated signal indicating a phase difference between the displacement signal generated by the displacement sensor and the reference signal generated by the reference signal generator, the phase difference representing the displacement of the object to be measured with respect to the reference position
- a subtractor for subtracting a period of the phase modulated signal which is converted into a number of pulses of an interpolation clock from that of the reference signal which is converted into the number of pulses of the interpolation clock so as to output a direction signal indicating a direction to which the object to be measured is displaced and output a magnitude of the displacement signal indicating the magnitude of the displacement and which is converted into the number of pulses of the interpolation clock;
- a basic clock generator for generating a basic clock having a predetermined period
- a divider for dividing the period of at least one of either the reference signal or the phase modulated signal which is converted into the number of pulses of the basic clock by the magnitude of the displacement signal which is converted into the number of pulses of the basic clock so as to output a multiplier representing the number of pulses of the basic clock per pulse of the interpolation clock;
- a clock pulse generator for generating a clock pulse having a period corresponding to that of the basic clock multiplied by the multiplier outputted by the divider on the basis of the multiplier;
- a pulse train converter for receiving the magnitude of the displacement signal from the subtractor and for outputting a pulse train signal whose period is derived on the basis of the clock pulse supplied from the clock pulse generator and the magnitude of the displacement signal.
- a method of measuring a displacement of an object to be measured comprising the steps of:
- phase modulated signal indicating a phase difference between the displacement signal and the reference signal generator, the phase difference representing the displacement of the object to be measured with respect to the reference position
- FIG. 1 is a circuit block diagram of a first preferred embodiment of a displacement apparatus according to the present invention.
- FIGS. 2A, 2B, 2C, 2D, and 2E are integrally a signal timing chart for explaining an operation of the first embodiment shown in FIG. 1.
- FIG. 3 is a circuit block diagram of a second preferred embodiment of the displacement apparatus according to the present invention.
- FIGS. 4A through 4G are integrally a timing chart of each signal in the second embodiment shown in FIG. 3 for explaining the operation of the displacement apparatus in the second embodiment shown in FIG. 3.
- FIG. 5 is a circuit block diagram of a comparative example to the first embodiment shown in FIG. 1.
- FIGS. 6A through 6E are integrally a timing chart of each signal for explaining the operation of the comparative example shown in FIG. 5.
- FIGS. 7A through 7E are integrally a timing chart for explaining the operation of the comparative example shown in FIG. 5.
- FIGS. 8A and 8B and 9A and 9B are integrally a signal waveform chart for explaining a displacement.
- FIG. 10 is an explanatory view for explaining a ROM table applicable to a divider shown in FIGS. 1 and 3.
- FIGS. 8 (A) and 8 (B) are, integrally, a case where a period of a pulse modulated signal is longer than that of a reference signal and FIGS. 9 (A) and 9 (B) are, integrally, a case where the period of the pulse modulated signal is shorter than that of the reference signal.
- a difference between the periods of the phase modulated signal and that of the reference signal represents the displacement of an object to be measured.
- FIG. 5 shows the comparative example of an interpolation processing displacement measuring apparatus.
- the phase modulated signal inputted at a terminal T51 is differentiated by means of a differentiator 501.
- the differentiator 501 outputs a pulse on a falling edge of the phase modulated signal to a clear end of an up counter 502, the pulse being inverted by an inverter RV3 and applied to a register 503 and to a preset instruction input end of a (shift) register 503 and a down counter 506.
- the number of the interpolation clocks counted by the up counter 502 represents a value of the period of the pulse modulated signal divided by the period of the interpolation clock.
- the period of the pulse modulated signal is represented by the number of pulses of the interpolation clock.
- An interpolation number setter 504 sets a number of interpolations.
- , in this example, 220-200 20).
- the displacement indicative signal indicates the displacement in a form of the number of pulses of the interpolation clock.
- a down counter 506 is provided with an input terminal receiving the preset instruction, an input terminal receiving a preset data, an input terminal receiving the clock signal, and an output terminal outputting a borrow signal.
- the down counter 506 sets therein the displacement indicative signal (
- the active borrow signal is inputted at one input end of a gate circuit, i.e., a NAND 3 so as to control a passage of a clock signal applied to the other input end of the gate circuit NAND 3.
- a value of the preset data is sequentially, 4, 3, and 3, as shown in FIG. 6 (B).
- the inverted signal inverted through the inverter RV3 and differentiated by the differentiator 501 represents a point of a time at which the phase modulated signal falls. Hence, this point of the time indicates an end of a certain period of the phase modulated signal and also indicates a start of the period subsequent to the certain period so that the preset instruction to the down counter 506 is issued at the start of every period of the phase modulated signal.
- the gate circuit of NAND 3 When the borrow signal is turned on (active), the gate circuit of NAND 3 is opened, the basic clock being supplied from a clock pulse generator 507 being supplied to an A/B phase converter denoted by a dotted line of FIG. 5.
- the turned on borrow signal is also supplied to the down counter 506 to count down the preset value (in this example, four).
- the down counter 506 is synchronized with the basic clock.
- the clock supplied to the A/B phase converter through the gate circuit of NAND 3 is the clock pulses having the same number as the number of the pulses in the interpolation clock corresponding to the magnitude of the displacement and having the period of the basic clock.
- the A/B phase converter includes: first and second flip-flops FF1 and FF2, gate circuits NAND 1 and NAND 2, exclusive OR gates XOR 1 and XOR 2, and an inverter RV1.
- the direction discrimination signal S is inputted to one input end of the XOR 1 and an output end of the XOR 1 is directly inputted to one input end of the gate circuit NAND 1 and to one input end of the gate circuit NAND 2 via the inverter RV1.
- the other input ends of the NAND 1 and NAND 2 receive the clock pulses passed through the NAND 3.
- the other input ends of NAND 1 and NAND 2 receive the clock pulses passed through the NAND 3.
- the received clock pulses serve to invert status of either the flip-flop FF1 or FF2 via a corresponding gate opened according a plurality of the direction discrimination signal.
- An Q output of each of the first and second flip-flops FF1 and FF2 is supplied to a corresponding one of output terminals T53 and T54 as the A phase signal or as the B phase signal.
- the Q outputs of the flip-flops FF1 and FF2 are inputted at input ends of the XOR 2 and an output end of the XOR 2 is connected to the other input end of the XOR 1.
- the clock pulses supplied to the A/B phase converter from the gate circuit NAND 3 via the inverter RV2 are passed alternatingly through the gate circuits NAND 1 and NAND 2 to invert the status of each flip-flop FF1 and FF2 and to output alternatingly inverted A phase signal or B phase signal to the corresponding one of the output terminals T53 and T54.
- FIGS. 7 (C), 7 (D), and 7 (E) show the clock input CP in the A/B phase converter, A phase signal, and B phase signal in the comparative example shown in FIG. 5.
- the number of pulses in the clock supplied to the A/B phase converter via the inverter RV2 are four.
- the Q output of the first flip-flop FF1 is inverted in response to the input of the first pulse of the clock pulses (4), the A phase signal is turned at an "L” (low) level.
- the second flip-flop FF2 is, in turn, inverted in response to the next second pulse of the inputted clock, the B phase signal is turned to an "H” (high) level.
- the first flip-flop FF 1 is again inverted in response to the next third pulse of the input clock, the A phase signal is turned to an "H" (high) level.
- the second flip-flop FF2 When the last fourth pulse is inputted, the second flip-flop FF2 is inverted so that the B phase signal is turned to the "H" level. Thereafter, the Q outputs of the flip-flops FF1 and FF2 are not changed until the arrival of the next period of the clock pulses.
- FIG. 1 shows a first preferred embodiment of a displacement measuring apparatus according to the present invention.
- the subtractor 101 corresponds to the subtractor 505 in FIG. 5.
- the period of the phase modulated signal converted into the number of pulses of the interpolation clock is supplied to one input terminal T1.
- the period of a reference signal converted into the number of pulses of the interpolation clock is supplied to the other input terminal T2.
- the subtractor 101 outputs the direction discrimination signal S indicating the direction of the displacement of an object to be measured (normally, left or right) and outputs the displacement indicative signal converted into the number of pulses of the interpolation clock.
- the displacement indicative signal is supplied to a pulse train converter 103 and to one input end of a divider 105.
- the other input end of the divider 105 receives a signal from a setter 104.
- the setter 104 sets a length of the period of the phase modulated signal converted into the number of pulses in the basic clock.
- the divider 105 divides the set value (1000) by the displacement indicative signal (for example, 2), a quotient (in this case, 500) being preset to a down counter 106.
- the divider 105 divides the period of the phase modulated signal converted into the number of pulses of the basic clock which is the set value of the setter 104 by the displacement indicative signal which is the difference between the periods of the phase modulated signal and the reference signal converted into the number of pulses of the interpolation clock so as to calculate the number of pulses of the basic clock per one interpolation clock pulse.
- the number of pulses of the basic clock per one interpolation clock pulse are calculated on a preset value to a down counter 106.
- the first preset of the down counter 106 is carried out when a differentiated value indicative signal on a falling edge of the pulse modulated signal inputted to a terminal T3 is inverted by an inverter RV4 and is inputted into a preset instruction end of the down counter 106 through an OR gate OR.
- the preset is carried out at the next time whenever the borrow signal is outputted.
- a clock signal is supplied from a basic clock generator 107 to the down counter 106 so that a preset value is decrementally counted.
- a borrow output signal of the down counter 106 is a clock having a period such that the period of the basic clock is multiplied by the preset value and is a clock having the period of the interpolation clock.
- the pulse train converter 103 develops the output pulse train whose number of pulses are in accordance with the clock.
- FIGS. 2A through 2E show the respective waveform charts for explaining the operation of the displacement measuring apparatus in the first preferred embodiment according to the present invention.
- the down counter 103 creates the number of pulses of the basic clock supplied from the basic clock generator 107 so that the count value of the down counter 103 is varied as 3, 2, 1, and 0.
- the preset data at this time is set into the down counter 106. Namely, the count value of the counter indicates four. Thereafter, the same operation is repeated. It is of course the case that if the present value is varied, the numerical value set in the counter 106 is also varied.
- the clock such that a period of a clock signal supplied from the basic clock generator 107 multiplied by the preset data is created and is supplied to the pulse train converter 103 via the OR gate.
- the period of the clock signal generated in the basic clock generator 507 is changed and is supplied to the pulse train converter (A/B phase converter).
- the first embodiment of the displacement measuring apparatus permits the pulse having the period of the basic clock (for example, 1 ⁇ sec.) multiplied by the preset data (500) for each period of the phase modulated signal to be achieved and the period of the pulse can be varied according to the number of pulses outputted as the displacement.
- the pulse train converter 103 fails to output the pulse train and to set the next data so that a defect of data occurs.
- the period a of the basic clock signal is 20 ⁇ sec.
- the number of the interpolations are 400.
- it is necessary to select the period of the interpolation clocks as 20 ⁇ sec. ⁇ 400 0.05 ⁇ sec.
- the result of division is set in the down counter 106 shown in FIG. 1 and is decrementally counted according to the basic clock signal thereat.
- the pulse train converter cannot output the required number of pulses if the next period of the phase modulated signal is 18 ⁇ sec.
- FIG. 3 shows a second preferred embodiment of the displacement measuring apparatus according to the present invention.
- the second embodiment shown in FIG. 3 is conceived.
- the period of the phase modulated signal can be derived as a multiplier of the basic clock period.
- the value of the dividend is varied for each period of the phase modulated signal.
- the differentiator 301, the up counter 302, the register 303, the interpolation number setter 304, and the subtractor 305 with the sign discriminator corresponds to those 501, 502, 503, 504, and 505 shown in FIG. 5. The detailed description will be omitted here.
- the divider 309, the down counter 310, the basic clock generator 311, the pulse train converter 306, the inverter RV4, and OR gate OR correspond to those of 105, 106, 107, 103, RV4, and OR. The detailed description thereof will be omitted here.
- the difference point between the first embodiment described with reference to FIG. 1 and the second embodiment described with reference to FIG. 3 is a circuit portion having a counter 307 and a register 308.
- This combination of the circuits 307 and 308 corresponds to the setter 104 shown in FIG. 1, outputting the ratio between those periods of the reference signal and the basic clock.
- the ratio is fixed in the circuitry shown in FIG. 1, the ratio in the case of the circuitry shown in FIG. 3 is variable.
- a signal from the differentiator 301 is applied to the clear input end of the up counter 307. Since the signal which is inverted from the differentiator 301 is applied to the register 308, the register 308 latches the number of pulses of the basic clock corresponding to one period of the pulse modulated signal.
- FIG. 4A indicates the pulse modulated signal inputted to the input terminal T31 of FIG. 3.
- the displacement at the second stage of FIG. 4B indicates the output of the subtractor 305 and the output signal waveform shown in FIG. 4 B indicates the output of the subtractor 305 and the output signal waveform shown in FIG. 4C indicates the output signal of the basic clock generator 311.
- the quotient of the basic clock divided by the displacement is set to the down counter 310 of FIG. 3.
- the clock shown in the fourth stage of FIG. 4D is outputted at the output end of the OR gate of FIG. 3.
- the period of the basic signal is 20 ⁇ sec. and the number of interpolations is 400.
- the outputted pulse train signal enters the next period before the end of the output of the required number of pulses.
- the result of division falls within the period (18 ⁇ sec.) of the pulse modulated signal and it will be appreciated that it is a sufficient time duration during which the output of the pulse train can sufficiently be provided.
- the period of the pulse modulated signal is 15 ⁇ sec.
- the result of division is 150 ⁇ 100 (whose integer part indicates 1) and the pulse train ends its output at 9. 9 ⁇ sec.
- the pulse train can be outputted at the period of 19.8 ⁇ sec.
- the advantage of the second embodiment is that the period of the pulse train is varied according to the difference in the direction of the period of the pulse modulated signal toward the shortening side or toward the elongating side even if the magnitude of the displacement is the same so that a time averaging is possible.
- ROM Read Only Memory
- FIG. 10 shows the divider using a ROM table.
- the quotient is written onto a memory location designated by these lower and higher order addresses. If the ROM is used, the ROM table performs the same function as the divider prepared in terms of a hardware.
- the phase modulated signal is inputted at the terminal of T31
- the interpolation clock is inputted at the terminal of T32
- the terminal T33 is connected to the A/B phase converter (102 as shown in FIG. 1)
- the terminal T34 is connected to the A/B phase converter (102) as shown in FIG. 1.
- the displacement sensor is exemplified by a U.S. Pat. No. 5,432,443 issued on Jul. 11, 1995, (the disclosure of which is herein incorporated by reference). It is also noted that although the form is different, the A phase and B phase signal are exemplified by a U.S. Pat. No. 4,785,181, (the disclosure of which is herein incorporated by reference).
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Abstract
Description
Claims (16)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP23345996A JP3531375B2 (en) | 1996-09-03 | 1996-09-03 | Displacement detector |
JP8-233459 | 1996-09-03 |
Publications (1)
Publication Number | Publication Date |
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US5970432A true US5970432A (en) | 1999-10-19 |
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Application Number | Title | Priority Date | Filing Date |
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US08/922,527 Expired - Lifetime US5970432A (en) | 1996-09-03 | 1997-09-03 | Apparatus and method for measuring displacement |
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US (1) | US5970432A (en) |
JP (1) | JP3531375B2 (en) |
DE (1) | DE19738528B4 (en) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6466011B1 (en) * | 1998-06-19 | 2002-10-15 | Kabushiki Kaisha Yaskawa Denki | Two-dimensional absolute position sensor |
US6470292B1 (en) * | 1999-08-31 | 2002-10-22 | Sony Precision Technology Inc. | Position detection apparatus |
US6556946B2 (en) | 2000-12-19 | 2003-04-29 | Caterpillar Inc | Linear position sensor |
EP1750099A1 (en) * | 2005-08-03 | 2007-02-07 | CSEM Centre Suisse d'Electronique et de Microtechnique SA Recherche et Développement | Device and method for measuring the relative position of periodic or quasi-periodic marks |
WO2018222441A1 (en) * | 2017-05-30 | 2018-12-06 | Haemonetics Corporation | System and method for collecting plasma |
US10792416B2 (en) | 2017-05-30 | 2020-10-06 | Haemonetics Corporation | System and method for collecting plasma |
US10946131B2 (en) | 2018-05-21 | 2021-03-16 | Fenwal, Inc. | Systems and methods for optimization of plasma collection volumes |
US11412967B2 (en) | 2018-05-21 | 2022-08-16 | Fenwal, Inc. | Systems and methods for plasma collection |
US11837357B2 (en) | 2011-05-18 | 2023-12-05 | Fenwal, Inc. | Plasma collection with remote programming |
US12033750B2 (en) | 2018-05-21 | 2024-07-09 | Fenwal, Inc. | Plasma collection |
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US5299143A (en) * | 1990-09-28 | 1994-03-29 | Kayaba Kogyo Kabushiki Kaisha | Displacement detecting apparatus |
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US5663643A (en) * | 1994-09-30 | 1997-09-02 | Sony Magnescale Inc. | Position detecting apparatus using offset calculated from sum of three-phase signals |
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JPS62200215A (en) * | 1986-02-27 | 1987-09-03 | Mitsutoyo Mfg Corp | Measuring apparatus |
JPH06273194A (en) * | 1993-03-23 | 1994-09-30 | Ntn Corp | Output interpolating circuit for measuring apparatus |
DE69613867T2 (en) * | 1995-01-30 | 2001-10-31 | Sony Prec Technology Inc | Interpolation device |
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- 1996-09-03 JP JP23345996A patent/JP3531375B2/en not_active Expired - Lifetime
-
1997
- 1997-09-03 DE DE19738528A patent/DE19738528B4/en not_active Expired - Lifetime
- 1997-09-03 US US08/922,527 patent/US5970432A/en not_active Expired - Lifetime
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US4131838A (en) * | 1976-09-28 | 1978-12-26 | Toyoda-Koki Kabushiki-Kaisha | Displacement amount detecting device |
US4309702A (en) * | 1978-02-24 | 1982-01-05 | Sony Corporation | Displacement detecting apparatus |
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Cited By (21)
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---|---|---|---|---|
US6466011B1 (en) * | 1998-06-19 | 2002-10-15 | Kabushiki Kaisha Yaskawa Denki | Two-dimensional absolute position sensor |
US6470292B1 (en) * | 1999-08-31 | 2002-10-22 | Sony Precision Technology Inc. | Position detection apparatus |
US6556946B2 (en) | 2000-12-19 | 2003-04-29 | Caterpillar Inc | Linear position sensor |
EP1750099A1 (en) * | 2005-08-03 | 2007-02-07 | CSEM Centre Suisse d'Electronique et de Microtechnique SA Recherche et Développement | Device and method for measuring the relative position of periodic or quasi-periodic marks |
US11837357B2 (en) | 2011-05-18 | 2023-12-05 | Fenwal, Inc. | Plasma collection with remote programming |
US11738124B2 (en) | 2017-05-30 | 2023-08-29 | Haemonetics Corporation | System and method for collecting plasma |
WO2018222441A1 (en) * | 2017-05-30 | 2018-12-06 | Haemonetics Corporation | System and method for collecting plasma |
US10758652B2 (en) | 2017-05-30 | 2020-09-01 | Haemonetics Corporation | System and method for collecting plasma |
US10792416B2 (en) | 2017-05-30 | 2020-10-06 | Haemonetics Corporation | System and method for collecting plasma |
US10980934B2 (en) | 2017-05-30 | 2021-04-20 | Haemonetics Corporation | System and method for collecting plasma |
US10980926B2 (en) | 2017-05-30 | 2021-04-20 | Haemonetics Corporation | System and method for collecting plasma |
US11097042B2 (en) | 2018-05-21 | 2021-08-24 | Fenwal, Inc. | Systems and methods for optimization of plasma collection volumes |
US11285251B2 (en) | 2018-05-21 | 2022-03-29 | Fenwal, Inc. | Systems and methods for optimization of plasma collection volumes |
US11369724B2 (en) | 2018-05-21 | 2022-06-28 | Fenwal, Inc. | Systems and methods for optimization of plasma collection volumes |
US11383013B2 (en) | 2018-05-21 | 2022-07-12 | Fenwal, Inc. | Systems and methods for optimization of plasma collection volumes |
US11412967B2 (en) | 2018-05-21 | 2022-08-16 | Fenwal, Inc. | Systems and methods for plasma collection |
US11730873B2 (en) | 2018-05-21 | 2023-08-22 | Fenwal, Inc. | Systems and methods for optimization of plasma collection volumes |
US11110216B2 (en) | 2018-05-21 | 2021-09-07 | Fenwal, Inc. | Systems and methods for optimization of plasma collection volumes |
US11801001B2 (en) | 2018-05-21 | 2023-10-31 | Fenwal, Inc. | Systems and methods for plasma collection |
US10946131B2 (en) | 2018-05-21 | 2021-03-16 | Fenwal, Inc. | Systems and methods for optimization of plasma collection volumes |
US12033750B2 (en) | 2018-05-21 | 2024-07-09 | Fenwal, Inc. | Plasma collection |
Also Published As
Publication number | Publication date |
---|---|
JPH1078315A (en) | 1998-03-24 |
JP3531375B2 (en) | 2004-05-31 |
DE19738528B4 (en) | 2007-02-08 |
DE19738528A1 (en) | 1998-07-02 |
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