SU397920A1 - DEVICE FOR MEASURING THE RELATIVE DIFFERENCE OF TWO HARMONIC SIGNALS - Google Patents

Description

The proposed device relates to the field of computer technology and can be used in the control and adjustment of elements and assemblies of rad devices. Devices are known for measuring the displacement difference of two harmonic signals, comprising a switch connected via a linear detector to a first input of a controlled voltage divider connected to a voltage converter in a number of pulses, as well as a clock generator and a counting unit. The known devices do not have sufficient speed and are suitable for operation only in the range of relatively high frequencies. The aim of the invention is to expand the frequency range of the input signals and improve the speed of the device. This goal is achieved due to the fact that the device additionally includes a reversible pulse counter, a register, logic circuits "AND and." NOT, as well as a counter of clock pulses, the input of which is connected to a clock generator connected through the first circuit "And with the IEE. DOM voltage converter in the number of pulses. The high-end outputs of the counter are connected to the control inputs of the switch and the reversible counter, the counting input of which is connected to the output of the voltage converter in the number of pulses, the code outputs of the reversible counter are connected to the input of the reference block and the code inputs of the register. The register output is connected to the second input of the controlled voltage divider. The register overwriting input is connected to a pulsed output of a lower-order counter of clock pulses. The unit outputs of the bits of this counter are connected to the inputs of the second AND circuit, the output of which is connected to the control input of the reference block and through the NOT circuit with the control input of the first N. The drawing shows a block diagram of a device for measuring the relative difference of two harmonic signals. The device contains a switch}, a line detector 2, a controlled voltage divider 3 (meter, pa digital control resistance), a voltage converter 4 in the amplitude number, a reversing pulse counter 5, a register 6, a clock counter, performed on the trigger 7 and S, the circuit “And 9 and 10, the circuit“ NOT //, the clock generator 12 and the digital block of reference J3. In the initial state, the reversible pulse counter 5 is set to zero, the register 6 is in the state 1000 ..., as a result of which

The division factor K of the controlled voltage divider 3 is equal to one (Ka is controlled by the code recorded in register 6). Triggers 7 and S are set to one.

The measurement takes place in three cycles.

In the first cycle, after the arrival of the first pulse from the clock generator, the triggers 7 and S go to state 00. The switch /, controlled by trigger 7, connects the voltage t / i to the input of the linear detector, and the counter 5 is converted to Press “add. The same impulse of the generator 12, the gate passed (circuit “AND 10), starts the converter 4, which converts the voltage U into the number of pulses nl K.U, (where KI-coefficient is preo; b, development of the linear detector 2). This number of pulses is recorded in counter 5.

With the arrival of the second clock pulse from the generator 12, the trigger 8 is transferred to a single state. The voltage drop from its zero output affects the register overwriting input 6. As a result, the P 3 code of counter 5 is transferred to register 6, and the counter K is reset to zero.

In the controlled voltage divider, the division factor Ku KiO is set (where p is the proportionality coefficient). The voltage f / i is again converted to the number

; one

P2 A1 pulses - which is fixed

counter 5.

The third pulse of the generator 12 transfers the trigger 8 to the state O, and the transfer pulse from its single output transfers the trigger 7 to the state 1. At the same time, the switch 1 connects the voltage f / 2 to the output of the linear detector 2, and the counter 5 is switched to mode "subtraction. Voltage Uz is converted to the number of pulses.

Cd

the number of pulses is subtracted from the contents of counter 5, i.e. from p. As a result of performing three measurement cycles, a code is recorded in a reversible counter.

 1 U-, - U,

a - "g - Dz -.

With the arrival of the fourth pulse from the generator 12, the triggers 7 and 8 take state 11, the signal from the output of the circuit "And 9 turns on the digital block of reference 13. Moreover, the same signal through the circuit /" NOT // locks the gate (circuit “And 10), impeding the launch of the converter 4.

Thus, the proposed 1ZI | FIR meter for measuring the relative difference of two harmonic signals provides a measurement for three conversion cycles with high accuracy determined by the accuracy of the resistors of the controlled voltage divider.

Subject invention

A device for measuring the relative difference of two harmonic signals, comprising a switch connected via a linear detector to the first input of a controlled voltage divider connected to a voltage converter in a number of pulses, a clock generator and a reference block, characterized in that expanding the frequency range and increasing speed, it contains a pulse counter named after pulses, a register, logic circuits "AND and" NOT, as well as a clock pulse counter whose input is connected to a clock generator an atom connected through the first circuit "And to the input of a voltage converter in the number of pulses; The high-voltage outputs of the counter are connected to the control inputs of the switch and reversible counter, the counting input of which is connected to the output of the voltage converter in the number of pulses; the code outputs of the reversible counter are connected to the input of the reference block and to the code inputs of the register; the output of the register is connected to the second input of the controlled voltage divider; The register overwriting input is connected to the zero output of the low-order bit of the clock counter and pulses, and the unit outputs of the bits of this counter are connected to the inputs of the second AND circuit, the output of which is connected to the control input of the reference block and through the NOT-control .m. the input of the first circuit ".and.

one

and,

.