SU1277083A1 - Device for entering analog information - Google Patents

Abstract

The invention relates to the field of number technology and is intended to input analog values into a computer. The aim of the invention is to increase the speed and accuracy of the amplitude-phase processing of analog information. A device for inputting analog information is complemented by a block for allocating quadrant samples of the same name, the accuracy of which, at the corresponding ADC resolution, reaches .0.1% in the relative frequency band of ± 17% and 1% in the relative frequency band of ± 30%. 1 hp f-ly, 2 ill.

Description

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The invention relates to computing technology and can be used in automated control systems and technological processes and measurements for entering information about the parameters of objects, presented as analog values, into an electronic computer.

The aim of the invention is to increase the speed and accuracy of the amplitude-phase processing of analog information.

FIG. 1 is a block diagram of the device} in FIG. 2; a block diagram of a block for extracting simultaneous quadrature quadrature components,

The device contains a switch 1 channels, an analog-digital converter 2, a block 3 for allocating simultaneous quadrature samples, a register 4, a block 5 for control, a block 6 for comparison, a block 7 for match, a timer 8, a block 9 for memory, a switch 10 for input 11 external synchronization signal, information inputs 12 and 13 of the block B; Along the simultaneous quadrature component counting, the first control output 14 of the timer, the first control input 15 of the timer, the information input 16 and 17 of the timer, the second control output 18 of the timer, the second control yu move 19 timer, third control input 20 timer, third control; Start timer 21, fourth control input 22 timer, fifth control input 23 timer, information outputs 24 and 25 of the switch, information inputs 26 and 27 of the first group of switch, information inputs 28 and 29 of the second switch group, information inputs 30 and 31 of the first register, first register 32, operational memory 33j arithmetic unit 34, multiplexer 35, second register 36, information inputs 37 and 38 of the second group of device, information inputs 39 and 40 second arifmetikologicheskogo block group, data inputs 41 and 42 of the first group arifmetikologicheskogo unit data outputs 43 and 44 arifmetikologicheskogo unit, data inputs 45 and 46 of the first group 47 and second group 48 and multiplexer 35, data inputs 49 and 50 of the second re770832

gist control outputs 51-67 timer groups.

The device operates in two main modes: with internal synchronization and with external synchronization,

Each main mode contains three sub-modes: input on request from a computer, input of groups of parameters with consecutive addresses and input of separate parameters.

When operating in the first sub-mode of the first main mode, the device receives from the computer a readiness signal of the computer to the input of the control unit 7, which generates a signal from the readiness of the device and output synchronization using this signal. In response to these signals, the input of the memory block 9 receives the mode code . By signal Recording from the block 7 of the interface, information is recorded, After the signal is removed from the readiness of the computer, the block 7 of the interface generates a measurement signal arriving at the input of the block 5 of the control. On this signal, the control unit 5 generates a memory overwrite signal. The latter is fed to the input of the memory 9 memory,

30 after which information is copied from memory block 9 into control block 5. Then, the control unit 5 generates a signal Connecting the channel on which the switch 1

35 connects to analog-digital input

converter 2 corresponding

.channel, timer 8 signaling

Sensor Type (67), Signal Type

the sensor is switched

The 4Q inputs and outputs of the quad sampling unit are such that, in the case of a video signal sensor, a structure equivalent to the type is restored.

The measurement is performed on the Start signal coming from the output of the control unit 5 to the input 19 of the timer 8,

so In the case of a video signal sensor, the Start runs through timer 8 and through output 14 is fed to the input of analog-digital converter 2, which generates a signal from the end of digitization, fed to the input 15 of the timer. The passage of timer 8, the signal. The end of digitization through the output 18 affects the control unit 5. 3 According to this signal, control unit 5 generates a data entry signal, which is received via timer 8 (input 20, output 21) to input of interface unit 7 and is converted into a signal of the recording box that controls the recording of information E, the buffer register 4, then block 7 however, the device does not generate a Ready signal. Thus, the information is ready for input into the computer and is inputted by the corresponding signal. In the case of pa, a diometric sensor based on the Start signal, input from the output of the control unit 5 to the input 19 of timer 8, the analog-digital converter 2 starts eight: times. Glapusk signals. an analog-to-digital converter is generated at the output 14 of the timer. The input signal samples are recorded in the operational memory (FIG. 25, block 33) of the sample extraction unit — the preset components X and are used further in it to calculate the sighed and cosine quadrature components D1X. After finding and recording the sinus quadrature component in the output register (FIG. 2, block 36) of the block for separating quadrature components from the output 21 of the timer. Data input is generated, to which the interface unit 7 responds in the same way; as in the case video signal sensor. After the end of the first signal, the device is ready forged by the interface unit 7 and is fed to the input 22 of the timer and the cosine quadrature component, the latter is written into the input register 36, and a second signal is generated. Data input The end of the second signal device availability is a sign of the beginning signal generation The end of digitization, which goes through output 18 to control unit 5 and is moving to the next channel, enters information from other channels in a similar way; The first: kim first mode is characterized in that the first and last addresses of the parameters are stored in memory block 9. At the same time, in the comparison unit 6, the code of the last address of the group of parameters supplied to the inputs of the comparison unit 6, 83 memory blocks 9 is compared with the current address of the measured parameter coming from the control unit 5. In case of equality from the comparison unit 6, the control unit receives a signal. Comparative Heirae, The device waits for a request signal from the computer. The third submode of the first main mode differs from the second one. mma in that the addresses of individual parameters are recorded in memory block 9, the second main mode differs from the first main mode in that the control unit 5, generating a trigger signal, provides the input synchronization pulse to the timer output 14 (in the case of a remote sensor ) and further to the input of the analog-digital converter, i.e., the time moments of sampling are now determined by the sync pulses, All podr; 1O1s of the second main mode are otherwise reacted similarly to the first main mode. Before examining separately the operation of the block for simultaneous sampling of quadrature 1x samples, the block diagram of which is shown in FIG. 2, stop briefly on the features of the output signal of the radiometric sensor. In general, the output signal of the radiometric sensor can be represented as follows: x (t) A (t) cos Wot-4 (t) l A (t) cos (t ) sin, (I) where A (t) A (t) Mcos (t); . Ag (t) A (t) 4sin (t); A (t) is the signal amplitude; 4 (t) - signal phase; W is the central circular frequency (it is known for sure); t — current A (t) —sinus quadratic component; A (t) is the cosine quadrature component, Optimal alapog selection Aj, (t) and A (t) is carried out according to the principle known in the literature (see, Vakman D. Its About the best realizability of the ith approximation to the Hilbert converter, - Radio engineering and electrical engineering 1976, No. 7, pp. 1417-1426, Fig. 2), Digital algorithms for calculating quadrature components are described in the article by Arro I.O. Discretization of the band-pass signal: proceedings of the Tallinn Polytechnic Institute, 1982 No. 540, p. 3-9, Proceeding from the indicated literature, it can be argued that if we take x (t) from the abacus through the TG time interval and designate them as x (n) x (t), where,, 2.,., Then by seven counts you can define AZ () and AJ, () according to the following formulas: Hell () -2x (4), (2) A () x (5) -x (3) + 0, I25ex (7) -x (l ) J (3) It is formulas 2 and 3 that form the basis for calculating the simultaneous counts of quadrature components in the corresponding block. Note that the specific ratios for calculating the quadrature components depend on the properties of the signal x (t) and the required conversion accuracy. The above ratios provide an accuracy of 0.1% in the relative frequency band tl7% and 1% in the relative frequency band ± 30%. At the same time, the conversion error has a monotonic dependence on the detuning. The block of selection of samples of quadratic components functions as follows. After power is turned on, timer 8 takes the initial state. By Sense Measurement begins the countdown in the form of invariant time intervals. Signal Channel connection, arriving at inputs 16 and 17 of the timer, sets its output 67 high: the radiometric level, and zero if the video sensor, In the case of a high level, the switch 10 switches to its outputs 24 and 25, inputs 28 and 29, The Start signal (input 19) will start the analog-digital converter generating pulse generation system, which is post-output to output 14. On each trigger pulse, after removing the reference, an analog 836 th digital converter 2 generates a signal. Digitization end ADC, In time On the basis of this signal, the control signals for recording and storing the input data of register 32 (signals 51 and 52), as well as rewriting into the operational memory 33 (signal 53 - 57) are generated. Accepting the eighth signal. The end of the digitization of the ADC stops the further start of the analog-digital converter, and timer 8 converts the blocks 33 to 35 to the quadrature -computing mode. After calculating the sinus quadrature component A, it is written to output register 36, and output 21 is generated The data input signal, which is received by the interface unit 7, the interface unit 7, provides the transmission of A, just as in the case of the video signal sensor, that is, the data transmission is accompanied by a device Ready signal, tory input to timer 22, 8, simultaneously with the transmission process A calculating unit counts kvadS-temperature constituent computation continues. After the calculation is completed, the cosine quadrature component of the AC and the Ready Device signal At are transferred to the output register 36, and a second Data input signal is generated at the output 21. By the end of the second signal. Device availability ends the generation of simultaneous samples of the quadrature components of the signal at the input of the analog-to-digital converter, which is notified to the signal control unit 5. The digitization end arriving at output 18. Now the block of the quadrature samples readings can be used before re-digitizing the same channel (new signal Start), or DNP of the next (new signal Channel connection and Start), from the moment the signal is received Measurement (high level) at input 23 n chinaets countdown in the form of invariant time slots The signal connection 16 and the channel 17 is formed by a signal detector 67 Type 7, specifically defined by the channel number. ; In the case of a video signal sensor at output 67, a high level occurs, under the influence of which timer 8 switches the outputs 21, 14 and 18, input 19, and switch 10 establishes the connection between inputs 28 and 29 and outputs 24 and 25. Inputs 16 and 17 are switched. Now the Start signal (input 19) provides the generation of impulses of the invariant time shift. The first pulse, which contains an invariant moment of time, generates a pulse of starting the analog-digital converter at the time of invariance of the time reference and arrives at output 14. In response to the trigger pulse, the analog-digital converter generates a signal. A high-level digitizing pulse arrives at input 15 and generates a signal 52, which opens the input keys (AND circuits) of the input register 32, data is written from input 30 and 31 to the input register at the moment of the end of the pulse. The digitization end of the ADC, The second is transmitted to block 32 via output 51. To overwrite information from input register 32 into random access memory 33 by signal End of digitization of ADC, timer 8 sets the data address at outputs 53 to 55. Overwriting occurs under the influence of low level at outputs 56 and 57, A low level at the outputs 56 and 57 is formed from the moment of arrival of the signal. Start until the arrival of the first signal. Digitization end of the ADC (address - all zeros). The address in this case is determined by the number of received signals. The end of the digitization of the ADC, which is fixed by the timer, the process of starting the analog-to-digital converter, the reception of the signal. The end of the digitization of the ADC, writing data from input 30 and 31 to register 32 and re-writing to RAM 33 repeated eight times. The eighth signal. The end of digitization. The ADC sets a high level at outputs 51 and 57, i.e. no entries are made in registrar 32 and rewrites into the operational 838 memory of the eighth reference. At outputs 53 - 55, an address is created to write data to the RAM 33. Thus, the computation firmware of the quadrature components A and A is started (Formulas 2 and 3), Timer 8 sets the address of the RAM word 33 (outputs 53 - 55 ), the operation code of the arithmetic unit 34 (outputs 58 61), the transfer value of the lower bit of the arithmetic logic unit (output 62). The specific values of the word timer 8 at outputs 53-55 and 58-62 are shown in the table. The first half of the clock period goes to the establishment of the address of the RAM 33 and the operation code of the arithmetic logic unit. Data at the output of the RAM 33 and, respectively, at the inputs 41 and 42 of the arithmetic logic unit 34 is available during the second half due to the low level at the output 56. The result of the operation of the arithmetic logic unit is fixed in the multiplexer 35 at the moment of transition from high to low the signal that occurs at output 64. To explain the calculation, the following symbols are entered: A - inputs 39 and 40, B - outputs 41 and 42, F - outputs 43 and 44,. During the first clock cycle, the output F is the value 0, which is written to the multiplexer 35. During the second clock cycle, A f, B x (4) and F A - B – x (4). The third clock: A - x (4), + A -2x (4) AJ, This result must be converted to register 36. To do this, at the moment of arrival of the fourth clock pulse, output 66 is high and unlocks inputs 49 and 50 of register 36, The ACS output register 36 is recorded at the moment the pulse arrives at output 65 at register 36 input. The pulse must be less than half of the clock period. The arrival of the fifth clock implies switching the output 65 back to a low level and thus inputs 49 and 50 output register 36 block

signal 66, and it goes into the mode of storing and transmitting information, i.e. recorded quadra component A. there are outputs 24 and 25,

A Signal Input signal is generated, which is fed to output 21. Interface Block 7 responds to this signal as well as in the case of a video signal sensor, i.e. ensures the transfer of data to the register 4, which is accompanied by the generation of the readiness signal of the device, which through the input 22 enters the timer 8,

Consider how the cosine quadratic component is calculated.

Fourth cycle: F (, Fifth cycle: A 0, B x (5), F A + b

- x (5). The sixth cycle: A x (5),

B x (7), F A + B x (5) + x (7). Seventh cycle: A x (5) + x {7), B x (1), F A - B x (5) + x (7) x (1). The eighth cycle: A x (5) + x (7) x (1), B x (3), F A - B x (5) + + x (7) - x (1) - x (3),

The start of the eighth clock cycle also marks the beginning of the occurrence of a high level at output 63, which is protected until the ninth clock pulse arrives. This pulse enters through the output 63 to the input of the multiplexer 35 and switches the inputs 47 and 48 to the output 49 and 50 with a shift to the right by three bits, t, e. this is done by the delegate by eight at the time the data is written to the block register 36, when the signal 64 goes from high to low.

The ninth measure: (5) +: + x (7) -x (1) -x (3) E, (5), +. + In E + x (5). Tenth cycle: A. Е + х (5), В х (3) А А - В Е + х {5) - х (3) А, Eleventh cycle: А А, F А, which blocks the formation of clock pulses Timer 8, High level appears at output 56, Output signals 66 and 65 are then formed, which provide a rewriting of the cosine quadrature component A ,, from multiplexer 35 to output register 36. Note that it is affixed in block 36 before the eleventh clock pulse, while forming a pulse, which at output 21 gives a signal to enter data,

7708310

Now the signal. The readiness of the device from input 22 passes through teymer. The generated output pulse arrives at output 18; Thus, the digitizing signal is generated at output 18. Thus, the timer 8, as well as the entire quadrantx sample allocation unit, is reset. With

10 restarting at input 19, the entire cycle is repeated.

The proposed device opens up fundamentally new processing possibilities in an instant:) 1x values of the complex signal envelope, including high-frequency phase processing. The device can be used in measuring and radio systems, in which high speed is required and

20 accuracy of the amplitude-phase processing of the input analog signal,

Claims (1)

Invention Formula 25 1. Device for input of analog information containing a multiplexer, analog-digital converter, register, control unit, comparison unit, interface unit, memory unit, first and second control inputs of the interface unit, information inputs of the memory unit , the information inputs of the multiplexer are the first and second control inputs, the information inputs 35 mi of the first and second device groups, respectively, the first and second control outputs of the interface unit, the information outputs of the register are the first and second managers and  information outputs of the device, respectively, the third and fourth control outputs of the interface block are connected to the first and second control inputs of the register, the fifth and 5, the sixth control outputs of the interface block are connected to the first control inputs of the control block and the memory block, respectively, the information outputs of the memory block are connected to the information inputs of the memory block and to the information inputs of the first group of the comparison block, the information inputs of the second group of which are connected to the informational outputs of the first group of the control unit, the output of the comparator is connected to the second control input of the control unit, perII the control output of which is connected to the second control input of the memory unit, the information outputs of the second group of the control unit are connected to the address inputs of the multiplexer, the output of which is connected to the information input of the analog-digital converter, tl and h. So that, in order to increase the speed and accuracy of the amplitude-phase processing of analog information, a block for simultaneous quadrature components counting, a switch, a timer, information outputs of the analog-digital converter are connected to the information inputs of a block of simultaneous of quadrature component counts and information inputs of the first switchboard group, the information outputs of the quadrature sample allocation block are connected to to the secondary inputs of the second group of the switch, the information outputs of which are connected to the information inputs of the register, the control outputs of the timer group are connected to the control inputs of the block for the simultaneous sampling of quadrature components, the first, second and third control outputs of the timer are connected respectively to the control input of the analog the digital converter, to the third control input of the control unit and to the third control input of the interface block, the control output of the analog-digital converter Tre7708312 The second and the second control outputs of the control unit, the second and fifth control outputs of the interface block are respectively connected to the first to the fifth to the control inputs of the timer, the sixth control input of the timer is the clock input of the external synchronization of the device, the fourth control output of the timer connected to the control input of the switch. 2, the apparatus according to claim 1, characterized in that the block for extracting simultaneous quadrature samples. The components contain two registers, a RAM, an arithmetic logic unit, a multiplexer, control inputs of the first and second registers, a RAM memory, an arithmetic logic unit, and a multiplexer; the control inputs of the first register are the information inputs of the block, the information outputs of the first register are connected to the information inputs of the main memory, the information outputs of which are connected to the information inputs of the first group of the arithmetic logic unit, information outputs of which are connected to information inputs of the first and second groups of the multiplexer, information outputs of which are connected to information inputs of the second register and information inputs of the second group of the arithmetic logic unit, information outputs of the second register are information outputs of the block, Baseline About 1 1 o eleven 1 1 1 1 about Oh oh 1 about o one 0101 1101 about 1 one one about about 1 about about 1 oh oh about about 1 about 1 about one oh oh oh oh about 1 oh oh sh W 2B /  I i, 1 niuiuii / "/ 5 ff / 7/5 GE 20 21 22 23 FIG. 2