SU1591020A1

SU1591020A1 - Device for monitoring pulse sequences

Info

Publication number: SU1591020A1
Application number: SU884615892A
Authority: SU
Inventors: Vyacheslav S Kharchenko; Grigorij N Timonkin; Andrej G Zolotarev; Sergej N Tkachenko
Original assignee: Vyacheslav S Kharchenko; Grigorij N Timonkin; Andrej G Zolotarev; Sergej N Tkachenko
Priority date: 1988-12-05
Filing date: 1988-12-05
Publication date: 1990-09-07

Description

The invention relates to computing and can be used to control complex analog signals. A distinctive feature of the device is that it allows you to provide

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control of complex analog signals of arbitrary shape and duration, arriving at the device input; parallel processing of the monitored signal; the ability to change the required accuracy of control. The aim of the invention is the extension of functionality due to the control of complex analog signals. This goal is achieved by introducing the decoder 4, block 5 comparison, trigger 6, a group of elements OR 7, block elements And 8, analog-to-digital Converter 9, trigger 10, one-shot 11, element OR 12, trigger 13, generator 14 clock pulses, odnonibratorov 15, 16, element And 17. 2 Il.

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The invention relates to automatic- Trigger 6 (end of control) serves

ke and computer technology and can be used to control complex analog signals at the inputs of the device from the objects ^{5 of the} control in the process of their control and testing.

The purpose of the invention is the extension of functionality due to the control of complex analog signals.

Ia figure 1 presents a functional diagram of the device; FIG. 2 is a time chart of the operation of the device.

The device contains a counter 1, block 2 permanent memory, register 3, decoder 4, block 5 comparison, trigger 6, a group of elements OR 7, a block of elements AND 8, analog-to-digital converter 9, trigger 10, one-shot 11, element OR 12, trigger 13, generator 14 clock pulses, one-shot 15 and 16, element And 17, 25

a group of 18 inputs of the monitored sequences, an input 19 of the start, a group of inputs 20 of the number of the monitored sequence of the device, an output 21 of the monitored sequence and an output 22 of the end of the device operation,

Counter 1 is designed for addressing memory block 2. The recording of the starting address from the input 20 is performed on the falling edge of the signal from the output of the one-shot 15, and the pulse counter is organized at the input "+1".

Memory block 2 is used to store and output information about the value of the monitored signal and the required / accuracy of comparing the value of the input signal of the signal with the reference and the end of the command. Register 3 is designed to receive, store and issue information about the level of the input signal of the device.

The decoder 4 is designed to convert the positional code arriving at its inputs, carrying information about the number of masked digits of the incoming level of a complex signal, into a unitary code. The comparison unit 5 compares the value of the complex signal level code input to the device with its reference value stored in memory block 2.

for receiving, storing and issuing information about the end of control of a complex signal. The device modifies until the trigger 6 is turned on (end of control) in one state only in the case of each correspondence of a complex signal to a reference value. The group of elements OR 7.1, ..., 7.N-1 is intended for masking bits of the value of the level of a complex signal.

The block of elements And 8 directly implements this masking, Analog-to-digital converter 9 is designed to convert an analog complex signal input to a device into a discrete one.

The trigger 10 of the result of the control serves to memorize the result of the control (positive or negative). The one-shot 11 is designed to form a pulse that ensures the device to stop in case of a negative control result (a discrepancy between the value of a complex signal and its reference value stored in block 2 of the memory).

The element OR 12 is designed to generate a pulse that stops the device either in the case of a negative control result, or in the case that all the levels of a complex signal _} correspond to the moments of its sampling coincide in time with its reference value stored in memory block 2. This corresponds to the moment of issuing the "End command" signal from memory block 2. The trigger 13 (start) is designed to start the device. The generator 14 clock pulses produces two time-shifted sequences of clock pulses that synchronize the operation of the device. The one-vibration 15 is designed to generate a pulse that synchronizes the operation of the counter 1 at the time of launching the device. ·

The one-vibration 16 generates a pulse, which provides a stop of the device at the moment of issuing the signal "End of command" from memory block 2. Element And 17 is designed to inform the user about the end of the command, i.e. correctness of the complex signal that came to the device input.

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The device works as follows.

At the initial moment of time the trigger 13 is started, the trigger 6 of the end of control 10 of the control result, the register of 3 values of the monitored signal and the counter 1 of the micro-command addresses are in the zero state. The reset circuits are not shown.

When a single potential is applied to the device input 19, a one-shot 15 is triggered. On the falling edge of each single pulse generated by the one-shot 15, the microcommand addresses of information received at its information inputs (information about the number of the monitored signal being monitored) are recorded into the counter 1. This information from the outputs of counter 1 is fed to the address inputs of memory block 2, thereby determining the address of the first microcommand for the microprograms for monitoring this complex signal.

In addition, a single potential applied to the input 19 of the device translates the trigger 13 into a single state. A single potential from the direct output of the trigger 13 is fed to the input of the generator 14 clock pulses and turns it on.

On the falling edge of the first clock pulse coming from the first generator output of 14 clock pulses to the register recording resolution input, the value of the complex signal level is recorded in the first sampling interval (the signal is converted from analog to digital form by analog-digital converter 9).

After the information about the address' first microcommand arrives at the address inputs of memory block 2, the first microcommand of the device operation appears on its outputs. In this case, the microinstruction is divided into three fields. The first field 2.1 sets the control accuracy, i.e. the number of masked (not controlled by the lower-order) bits of the level of a complex signal entering the device at the time of sampling. The second field 2.2 carries information about the reference value of this complex signal at the moment of discretization. The third field is 2,3, represented only

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one bit of information, carries information about the end of the execution of the command. >

Information about the number of masked bits of the monitored signal from field 2.1 of the microcommand of memory block 2 is fed to a group of inputs of the decoder 4. The decoder 4 converts the positional code into a unitary code that appears on its outputs. A single potential from one of the outputs of the decoder 4 (the number of maximized digits) goes to one of the second inputs (Ν-1) of the elements of the group: OR elements 7.1, ..., 7.Ν-1 or to the higher input from the second group of inputs of the element block And 8. If the unit potential arrives at the input of the ίth element OR from the group of elements OR 7.1, ..., 7.N-1, then a unit appears at its output, which, in turn, goes to the first input (ι- 1) -γο element OR and translates it into a single state, what happens with all subsequent elements OR to the first. The unit potentials from the outputs of the group of elements OR 7 are fed to the second group of inputs of the block of elements AND 8. A similar situation occurs when a single potential appears at the higher output of the decoder 4.

Thus, a certain: number

honestly single potentials, arriving at the second group of inputs of the block of elements And 8, marks a certain number of bits entering the first group of inputs of the block of elements And 8 from the group of outputs of the register 3.

40 At the same time at the outputs of the And 8 block of elements there is information about the value of the complex signal at the moment of sampling. This information goes to the second group of inputs of the comparison unit 5, to the second group of inputs ko-. information about the reference value of the complex signal at the moment of sampling from the field

2.2 memory block 2,

If these two values are equal, a logical "0" signal appears at the output of the inequality of the comparison block 5.

On the falling edge of the first clock pulse coming from the second output of the generator 14 clock pulses to the clock input of the trigger 10, the content of the counter 1 is increased by one and recorded in the trigger

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ger 10 logical "0", indicating the coincidence of the signal value with its reference value.

As the contents of counter 1 is increased by one, the memory unit 2 is redirected to the second micro-command of the complex signal control firmware.

Further operation of the device occurs according to the law, functioning.

In case the value of the monitored signal entering the device input does not coincide with its reference value stored in memory block 2, a unit appears at the output of comparison block 5. On the falling edge of the next sync pulse coming from the second generator output 14 sync pulses to the trigger trigger trigger 10, this unit is written into trigger 10.

The single potential from the direct output of the trigger 10 is fed to the input of the one-shot 11, which at the same time forms a shortened pulse at its output. A single pulse from the output of the one-shot 11 enters the first input of the element OR 12 and translates it into a single state. The unit potential from the output of the element OR 1.2 enters the reset input to the zero of the trigger 10 and transfers it to the zero state, thereby preparing it for further work, and to the reset input to the zero of the trigger 13, converts it to the zero state. The zero potential from the output of the trigger 13 is fed to the input of the generator 14 clock pulses, and turns it off. This stops the device.

In the case when the complex signal received at the device input fully corresponds to its reference value, a single potential appears at the end of the monitoring microprogram at the output 2.3 of memory 2.

On the falling edge of the next sync pulse arriving at the sync trigger of trigger 6, this unit potential translates ₁ trigger 6 into a single state.

The unit potential from the direct output of the trigger 6 is fed to the second input element And 17, at the first input of which there is a single potential coming from the inverse output of the trigger 10. Thus,

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the element And 17 is translated into one state, and the unit is absent at the output 21 of the device, which indicates the correctness of the complex signal received at the input of the device.

In addition, the unit from the direct output of the trigger 6 is fed to the input of the one-shot 16. A single pulse from the output of the one-shot 16 passes through the OR element 12 and enters the reset input to the zero of the trigger 13. The zero level from the direct output of the trigger 13 is fed to the input of the generator 14 clock pulses and turns it off. Thus the device stops.

Claims

Claim

A device for controlling pulse sequences containing a counter, a block of permanent memory and a register, the group of outputs of the counter connected to a group of address inputs of a block of permanent memory, characterized in that, in order to extend the functionality by monitoring complex analog signals, a decoder is inserted into the device , a comparison unit, three triggers, an AND block, a group of OR elements, an analog-to-digital converter, an OR element, a clock generator, an AND element, and three single-oscillators, the group The outputs of the task of controlling the constant memory block are connected to the group of inputs of the decoder, the group of address inputs of the permanent memory block is connected to the first group of inputs of the comparison block, the output of the end of the command of the permanent memory block is connected to the information input of the first trigger, the decoder outputs from the first to (n-1) th is connected to the first inputs of the elements OR of the group of respectively the first through (n-1) -th, η-th output of the decoder is connected to the second input of the (n-1) -th element of the OR group and the first input of the first group of inputs of the block of elements And, the output of the ΐ-th element of the OR group (ί = 2 ... (η-1)) is connected to the second input (ΐ-1) -Γθ of the OR element of the group and to the inputs, respectively, from the second to (n-1) of the first group of inputs of the block of elements AND, the output of the first element OR of the group

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connected to the ηth input of the first group of inputs of elements I of the group, the output group of the analog-digital converter is connected to a group of information inputs of the register, the output group of which is connected to the second group of inputs of the block of elements I, the output group of which is connected to the second group of inputs of the block comparison, the output of the inequality of which is connected to the information input of the second trigger, the direct output of which is connected to the input of the first one-vibrator, the output of which is connected to the first input of the element (5 element OR, the output of which is connected the reset inputs in the “O” of the first, second and third flip-flops, the direct output of the third flip-flop is connected to the trigger input of the clock generator, the first output of which is connected to the register recording enable input, the second clock generator output is connected to the counter input of the counter and the first and second clock inputs 25

the second trigger, the output of the second one-shot is connected to the counter input of the counter recording, the direct output of the first trigger is connected to the input of the third one-shot, the first input of the AND element is the output of the device's work circuit, the output of the third one-shot is connected to the second input of the second the trigger is connected to the second input of the element I, the group of inputs of the analog-to-digital converter is a group of inputs of the monitored device sequences, the input of the installation at "1" of the third trigger is connected with the input of the second one-shot and is the start input of the device, the group of information inputs of the counter is a group of inputs of the number of the controlled sequence of the device, the output of the element I Is the output of the control rate of the controlled sequence of the device.

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