SU1144190A1 - Multichannel shaft turn angle encoder - Google Patents

Description

The second, third and fourth inputs of the octant definition block are connected respectively to the third input of the microprogram memory block, to the fourth input of the interface block and to the bi-directional bus input, the output of the overlapping block is connected to the first output of the octant definition block, the third output of the interface block is connected to the second output of the octant definition unit

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and to the third input of the memory unit, the second outputs of the memory unit and the output registers are combined and connected to the third output of the octant definition unit and to the fifth input of the interface unit, the output of the bidirectional bus is connected to the fourth output of the octant detection unit whose fifth output is connected with the third output of the memory block.

The invention relates to -automatic and computing equipment and can be used to connect analog information sources with computer complexes. Multichannel shaft angle converters are known in code, containing CTD sensors connected to an input switch, a quad switch that has an input connected to the first the output of the distribution block, the second output of which is connected to the first input of the code-voltage decoder converter, the output of which is connected to one of the inputs of the comparison unit, the output the second one is connected to the quad switch, the first input of which is connected to the input of the distribution unit, and the second and third outputs of the last one through the amplifiers are connected to the third input of the decoding converter, while the second input of the comparison unit grounded lj.  The disadvantage of such converters is their low accuracy.  The closest technical solution to the invention is a multi-channel, w-converter of the angle of rotation of the shaft into a code containing a sine. cosine angle sensors connected to the switch inputs, the first and second switches of the switch are connected to one input of the first and second sampling blocks, the outputs of which are connected to one input of the first and second comparison blocks, the reference voltage block connected to the first inputs of the first and the second decoding converters, the first outputs of which are connected to other inputs of the first and second comparison blocks, the outputs of the first and second comparison blocks to the second inputs of the first and second decoding converters, and Other outputs are connected to the first input of the distribution block, first output of the distribution block to the control input of the switch, second output to the other inputs of the first and second sampling units, third output to the third inputs of the first and second decoding converters, the output unit oKTaaTOBj whose first output connected to a digital computing my-bus, the fourth output of the distribution block to one input of the first and second averaging blocks, the other inputs of which are connected to the third outputs of the first and volts cerned decoding converters, and the outputs of the first and second averaging units are connected to first and second inputs determination unit octants, third and fourth inputs of which are connected to the fifth and sixth output distribution block 2 w.  A disadvantage of the known converter is the functional dependence of the output code on the angle of rotation, which limits its scope and requires the use of a computing device to form a linear dependence of the output code on the angle of rotation.  31 The purpose of the invention is to increase the accuracy and expand the field of application of the multichannel shaft angle-to-code converter.  The goal is achieved by the fact that in a multichannel converter the angle of rotation of the shaft into a code containing sine-cosine angle sensors connected to the inputs of the switch, the first and second outputs of the switch are connected to one input of the first and second sample blocks, the outputs of which are connected to one the inputs of the first and second blocks of the comparison, the unit of reference voltage connected to the first inputs of the first and second decoder converters, the first outputs of which are connected to the other inputs of the first and second blocks of the comparison ,, audio outputs of the first and second comparing units - to the second inputs of the first and second decoders. converters, the second outputs of which are connected to the first input of the distribution block, the first output of the distribution block to the control input of the switch 5, the second output to other inputs of the first and second sample booths, the third output to the third inputs of the first and second decoding converters, an octant determination unit, the first output of which is connected to a digital computer, an asynchronous exchange unit is introduced, the inputs of which are connected to the second, third and fourth outputs of the octant definition unit, the first the output is connected to the fourth inputs of the first and second decoding converters, the second output; - to the first input of the octant determination unit, the second, third and fourth inputs of the octant determination unit are connected respectively to the fourth output of the distribution unit, the digital computer output and the third outputs of the first and second decoding converters, and the fifth output of the octant detection unit is connected to the second input distribution block.  The octant definition block contains a firmware memory block, an arithmetic block, a memory block, an exchange control block, a register block, an interface block and a combination block interconnected via a bi-directional information bus, a microprogram memory block and an arithmetic block connected to one another with another bi-directional bus; the second inputs and outputs of the exchange control unit and the interface unit are interconnected; the first input of the octant definition unit is connected to the second inputs of the memory unit, the register registers and the third input of the interface unit, the second, third and fourth inputs of the octant determination unit, respectively, to the third input of the microprogram memory block, to the fourth input of the interface unit and to the bi-directional bus input, output of the combining unit to the first | upper one; octants, the third port of the interface block - to the second output of the block. octant definitions and to the third input of the memory block, the second outputs of the memory block and output registers are combined and connected to the third output of the octant definition block and to the fifth input of the interface unit, the output of the bidirectional bus is connected to the fourth output of the octant definition block, the fifth output of which connected to the third output of the memory unit.  FIG. 1 shows a flowchart of a converter; in fig. 2 is a functional diagram of the interface unit.  The converter contains sine-sinus-sine sensors 1 (MSC), switch 2, sampling units 3, decoding converters 4, comparison units 5, block 6, defining opants, block.  7 asynchronous exchange, distribution block 8, reference voltage block 9, sequential approximation registers 10, electronic keys 11 bits with R-2R resistor matrices, microprogram memory block 12, arithmetic, block 13, memory block 14, control block 15 exchange unit, register block 16, interface block 17, bidirectional information transfer bus 18, combination block 19, synchronization block 20, clock distributor 21, address control block 22, control block 23, bloom control block 24, providing feedback ene information to the block 13 and the handshake exchange commands with block 12, the synchronization unit 25, a register 26 and decoder microinstructions interface unit 27 and the control trunk transceivers.  The octant definition block 6 is built on the basis of a microprocessor set of low-threshold CMOS BIS series 588, designed to build advanced microcomputer systems.  Block 6 performs the following function; collecting information from registers 10 and determining the averaged (three samples) voltage codes Usiniyi and Ucos oi sensors 1 (coarse and fine channels), calculating the tangent codes (cotangent) of the angle of rotation of the shaft U s ii-io for and (.  - and cos coso - and / w (I S ill cf; and with S (X.  or -K, -g-; and sintsi determine the angle code in the range of 0-45 ° (octant), ui arctgK for and siniy U cosoi or ui 90 -at: ctgK2 for U sinoii U cosoi, determine the octant number code, co-alignment of the angle codes of sensors 1 coarse and accurate channels.  The unit 6 for determining octants consists of a block 12 of firmware memory (BIS UE KR588VU2) / converts 16-bit command codes in a sequence of 13-bit microinstructions, arithmetic unit 13 (BIS AU KR588BC2), which is a universal asynchronous digital processing module information for receiving online storage (on 16-bit general purpose registers RON) of processing and storing numeric and address information with one information bus, microinstruction bus and status indication bus; block, 14 memory (BIS 556PT7) intended for storing program commands, block 15 of exchange control (BIS SK KP588BF1) implementing the exchange control according to a given algorithm, - block 16 of registers representing the RAM module, in koTopoM accumulate the results of transformation, interface block 17 (BIS SK KR588VG1), designed to ensure the functioning of the processor set according to the corresponding timing diagram of the bidirectional 16-bit bus 18 data, addresses and commands (form 531A11AP, or 589AP16); block 19, combining communication with the appropriate exchange algorithm of block 6 for determining octants with the on-board computer; If the on-board computer has a wide bus (address and data buses are separated from one another), then block 19 is implemented on a BIS AD (adapter narrow bus - wide bus), either on a set of IP; if the on-board computer has a narrow bus, then block 19 is implemented on conventional integral keys controlled by interrupt from the on-board computer.  Blocks 15, 17 and 18 are the system interface of the LSI IC 4, which defines the interface between the processor unit (blocks 12 and 13) and system devices (registers 10, unit 16 and the on-board computer).  Block 7 of asynchronous exchange serves to organize the exchange of information between decoding converters 4 and block 6 of determining octants on the principle of reception-response.  The distribution unit 8 comprises a synchronization unit 20 connected to a clock distributor 21 Qo j of the control unit 23, another input connected to the output of the distributor 21, and an address control unit 22 connected to the synchronization unit 20.  At the same time, the second input of the distributor 21 is the input of the distribution block 8, the second ° 22 address control control input of the distribution block 8, whose outputs are respectively the outputs of the synchronization blocks 0 and the block 22, as well as the outputs of the control block 23. . The distribution unit 8 is a logical control unit of the device.  The reference voltage unit 9 serves to form a precision reference voltage, which is applied to the corresponding inputs to be decoded.  converters 4.  The multichannel converter at turn of a shaft in the code works in the following way.  I When the converter is turned on according to the program laid down in block 14, the address control unit 22 is started simultaneously with the transmitter installation signal, ensuring the operation of the input switch 2.  The synchronization unit 20 determines the reference frequencies and control signals necessary for synchronizing the operation of individual logic devices in time.  .  The address control unit 22 provides for the sequential switching of the channels of the input switch 2 and can be executed on the Johnson counter (564IE9) or the ring shift register (564ИР2).  Switching on the next channel of the input switch occurs after the termination of the conversion of the 3rd sample of the previous channel.  The operation of block 22 is controlled by the signals Turn on from the output of block 14, the conversion of the 3rd sample of the previous channel from the control block 23 and the reference frequency - block 20 of synchronization.  At the moment of crossing the zero positive half-period of the supply voltage of the SKT sensor, the synchronization unit 20 generates pulses. Start of conversion. A synchronization pulse taking into account the phase shifts of the output voltages of various sensors 1 (coarse and accurate channels) relative to the supply voltage, which ensures the balancing process. measure e1 1x voltage at the time of reaching the working sections of sinusoidal voltage.  The synchronization pulse starts the clock distributor 21 and the block 23, which controls the operation of the sampling units 3 and the octant definition unit 6.  The control unit 23 consists of | logic elements, forming control signals for blocks 3 (Sampling, Storage, Zeroing) for 3 samples of each channel of the input switch, and can be implemented as a 2-bit binary counter (564ТМ2) and logical assembly (564ЛА9 ) for signals The end of the conversion is 3 samples of each channel of the input switch 2, which forms the Start signal for the octant determination unit 6, t Sampling units 3 provide with high accuracy simultaneous fixation of the instantaneous U sinci and cosoi levels present at the start conversion, and storing the selected input level at the time of the conversion.  The input signals at this time are different from the input of the converter.  Information from the outputs of the sampling units 3 are simultaneously fed to one 1 08 of the inputs of the comparison units 5.  Decoding converters 4 in the sine and cosine signals are simultaneously triggered by signals from the distributor 21 clock pulses.  The output voltages of the reference voltages of the decoding converters 4 are fed to the second input of the comparison blocks 5, where bitwise comparison of the measured voltage with the reference voltage is made.  The second inputs of the block 11 receives the reference voltage from the output of block 9.  On the p-cycle of encoding, block 5 compares the output pulse arriving at the input of register 10 of the sequential approximation and controlling the operation of the nth bit, disconnecting this bit from the balancing process under the condition ((, (where Uip is the output voltage of the decoder converter).  As a result of the conversion, a 12-bit U sinoC code and a U cosot CKT sensor are set on the registers 10.  At this moment, from the registers 10 to the input of the synchronization unit 20 a pulse arrives. A conversion end that, through the control unit 23, starts the block 6 opr:; division of octants (Start signal), which, in accordance with the program.  written in block 14 of memory, executes the first commands — writes information from the output of registers 10 into the corresponding general purpose registers RON of the arithmetic unit 13.  After this, the second launch of blocks 3 and decoding converters 4 (mode. 1 second count-ta), which occurs similarly.  At the same time, the execution of the following command in block 6 for determining octants is blocked by software.  The lock takes off-.  with the next start signal from block 23.  I The next command is executed, which records information from the registers 10 into the corresponding RON registers of block 13 (second counting mode).  After this, the third reading mode proceeds in a similar way, ending with recording the conversion result from the registers 10 into the corresponding registers of block 13.  Having executed the commands for receiving information of the third reference mode, the octant definition unit 6 proceeds to execute a sequence of information processing instructions received from decoding converters 4 as a result of performing three sampling modes.  At the same time, the address control unit 22 is started, and the process of converting the information of the next channel of the input switch 2 begins.  Three-fold mode of operation of the proposed converter eliminates random conversion errors, which increases the reliability and accuracy of operation.  This mode is provided by the high speed of operation of blocks 3-6 and 8.  From the moment of launching the next input channel to the end of the first counting mode on this channel (appearance at the output of registers 10 and sihoi and sovhob), block 6 will execute all commands for the sequential processing of information on the previous input channel, ending with the Stop command, on which the block 6 stops processing the information and waits for the next command.  Start from control unit 23.  The operation of the octant definition unit 6 is performed as follows. The operation starts with a signal. A start from the distribution block 8 arriving at the input of the block 12 of the microprogram me memory.  By this signal, the synchronization element of the block 12 is used to generate the control signals, start and end the issuance of microcommands and external signals at the output of the synchronization block 12, intended to control the block 13 (BIS AU), zero the current address register in block 12, which serves to address the current microcommand in the microprogram; Block 12 converts the 16-bit instructions into a sequence of 13-bit microcommands.  I In block 14 of the memory, a sequence of information processing instructions is recorded.  On the outputs of the micro-instructions of block 12, the initial installation code of block 13 is established, and then the block 12 proceeds to form the next micro-command.  According to the microinstruction of the initial installation, the synchronization element of the block 13 is set to the initial state and transitions to the mode of reception of the next microcommand and its execution. At the same time, unit 13 at the output Executed sets the reception enable signal of the next micromash.  Unit 12, having received the enable (handshake) signal from unit 13, carries out the next 2nd micro-command and at the same time forms the next 3rd micro-command.  Block 13, having received the 2nd micro-command, executes it and sends to the bus 18 data, addresses and commands the contents of the register of the command counter — the address of the first command recorded in memory block 14, and sets the output signal on the pin Executed microinstructions  The interface unit 17 performs interfacing within the processor interface, performed according to the asynchronous principle.  The exchange of information takes place on the acknowledgment signals reception-response with the bus 18.  Block 17 performs the following functions: microprogram control, information exchange management between the processor (blocks 12 and 13) and external devices (blocks 7, 10 and the BCMM or RAM - block 16j, control of bi-directional trunk transceivers on the BIS MOP KR588 VA1.  The interface unit 17 can be performed on the BIS SK Kr5888G1 (system controller).  The selected device in this case is block 14 (the first is its cell, where the first 16-bit command is recorded).  At the same time, block 12 issues a third micro-command to block 13, according to which block 13 removes the address of the first command from bus 18 and increases the contents of the command counter by one, and block 17 issues an Input signal to the processor.  After issuing the third microinstruction and receiving the input signal to the processor, unit 14 exposes the contents of the first cell to the bus 18, together with the tracking signal, the first 16-bit command (write the contents of register 10 of the first decoder converter 4 according to the first countdown to the first general register (РОН) block 13), which is fed to the input of the 16-bit command of block 12.  After receiving the first command, block 12 begins to sequence the 12-bit microcommands for which the command is executed: the command counter in block 13 is incremented by one (the command counter is increased by two units as a result) the address of the call is determined in accordance with received command (addressing type); The address of addressing bus 18 is set, block 17, in accordance with the command, carries the address maintenance signal, and block 7 of asynchronous exchange using this signal determines which of registers 10 needs to be connected to bus 18 via the signal path Input to the processor, which It also blocks 17 by decoding the address in block 7 and preparing for the data transfer operation, and, having received the input signal to the processor, block 7 connects register 18 to the bus 10 of the first decoder of converter 4 and outputs the data tracking signal, is written held reg Stra 10 first decoding the first transducer 4 POH block 13j is output block 13 the contents of program counter 18 to the address bus of the second command, which compared to the first instruction address is increased by unity dd, incremented contains zhimoe counter unit 13 commands.  Unit 12 according to the second command, a sequence of micro-manners of recording the contents of register 10 of the second decoding converter 4 n is first counted in the second RON unit 13.  The operation is similar.  Simultaneously with the issuance of the third command to the bus 18, decoding converters 4 are started in the second reference mode.  The third command (writing the contents of register 10 of the first decoder converter 4 of the second reference to the third RON of block 13) until the end of the second reference mode in block 12 fails, t. e.  The third-to-one 16-bit code is placed on bus 18 (the signal is blocked. The command is escorted from block 14 until it appears on the registers 10 of the conversion results by the second reference mode).  After the termination of the second reference mode, the signal Accompanying the command from block 14 allows the third and fourth vertices to execute commands (recording the contents of the register 10 of the second decoding converter 4 into the fourth RON of block 13 according to the second counting mode).  The process proceeds in the same way as the first and second commands.  After that, the fifth command is inserted into the pitch 18 (writing in the fifth RHEN of the block 13 of the register 10 of the first dexdriver of the transducer 4 according to the third counting mode).  Execution of the fifth and then sixth commands is blocked until the end of the third reference mode, after which through the address control block 22, decoding converters 4 are started up in the first countdown mode of the second information channel of the input switch 2.  Block 14 with a signal The command support permits the execution of the fifth and sixth commands.  The seventh and all subsequent commands sent to bus 18 are information processing commands and are executed without blocking.  The output of the averaged angle codes (after the conjugation of the coarse and exact channels of the SKT sensor) of the first information channel to the corresponding output registers of block 16 occurs before the first reading of the second information channel of the input switch 2 finishes, Vshod proceeds as follows: into the bus 18 of block 13, the address of the output register of block 16 is entered in accordance with the output command, the output register of block 16 with this address goes into the waiting mode for information from the bus 18 on a signal output from the processors, block 1 3, controlled by block 12, removes from the bus 18 the address of the output register of block 16, sends to the bus 18 the processing data of the first information channel of the input switch 2, outputs the output signal from the processor, which records data to the register of block 16, after which the register of the block 16 carries the write confirmation signal, and the block 13 of the bus 18 information.  The last program in the program is the Stop command, according to which the octant definition block 6 stops all calculations and goes into standby mode of the Start command from the distribution block 8.  During the operation of the converter, the execution interruption is skipped) of the on-board computer or other external one. with a device.  The program shutdown mode occurs in the following way: block 13 has sixteen 16-bit RON, from which RON 6 and 7 are allocated, and RON 7 is used as a command counter, t. e.  contains the address of the next execution of the 1st command.  When executing a number of commands that require temporarily storing data (for example, return addresses when the Tk is addressed, the subroutine of definition or subprogramme for joining the averaged codes of the hard and exact channels of the SKT sensor) or with external interrupts, РОН 6 is used as a stack pointer.  A stack is a method of organizing an array of memory elements, in which the recording or sampling of elements is performed according to the principle: the last recorded element is selected from the array first.  The program determines the moment area reserved for the hardware stack (10–12 last registers of block 16). The exchange control unit 15 also interfaces the interface unit 17, bus 18 with the on-board computer and the intraprocessor interface of the octant definition unit 6.  Block 15 can be executed on a BIS SK Kr588AG1 or a set of integrated circuits 564 series.  The exchange control unit 15 includes a priority interrupt handling control unit 28 and a direct memory access control unit 29.  In processing the faults, block 15 includes the exchange control block 24 synchronization block 25 and a decoder 26 microcommands that are part of: the interface block 17.  When receiving an interrupt signal from the on-board computer, unit 15 compares the priority of the interruption line with the processor priority of the octant definition unit 6 recorded in a special 16-bit register of unit 13 (processor status word register). If the priority of the interrupt line is higher than the priority of the processor, block 15 selects the interrupt enable signal after the end of the current command and starts executing the interrupt procedure.  I The break signal from block 15 is fed to block 19, which connects bus 18 to the on-board bus.  After receiving the cut-off permission signal, the on-board computer sets the address of the interrupt vector on the data bus, upon receipt of which unit 15 controls the operation of block 13 as follows: it stores in the stack (the memory cell whose address is in the stack pointer РОН 6) the current status word Litter, in the next stack cell remembers the address of the next command of the interrupted program, writes in the stack (the memory cell whose address is in the stack pointer RON 6) the current processor status word in the next stack cell remembers.  the address of the next command of the interrupted program writes in the command counter (RON 7) of block 13 the address of the interrupt processing routine (first word of interrupt vector) and into the word processor register of block 13 second word of interrupt vector (new processor state word), Octane definition unit 6 executes all the commands in accordance with the interrupt program recorded in the memory of the on-board computer or any external device, and following the last command of the program, the interrogation will further execute its interrupted program.  When transferring the results of the calculation from the converter to the on-board computer (transfer mode of information from the memory of the octant definition block 6), the interrupt mode is implemented in another way: the interrupt signal from the PCB is simultaneously supplied to the blocks 15 and 17, while in block 15 there is a comparison.  priority, and the block 17 blocks the internal channel of the microprocessor block from the bus 18 and connects the bus 18 to the on-board computer interface via the t9 block.  If there are signals, the Address Maintenance and Input in the On-Board Computer are the output registers of block 16 that can be used as the on-board memory computer (direct memory access mode).  The execution of the octant definition unit 6 on the basis of the microprocessor set and the introduction of the asynchronous exchange unit 7 make it possible to create a functionally complete autonomous converter for the angle of rotation of the shaft to the code. , angle, that expands its area when-, medneni.

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Claims (2)

1. MULTI-CHANNEL SHAFT ANGLE CONVERTER TO CODE, containing sine-cosine angle sensors connected to the inputs of the switch, the first and second outputs of the switch are connected to one input of the first and second sample blocks, the outputs of which are connected to one input of the first and second comparison blocks, block reference voltage connected to the first inputs of the first and second decoding converters, the first outputs of which are connected to other inputs of the first and second comparison units, the outputs of the first and second blocks are comparable are connected to the second inputs of the first and second decoding converters, the second outputs of which are connected to the first input of the distribution block, the first output of the distribution block is connected to the control input com? mutator, the second output to the other inputs of the first and second blocks ^{of the} sample ¹ , the third output to the third inputs of the first and second decoding converters, an octant detection unit, the first output of which is connected to a digital computer, characterized in that, for the purpose of increasing accuracy and expanding the scope, an asynchronous exchange unit is introduced into it, the inputs of which are connected to the second, third and fourth outputs of the octant detection unit, the first output is connected to the fourth inputs of the first and second decoding pre browser, the second output is to the first input of the octant detection unit, the second, third and fourth inputs of the octant detection unit are connected respectively to the fourth output of the distribution unit, the output of the digital computer and the third outputs of the first and second decoding converters, and the fifth output of the octant detection unit connected to the second input of the distribution block. 2. The Converter according to claim 1, about t -. Caused by the fact that the unit for determining the octants contains a block · microprogram memory, arithmetic. The memory unit, the memory unit, the exchange control unit, the register unit, the interface unit and the combining unit, mutually interconnected via a bi-directional information transfer bus, the firmware unit. the memory and the arithmetic unit are connected to each other by an additional bi-directional bus, the second inputs and outputs of the exchange control unit and the interface unit are mutually connected to each other, the first input is “block-” _; The definition of octants is connected to the second inputs of the memory block, the register block, and the third input of the interface. I clear block, the second, third and fourth inputs of the octant detection block are connected respectively to the third input of the microprogram memory block, to the fourth input of the interface block and to the bi-directional bus input, the output of the combining block is connected to the first output of the octant detection block, the third output of the interface block is connected to to the second output of the octant detection unit and to the third input of the memory unit, the second outputs of the memory unit and output registers are combined and connected to the third output of the octant detection unit and to to the input of the interface unit, the bi-directional bus output is connected to the fourth output of the octant detection unit, the fifth output of which is connected to the third output of the memory unit.