SU1642459A1 - Device for synchronization of signals - Google Patents

Abstract

The invention relates to computing and can be used in the equipment for processing discrete signals. The purpose of the invention is to simplify the device. The goal is achieved due to the fact that the device contains an inverter and the second element IS NOT. 1 il.

Description

The invention relates to computing and can be used in the equipment for processing discrete signals.

The purpose of the invention is to simplify the device.

The drawing shows the electrical circuit of the device for synchronizing signals

The device includes triggers 1 entries, the first element AND-NOT 2, inverter 3, trigger 4 blocking, elements AND 5, the second element AND-NOT 6 and triggers 7 of the first digit of the register.

The device uses D-flip-flops that are triggered on the front of the CHI-nal at the C-input.

In the drawing, there are 8 - information inputs connected to the D - inputs of the trigger 1 record; 9 - outputs of the trigger 7, which are the outputs of the device; 10 - recording control input connected to the C-inputs of the flip-flops 1; 11 - clock input connected to the C-inputs of the trigger 7, one of the inputs of the NAND 6 element and through the inverter 3 to the C-input of the trigger 4 of the lock Direct outputs of the trigger 1 records are connected to one of the inputs of the corresponding elements 5 And, and inverse - with the inputs of the element AND-NOT 2, the output of which is connected to the D- and R-inputs of the trigger 40 The output of the trigger 4 is connected to other inputs of the elements AND 5 and the element AND-NOT 6, the output of which is connected to the R-inputs of the trigger 1

The device works as follows

In the initial state on the direct outputs of the triggers 1, at the output of the element AND-NOT 2, at the output of the trigger 4, at the outputs of the elements, And 5 and at the outputs 9 there are level signals O, and at the inverse outputs of the triggers 1 and at the output of the element And - NOT 6 - level 1 signals.

The inputs 8 of the device receive, for example, an ADC word code in the form of level 1 and O signals. When a signal appears at input 10 of the record, triggers 1, on the D inputs of which there is a level 1 signal, are switched and their outputs appear Level 1, which arrive at the first inputs of the elements And 5. Pos

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: a ring on the second inputs of elements 1 5 there is a level signal O from the output of the trigger 4, at the outputs of the I 5 elements and, therefore, on the D-inputs of the triggers 7 of the first bit of the register remains the level signal O l. at the moment of arrival at the clock input 11 of the clock pulse, the triggering of the corresponding triggers 7 will not occur. From the inverse outputs of those 1 record triggers, on the direct outputs of which level 1 signals appeared, the level O signals are fed to the inputs of the AND-NOT element 2, causing the output of the level 1 signal that goes to the D input of the trigger 4 " At the end of the pulse at the clock input 11, which enters the C input of trigger 4 through inverter 3, the trigger 4 is triggered, a level 1 signal appears at its output, which, arriving at the inputs of the And 5 elements, allows the signals to pass through them my outputs of the triggers 1 on the D-inputs of the 70 trigger trigger output EPA 4 level 1 signal is also applied to element input AND-6, preparing it for operation. When a clock pulse arrives at the clock input 11, those triggers 7, on the D-inputs of which a level 1 signal is present, are triggered and on their outputs 9 there are level 1 signals, i.e., the first bit of the register has recorded information from the triggers 1 without distortion due to the separation in time of the occurrence moments at the inputs of the triggers 7 information and clock pulses

When a pulse appears at the clock input 11, it enters them in the initial state by entering through the AND-HE element 6 to the R-inputs of the flip-flops 1. At the output of the NAND 2 element, an O level signal appears, which

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sets to the initial state the trigger 4. On the D-inputs of the triggers 7, the level O signal appears. When the next clock pulse arrives, the information from the first register bit is rewritten to the second bit (not shown). The device returns to the initial state. Thus, the writing of the code of the word, for example, from the ADC to the n-bit shift register without distortion, is carried out. At the same time, the functional reliability of the device is enhanced by simplifying it.

Claims (1)

Invention Formula 20 25 thirty A device for synchronizing signals, containing recording triggers, triggers of the first register bit, AND elements, a blocking trigger, and the first NAND element, the C inputs of recording triggers being a device recording input, and D inputs are corresponding information inputs of the device, inverse the write trigger outputs are connected to the inputs of the NAND element, the C inputs of the first register triggers are a clock input of the device, characterized in that, in order to simplify the device, it contains an inverter and a second NAND element, the first the input of which is connected to the output of the blocking trigger and the first inputs of the And elements, the second input is connected to the input of the inverter and is the clock input of the device, and the output is connected to the H inputs of the recording triggers, the forward outputs of which are connected to the second inputs of the And elements whose outputs are connected with the D-inputs of the first-digit triggers of the register, the output of the first element 45 is NOT connected to the D- and R-inputs of the blocking trigger, the C-input of which is connected to the output of the inverter. 35 40 sets to the initial state the trigger 4. On the D-inputs of the triggers 7, the level O signal appears. When the next clock pulse arrives, the information from the first register bit is rewritten to the second bit (not shown). The device returns to the initial state. Thus, the writing of the code of the word, for example, from the ADC to the n-bit shift register without distortion, is carried out. At the same time, the functional reliability of the device is enhanced by simplifying it. Invention Formula register bit BUT