SU468243A1 - Interface device - Google Patents

Description

The invention relates to digital computing and can be used in the construction of computers and data processing systems.

A device for interfacing a digital computer with an external drive is known. St. No. 389504, which contains an electronic clock, logic circuits, keys, triggers, a control unit, and a buffer register. However, using this device it is impossible to detect spurious pulses from the accumulator in the intervals between the clock pulse and the timestamp, as well as between the polling signal from the buffer register and the timestamp.

The purpose of the invention is to expand the operational capabilities of the device.

The proposed device differs from the known one in that it contains an additional trigger, the first and second additional OR circuits, the registration circuit, the delay line and the additional coincidence circuit, the output of which is connected to the input of the registration circuit, the first input is connected to the input of the separation circuit, and the second is output of an additional trigger. The trigger inputs are connected to the outputs of additional OR circuits, respectively, the first input of the first additional OR circuit is connected to the output of the buffer register of communications and to the input

the second matching circuit, the second input through the delay line is connected to the first output of the separation circuit and to the input of the electronic clock and control circuit. The first input of the second additional circuit “OR is connected to the output of the electronic clock and with zero input of the third trigger, the second input of the second additional circuit“ OR is connected to the second output of the electronic clock.

This embodiment improves the performance of the device by detecting false pulses from an external storage device.

The drawing shows a block diagram of an interface device.

The proposed device contains an electronic clock 1 with outputs 2-6 and inputs 7-9, a control circuit 10, a separation circuit 11, triggers 12-14, keys 15-17 and coincidence circuits 18-20, as well as an additional trigger 21, which inputs through Additional circuits OR 22 and 23 are connected to the output of the buffer register 24 through a delay line 25 with a clock output of the separation circuit 11, with outputs 3 and 4 of the electronic clock 1. The output of the trigger 21 is connected to the input of the coincidence circuit 26, the second input of which is connected to the output of the accumulator 27. The output of the coincidence circuit 26 is connected to the circuit 28 th registration .- -. - -.

The proposed device operates in the mode of recording information from the computer to the drive and in reading it from the drive and transferring it to the computer. In the recording mode, the information coming from the computer is rebuilt according to a predetermined sequence diagram and transmitted to drive 27, trigger 21, circuits 22 and 23 "OR. Line 25 of delay, coincidence circuit 26, and registration circuit 28 are not involved in the operation.

In the read mode, the signals from the control circuit 10 determine the operating mode of the accumulator 27, lock the key 15, open the keys 16 and 17, and issue a command to the drive to start reading the information. The signal separation circuit also divides the information, the arrival of the accumulator 27 from the clock and code pulses, the clock pulses to the input of 8 electron hours 1 and serve as a command to start the timing of time. In addition, through the delay line 25 and the OR circuit 22, they arrive at the single input of the flip-flop 21 and a signal appears at its output. Code pulses are applied to trigger 14.

From the output 2 of the electronic clock 1, through the key 16, a pulse is given to the computer, which with a certain delay leaves the machine and is fed to the coincidence circuit 19. If at this moment there is a signal at the output of the trigger 14, it is transmitted to the computer and is perceived as a unit code.

A code pulse should appear at the output of the accumulator with a certain shift after the clock. If it turns out too early, the signal taken from the output of the 6 electronic clock 1 and defining the lower limit of the allowed shift will reset trigger 14 and this code pulse will not pass to the buffer connection register 24 of the computer. The same signal from output 6, having passed through circuit 23, OR, flips trigger 21 to another state, and the signal at its output will disappear. So, if on. the output of the accumulator 27 is passed through a false pulse in the time interval between the clock pulse and the signal from output 6, then it will pass through the coincidence circuit 26 to the false pulse detection circuit 28. Line 25 of the delay is chosen so that it delayed the clock pulse for a time equal to its duration. This is necessary to exclude the filing of one

the same clock pulse simultaneously to the two inputs of the coincidence circuit 26.

The upper limit of the allowable offset of the code pulse relative to the clock is determined by the time of the signal from the computer supplied to the input of the coincidence circuit 19. The output signal 4, which is fed to the fault input 9 of the electronic clock 1 and input 7, stops the reference frequency to the electronic counter 1, which stops the time and is prepared to receive the next clock pulse from the separation circuit 11.

In the same way as described, the coincidence circuit 26 opens the input of the registration circuit 28 for receiving false pulses in the time interval between polling the next code pulse on the signal from the buffer register 24

connection and a signal from the output of 4 electronic clocks 1.

Thus, the auxiliary device allows detecting the false pulses recorded in the drive 27 in the intervals between

clock and code pulses.

Subject invention

A device for interfacing a digital computer with external storage devices by author. St. No. 389504, characterized in that, in order to expand operational capabilities, it contains an additional trigger, the first and second additional

The OR circuit, the registration circuit, the delay line and the additional matching circuit, the output of which is connected to the input of the registration circuit, the first input is connected to the input of the separation circuit, and the second input is connected to the output

an additional trigger whose inputs are connected to the outputs of the additional circuits OR, respectively, the first input of the first additional circuit OR connected to the output of the buffer register of communications and to the input

the second coincidence circuit, the second input through the delay line is connected to the first output of the separation circuit and to the input of the electronic clock and control circuit, the first input of the second additional OR circuit is connected to

the output of the electronic clock p with zero input of the third trigger, the second input of the second additional circuit "OR connected to the second output of the electronic clock.