SU1427374A1 - Tape recorder to computer interface - Google Patents

Abstract

The invention relates to computing technology for inputting digital data from one or more digital computers and outputs to them and can be used to interface a tape cassette recorder with a digital computer. The aim of the invention is to increase speed. The device comprises an output unit 1, a synchronization unit 2, a synchronization switch 3, an input unit 4, a program search block 5. 6 Il.

Description

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The invention relates to computing technology for inputting digital data from one or more digital computers and outputs to them and can be used to interface a tape cassette recorder with a digital computer.

The aim of the invention is to improve the speed,

In Fig. 1, a diagram of the device is presented; figure 2 - block diagram of the water; FIG. 3 is a block synchronization diagram; FIG. 4 is a diagram of a clock switch; FIG. 5 is a diagram of an input unit; Fig.6 is a block diagram of a software search.

The device contains (FIG. 1) an output unit 1, a synchronization unit 2, a synchronization switch 3, an input unit 4, a software search unit 5. In Fig. 1, inputs and outputs 6-18 of the device, inputs and outputs 19-26 of the output unit 1, inputs and outputs 27-34 of the synchronization unit 2, inputs and outputs J5-40 of the switch 3 of the sync signal are also designated.

The output unit 1 contains (FIG. 2) the register 41, the elements AND 42, 43, the converter 44 of rectangular pulses into a sine wave, the elements —OR 45 45.

Block 2 synchronization contains (fig.Z) triggers 47, 48, elements And 49-51, trigger 52, a divider by 8 53, dividers by 2 54, 55, register 56, elements 57-59, counter 60.

The clock switch 3 contains (FIG. 4) elements AND 61-66, elements OR 67-69, trigger 70, element NOT 71.

The input unit 4 comprises (FIG. 5) a top level comparator 72, a low level comparator 73, one-shot 74, 75, counters 76-78, triggers 79-81, And 82, register 83, delay Element 84.

The software search unit 5 contains (FIG. 6) a comparator 85, counters 86, 87, file counter 88, register 89, NOT element 90, triggers 91, 92, element 93, compare 1, one-shot 94, element OR 95, delay element 96, switch 97.

The output unit 1 is designed to convert O and 1 signals to 2.5 and 5 kHz pulses.

The synchronization unit 2 generates conversion signals corresponding to O and 1, as well as signals not

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walkable for operation of this device.

The switch 3 of the clock signals is intended for switching the pulses produced in the synchronization unit 2.

Block 4 input is designed to convert analog signals from the output of the cassette tape recorder recording, to the level O and 1, as well as generating a synchronizing pulse - a sign of information.

The device works as follows.

In the output mode, if the ready signal is set at the output of the device, information from the digital computer is fed to input 6 with a parallel code, and input 9 is a sign of this information. With the arrival of a signal at input 7, information is stored from input 6 in block 1 of the output, and in turn 9, in block 2 of synchronization.

The ready signal is outputted from output 11. At the output of the device, which is connected to the input of a cassette recorder, pulses of frequency 1.25, kHz appear. The number of these pulses is determined by the sign of information. If the attribute of information is 1, then output 8 will have a double pulse with a frequency of 1.25 kHz, indicating that this information is official, i.e. necessary for processing or detecting further information, if the information attribute is equal to O, then output 8 will have one 1.25 kHz pulse, indicating that the further information is non-service. In addition, -1.25 kHz pulses are synchronizing and determine the beginning of the byte of the information being recorded. After issuing 1.25 kHz pulses to the output of the device 8, it will receive pulses of a frequency of 5 or 2.5 kHz. A pulse with a frequency of 5 kHz corresponds to level 1, a pulse with a frequency of 2.5 kHz corresponds to level O of the highest bit of register 41 of the output unit 1. The shift of information in the EU register occurs with signals generated in the switch 3 and controlled in the synchronization unit 2. After all the information received at the input 6 of the device is converted

to an analog signal with a frequency of 5 and 2.5 kHz, at the output 11 of the device, a readiness signal is received, indicating that the device is ready to receive a new byte of information. Pulses with a frequency of 1.25, 2.5, 5 kHz are produced in block 2 syn. chronization by dividing the reference frequency to the input 10 of the device.

In the input mode, analog information from the output of a cassette recorder is fed to the input 12 of the device. With the arrival of 1.25 kHz clock pulses, the input unit 4 begins to analyze the input information. After he has analyzed the byte of information, the calculated information is output at output 13, and output 14 is a sign of information. With the arrival at output 13 of the synchronizing signal, the information from the device enters the digital computer.

Consider the detailed operation of the device blocks.

Unit 1 output (figure 2) works as follows.

The information from input 6 of output unit 1 is written to register 41 by a signal at input 7 of unit 1 of the state. At input 21 of block 1, a level O is set, which prohibits the passage of 5 kHz pulses from input 19 of the output unit 1, pulses with a frequency of 2.5 kHz from input 24 of the output unit 1 through elements 42 and 43. To output 8 of unit 1, output pulses with a frequency of 1.25 kHz are passed from input 20 of block 1 of the reel through the element OR 46 and converter 44 rectangular pulses into a sinusoid. With the arrival at input 21 of block 1 of the signal output with level 1, the output 8 of output block 1 will receive pulses with a frequency of 5 or 2.5 kHz depending on the state of the high bit of register 41. The information in register 41 is shifted according to the signals at input 22 unit 1 output.

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information from the input 9 of the synchronization unit 2, the number 60 in binary code is entered in the counter 60. The element 49 and 49 are opened, and the input frequency divider 53 receives the reference frequency pulses, on the outputs 27, 30, 33 of the synchronization unit 2 there appear pulses of 5 kHz, respectively, inverted pulses with a frequency of 5, 2.5 kHz. These pulses are generated by dividing the reference signal. At the output of the divider, the reference frequency of two 55, pulses with a frequency of 1.25 kHz are obtained, which are through an open-circuit element. And 50 arrive at the output 34 of the synchronization unit 2 and through the element NOT 59 to the shift input of the register 56. This will continue until the output of register 56 does not reach level 1. The trigger 48 is set to one, the output 29 of the synchronization unit 2 will be level 1, indicating that the synchronizing parcels in the unit 1 have been terminated and information packets are sent. By the first signal of the information parcel with level 1 at the input 31 of the synchronization unit 2, the trigger 52 is set to one and allow passage pulses in the input 32 through the element And 51 to the subtracting input of the counter 60 and to the output 28 of the synchronization unit 2. After the counter 60 counts the number written into it, the transfer pulse from its output sets the trigger 47 to one state and the output 11 of the synchronization unit 2 shows a readiness signal indicating that the device is ready to receive a new byte of information.

The clock switch 3 (figure 4) determines the parity of the signals

  1, received from the high-resolution register 41 block 1 output. If this number is even and the most significant bit of this register is in the zero state, switch 3 passes to the output

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Synchronization unit 2 (FIG. 3) operates at a 5 ° 38 2.5 kHz pulse from the input

melts as follows. With the arrival of the synchronization signal at the input 7 of the synchronization unit 2, the triggers 47.48, 52 are set to the zero state, the ready signal is removed at the output 11 and the level O is set at the output 29 of the synchronization unit 2, the sign is entered into the Lsegr 56

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information from the input 9 of the synchronization unit 2, the number 60 in binary code is entered in the counter 60. The element 49 and 49 is opened, and the reference frequency pulses arrive at the input of the splitter 53, at the outputs 27, 30, 33 of the synchronization unit 2, pulses appear, respectively, at a frequency of 5 kHz, inverted pulses at a frequency of 5, 2.5 kHz. These pulses are generated by dividing the reference signal. At the output of the divider, the reference frequency of two 55, pulses with a frequency of 1.25 kHz are obtained, which are through an open-circuit. And 50 arrive at the output 34 of the synchronization unit 2 and through the element NOT 59 to the shifting input of the register 56. This will continue until the output of the register 56 does not reach level 1. The trigger 48 is set to one, at the output 29 Block 2 of synchronization will be level 1, indicating that the synchronizing parcels in block 1 have ended and informational parcels are being sent. According to the first information signal with level 1 at input 31 of synchronization unit 2, trigger 52 is set to one and allows pulses to enter 32 through element 51 to pass to the subtracting input of counter 60 and to output 28 of synchronization unit 2. After the counter 60 counts the number recorded in it, the transfer pulse from its output sets the trigger 47 to one and at the output 11 of the synchronization unit 2 a ready signal is received, indicating that the device is ready to receive a new byte of information.

The clock switch 3 (figure 4) determines the parity of the signals

 1, received from the high-resolution register 41 block 1 output. If this number is even and the most significant bit of this register is in the zero state, switch 3 passes to the output

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37 of the switch 3, and the output 35 - inverted in the switch 3 pulse of a frequency of 2.5 kHz. If it is a number. The odd and high-order bit of the register is registered in block 41 of block 1; the switch is in the zero state, the switch 3 passes pulses at a frequency of 2.5 kHz to output 35, and pulsed signals at a frequency of 2.5 kHz to output 38. If the high-order bit of register 41 of output unit 1 is in the unit state, switch 3 passes to output 35 pulses with a frequency of 5 kHz from input 36 of switch 3.

Block 4 input (figure 5) works as follows. Recorded information on a tape recorder enters through the input 12 of block 4 of the input to the comparator inputs of the upper 72 and lower 73 levels. The pulse from the output of the one-shot 74 sets the trigger 79 to the zero state, the trigger 80 to the one state, and it also records the number twelve in binary code to the counter 76. The contents of the counters start to be seen as reference pulses from input 10 of the 4th input block. only at the output of the counter 76 is a transfer pulse, the trigger 80 is set to the zero state, and the number 77 is written to the number twelve in the binary code and the contents will already be read by the reference frequency pulses. The transfer pulse of the counter 77 sets the trigger 79 to the one state, the number 78 is entered into the counter 78 in the binary code, and the trigger 81 translates from one to the zero state. Thus, when reading service information from the tape recorder, the output 14 of input unit 4 will be level 1, otherwise, level O. With the arrival at input 12 of unit 4 of inputting information packets, the trigger 79 will not be set to single state, the pulses from the one-shot 75 will pass through the element 82 and the information from the trigger 80 will be rewritten to the register 83 with a shift, moreover, if the input 12 of the 4th input unit has a pulse of 2.5 kHz, then the register O will register the level O, if 5 kHz - the level 1. After how the register is filled, i.e. eight shifts will occur, the transfer pulse from counter 78 will go to output 15 of input unit 4 and will be copied from outputs 13 and 14 of input unit 4 to the digital computer. .

Unit 5 software search works as follows. Information from the tape recorder in rewind mode is fed to the input of the comparator 85, the signal from which records the number

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eight into counter 86 and sets trigger 91 to O. Information from counter 86 begins to be considered as reference frequency pulses, if the time interval between two successive pulses exceeds 0.2 ms, the transfer pulse from the counter output sets trigger 91 to one state, the counter 88 files zoom15

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cheat by 1, the number eight is recorded in counter 87 and already its content begins to be read, with reference frequency pulses. If the time interval exceeds 0.4 ms, then the transfer pulse zeroes the 88 file counter. Thus, the time interval with a duration of 0.4 ms is a marker of the beginning of the tape, and the interval with a duration of 0.2 ms is an inter-file separator.

The file number code from digital input 6 is written to input register 89 by a signal at input 16, from which a parallel code is sent to the 25th second input of the comparison element 93, to the first input of which passes the code of the current file number. When comparing the two codes, the signal from the output of the comparison element 93 will establish the trigger 92 via the single-vibrator 94 in one state, 1 through the OR 95 element will go to the remote control input. Switching off the motor of the tape recorder in the recording mode is carried out by a signal arriving at the input 17 with a delay set by the setting element 96 to form an interfile gap. In general, the program search is carried out as follows: after the initial installation of the tape, the rewind mode is activated, by the marker of the beginning of the tape the file counter 88 is set to the zero state, each subsequent file increases its contents by 1., if the code of the file number and the code of the counter 88 content match files, the tape recorder engine will be disconnected. Switching the engine into the information readout mode is performed by switch 97.

Claims (1)

Invention Formula A device for interfacing a magnetophone with a digital computer containing an input unit, an output unit, a synchronization unit, a clock switch, and the information input output unit is 35 40 45 50 the input of the device for connecting to the information output of the digital computer, the recording input of the output unit is connected to the recording input of the synchronization unit and is the input of the device for connecting to the first recording output of the digital computer, the operation input of the synchronization unit is the input of the device for connecting the output of the digital information sign The first synchronized input of the synchronization unit is connected to the synchronized input of the input unit and is the input of the device for connection to the synchronous output of the digital computer, the first information output of the output unit is the output of units for connecting to the information input of the tape recorder, the ready output of the synchronization unit is the output of the device for connecting to the ready input of the digital computer, the information input of the input unit is the input of the device for connecting to the information input of the tape recorder, the first, second and third information outputs of the input unit the outputs of the device for connecting respectively to the information input, to the input of the information sign and to the synchronous input of the digital computer, while the second synchronizing input of the synchronization unit is connected to ne The first information output of the clock switch, the first and second information inputs of which are connected respectively to the first and second synchronization inputs of the block, synchronization, the third, fourth and fifth synchronization outputs of which are connected respectively to the first, second and third synchronization inputs of the output unit, enabling input and installation output which is connected respectively with the enable output and the setup input of the synchronization unit, the second information output of the clock switch is connected to the fourth sync swing output unit, second and third informational outputs of which are respectively connected to first and second inputs of the gate clock switch, which is based on the fact that, in order to improve the speed of performance, a program search block was inserted containing a comparator, two counters, a register, a file counter, two triggers, a single vibrator, a reference element, an OR element, an element NOT delay element, a switch, the comparator information input is connected to the information input of the input unit, the synchronization input of the first counter is connected to the synchronization input of the second counter and connected to the synchronization input of the input unit, the information input of the register is connected to info rmatsionnomu input output unit, a register write input and the input of delay element are The Q inputs of the dp connection device, respectively, to the second recording input and the output of the logic condition of the digital computer, the output of the SC element is the output of the device for connection to the input 5 remote control tape, while the output of the comparator is connected to the recording input of the counter and the input element NOT, the output of which is connected to the zero input of the first trigger, the single input of which is connected to the overflow output of the first counter and the recording output of the second counter, which overflow output, connected to the installation input of the file counter, whose sync input is connected to the output of the first trigger, the output of the file counter is connected to the first input of the Comparison element, the second input of which is connected to the output of the gist, the output of the reference element is connected to the input of the one-vibrator, the output of which is connected to the single input of the second trigger, the output of which is connected to the first input five 0 45 50 the house of the OR element, the second input of which is connected to the output of the delay element, the zero input of the second trigger is connected to the first contact of the switch, the second contact of which is connected to the zero potential bus of the device. FIG. 2 . J . if FIG. five 6