SU1383449A1 - Device for checking memory units - Google Patents

Abstract

The invention relates to computing and can be used for diagnostic monitoring of memory blocks. The aim of the invention is to expand the diagnostic capabilities by counting the number of cells,: storing a constant zero or one, or the number of shorted cells. The device contains a control block, an address counter, a comparison block, first, second and third error counters, keys, AND elements, EXCLUSIVE OR and NOT, a trigger. In the device, at each address L, drying, information is recorded and information is read, then information is read at Ai +. Monitoring is performed for direct and inverse information codes. If errors are detected, the corresponding error counter is incremented. 2 Il.

Description

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I The invention relates to computational hardware and can be used to diagnose memory blocks.

The purpose of the invention is to expand diagnostic capabilities by counting the number of cells that store a constant zero or one, or the number of shorted cells.

FIG. 1 shows a diagram of a device for monitoring memory blocks; in fig. 2 - timing diagrams, explaining the principle of operation of the device.

I The device contains a key 1, a delay element 2, a synchronization input 3, a key 4, a trigger 5, a divider 6, a decoder 7, an address | account 8, elements AND 9-11, a monitored block 12, element 13, an element 1 SELECTED OR 14, comparison block 15, trigger 16, decoder 17, NOT element 118, keys 19-21, error counters 22-24, | blocks 25-27 of memory, indicators 28-30 and | initial setup 31. Elements 1, 2, | 4-7 and 11 represent a control block 32.

I The device works as follows. I In the initial state at the output of the trigger; Gera 5 there is a low potential, which rises to control the inputs of keys 1 and 4 and prohibits the passage of syncro: Pulses to the synchronization bus 3, to the input of the divider 6 and the inputs of the AND elements 9-11 and 13. When impulse control Kfig is received on 1 bus 31. 2a) divider 6 is zeroed, counters | 8 and 22-24, trigger 16 and a high potential is set at the output of trigger 5. Keys 1 and 4 are opened. At the sync input of the divider 6, the clock pulses begin to arrive (Fig. 26). Divider 6 divides the frequency of the clock pulses with a division factor of 3. At the same time, impulse sequences are formed at the outputs of the decoder 7 (Fig. 2d, e and e), which are fed to the first, 1st inputs of elements II and 9 and 10, respectively. 13. At the second inputs of these elements, the delayed sync pulses (see Fig. 2c) are delayed (for example, by half of the period) by element 2. As a result, at the outputs of the elements 11 and 10, the first and second gating pulse sequences are formed (Fig. 2g and 3, respectively).

At the outputs of the elements And 9 and 13, low potentials are maintained, since their third inputs are connected to the trigger output 16. At the output of the latter, after the arrival of the installation pulse, there is a low potential, as the information input of the monitored unit 12 receives a low potential from the trigger output 16 then the first after the impulse of the impulse of the first gating sequence (Fig. 2g) is recorded “O to the cell of the memory unit with number 1.

In the interval between the first and second pulses of the first gating sequence, the monitored memory block 12 reproduces information from the memory cell with number 1 and cell with the number 2, since the negative edge of the pulse sequence from the output of the decipheror 7 to the synchronizing input of the address counter 8 occurs switching the addresses of the cells of the monitored unit 12. Then, the recording of “O into the memory cell with the number 2 and the reproduction of information from the cells with the numbers 2 and 3.” is performed. qi output from the controlled unit 12 postu5 paet a first input of a comparison circuit 15, a second input connected to the output of the EXCLUSIVE OR gate 14 to a first input of which receives a low level output from the flip-flop 16, and the second input - the impulse sequence with

0 of the third output of the decoder 7 (Fig. 2e). The resulting error pulses are received at the information inputs of the keys 19-21, the control inputs of which are connected to the outputs of the elements AND 9, 10 and 13, respectively. Keys 19 and 21 are closed by a low potential from the outputs of the And 9 and 13 elements. The control input of the key 29 receives a second strobing sequence (Fig. 2h), highlighting errors only during the reproduction of information from a previously recorded memory cell of the monitored block. 12, which makes it possible to detect faulty memory cells whose outputs have a constant high potential. Recording, reproduction, "O and Comparison of production 5 s to complete filling of all the cells of the monitored unit 12 with zero characters. The negative high-order front of the address counter 8, the output of which is connected to the input of the trigger 16, switches to the last and a high potential is established at its output, which arrives at the information input of the monitored unit 12 and allows the second and third gating sequences to pass (Fig. 2h, c) the outputs of the elements And 9 and 13 on

5, the control inputs of the keys 18 and 21, respectively. At the output of element 10, a low potential is established, since its third input receives a low potential from the output of element 18. The first pulse after switching the trigger 16

0, the first gating sequence in the cell of the monitored block 12 with the number is written "1 character. Then, the content from the memory cell with numbers 1 and 2 is played back. Next, "1 character in

5, cell number 2 and reproduction of information from cell numbers 2 and 3. The reproduced information is compared in comparison diagram 15 with the sequence received from the output of the EXCLUSIVE OR 14 element (Fig. 2k). The resulting error pulses are received at the inputs of the keys 19 and 21, where they are gated with the second and third gating pulse sequences (Fig. 2h, 2), respectively. Thus, when filling the memory cells of the monitored block with 12 single characters at the output of the key 19, errors corresponding to the memory cells are highlighted, and at the output of the switch 21, errors corresponding to the cells shorted between each other. The recording of "1 character, reading and comparison of the written and read information is carried out before filling all the memory cells of the monitored block 12 with 1 characters. The decoder 17 selects the pulse of the last address of the monitored unit, the negative edge of which switches the trigger 5, and the zero potential at its output blocks the keys 1 and 4. The error pulses from the outputs of the keys 19-21 arrive at the syncro. The counting inputs of counters 22-24, respectively, where they are counted and their number is displayed on indicators 28-30. In this case, the error pulses from the outputs of the keys 19-21, corresponding to the type of errors, record the addresses of the faulty cells of the memory block 12 specified by the address counter 8 into the memory blocks 25-27. The cell numbers of the memory blocks 25-27, in which the addresses of the faulty cells of the monitored unit 12 are written, are set by counters 22-24.

Claims (1)

Invention Formula I A device for monitoring memory blocks containing a control unit, the first sync output of which is connected to the counter input of the same name, the bit outputs of which are the device’s address outputs, and the overflow output connected to the trigger setup input, the decoder, the output of which is connected to the end sign input control of the control unit, the write-read output of which is the device output of the same name, the comparison unit, the first input of which is with the information input of the device, the NOT element distinguishing so that, in order to expand diagnostic capabilities by counting the numbers of cells that store a constant zero or one, or the number of shorted cells, the device is 0 element EXCLUDE OR, first, second and third elements AND, first, second and third keys, first, second and third error counters, the first and second sync outputs of the control unit are connected 5, respectively, with the first inputs of the first and second elements AND, and with the second inputs of the first, second, and third elements AND, the third synchronized output of the control unit is connected to the first inputs of the third AND element and the EXCLUSIVE OUTER OR element whose output is connected to the second input of the comparison unit and the second the input is connected to the trigger output, the input element is NOT, the third inputs of the first and third elements are AND, to the single input of the decryption unit is the information output of the device, the other inputs of the decoder are connected to the outputs of the address counter The output of the comparison unit is connected to the control inputs of the first, second and third keys, the pulse inputs of which are connected respectively to the outputs of the first, second and third elements AND, the outputs of the first, second and third keys are outputs of the device error indications and connected to the synchronous inputs of the corresponding error counters, the outputs of which are diagnostic outputs of the device, and the inputs of the initial installation are the same input of the device and are connected to the same inputs of the address counter, trigger The control unit, whose synchronization input is the one0 nominal device input, the element output is NOT connected to the third input of the second element I. a) TL ff) JIJLJL JlJUlJLJlJTJ n-JLJL 2J d e rL, fL L P L Compiled by O. Isaev Editor I. DerbakTehred I., VeresKorrektor O. Kravtsova Order 919/52 Circulation 590 Subscription VNIIPI USSR State Committee for Inventions and Discoveries 113035, Moscow, Zh-35, Raushsk nab. 4/5 Production and printing company, Uzhgorod, ul. Project, 4 g I P P l Vlz.2