SU1451708A1 - Device for interfacing digital computer with magnetic tape recorder - Google Patents

Abstract

The invention relates to computing and can be used to interface a digital computer with a tape recorder. The aim of the invention is to improve the reliability of the exchange of information for. auto-synchronization account to read information. The device contains channel 1 of the view, channel 2 of the input, generator 3 clock pulses. The device records and reads information from the tape recorder of the recording, providing synchronization of the read information, which increases the reliability of playback. 3 il.

Description

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The invention relates to computing and can be used to interface a digital computer with a domestic tape recorder.

The aim of the invention is to increase the reliability of information exchange due to auto-synchronization to the read information.

Fig with 1 shows a block diagram of the device; in fig. 2 is a block diagram of the output channel; Fig, 3 is a block diagram of the input channel.

The device (FIG. 1) contains channel 1 of the output, channel 2 of the input, generator 3 of clock pulses, information input 4, analog output 5 and output 6 of the output channel synchronization, analog input 7, information output 8 and output 9 of the channel synchronization la input, inputs si-ghronizatsii 10 channel output and 11 channel inputs

Channel 1 (Fig, 2) contains a frequency divider 12, the first trigger 13, the element AND 14, the element OR 15, the second trigger 16, the converter 17 of the square of the pulses into a sinusoid.

Input channel 2 (FIG. 3) contains a top level comparator 18, pulse generator 19, AND element 20, first counter 21, first, second, third triggers 22-24, reference element 25, second counter 26, multiplier 27, register 28, element OR 29 element 30 delay one-shot 31

The device works as follows:

In the information output mode, on the leading edge of the signal at the output 6 of the synchronization channel, the output bits of information from the digital computer arrive at the information input 4 of the output channel. The received information is remembered for the transmission time of one bit and with the help of the reference frequency received from the first output of the generator 3 sync-t pulses to the input 10 of the output channel 1 of the output, is converted into frequency oscillations corresponding to the transmitted information, and the zero information bit is coded twice less than a single bit of information. The start of the transmission of the corresponding bit is initiated by the leading edge at the output 6 of the transmission timing. The converted information is output to analog output 5 of the output channel.

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In the input mode, information from the tape recorder is fed to the analog information input 7 of the input channel. Channel 2 of the input decodes the received information, tracks the length of the bit interval, corrects it and provides information to the digital output 8 of the input channel. The issuance of information is initiated by the strobe at the output 9 of the input channel synchronization. The bit-length of the bit interval is determined using the frequency of the synchronization pulses coming from the second generator output 3 clock pulses to the input 11 of input channel 2, the clock 3 generator generates two pulse frequencies: to synchronize the transmission on the output channel 1 and to synchronize the input channel 2, In channel 2 of the input, the duration of the clock interval is determined relative to the frequency of the pulses at input 11, so the source of the pulses may not be stabilized.

Channel 1 of the channel works as follows

The transmission synchronization frequency pulses from the input 10 of the output channel 1 through the frequency divider 12 are fed to the synchronization input of the information trigger 13 and output to the synchronization output 6, the leading edge of the pulse from the output of the information divider 12, coming from digital input 4, is written to the trigger 13, trigger 13 is maintained until the next pulse arrives from the output of frequency divider 12. The modulated information is produced as follows.

If there is a zero at the output of the trigger 13, the synchronization pulses from the input 10 through the element 14 are forbidden. The pulses from the output of the frequency divider 12 through the element RSI 15 are fed to the synchronization input of the trigger 16 operating in the counting mode. On the leading edge of the pulse, the trigger 16 switches to the opposite state. At the output of the trigger 16, a rectangular pulse is obtained, the duration of which is equal to the repetition period of the pulses from the output of the divider 12 frequency by two. If in the trigger 13 single information is recorded, then from its output the passage of pulses from the input 10 through the elements AND 14, OR 15 to the synchronization input 10 is permitted

The institute of trigger 16, which in this case switches with a frequency twice as large as with zero transmission. Square pulses from the output of the trigger 16 through the transducer 17 square pulses into a sine wave are fed to the analog output 5 of the output channel. Such an information transfer organization makes it possible to track the length of the bit interval when receiving information from a tape recorder.

Channel 2 input works as follows.

The frequency-modulated sinusoidal-i 5 signals from analog input 7 are fed to the input of a comparator 18 of the upper level, which converts the sinusoidal voltages to square impulses of levels O and 1. The pulses from the output of the comparator 18 are fed to the input of the former 19 pulses, which forms a short pulse on each front (positive or negative) of the input voltage.

Until the signal arrives at analog input 7, channel 2 of the input is in the initial state. In the initial state, the counter 21 is in the cyclic counting mode and recalculates through the number of Ipuls, determined by the code at the output of the register 28, which is connected to the input of the input 7. The information outputs of the counter 26 are connected to the corresponding inputs of the multiplier 27, the output of which is connected with the entry of the storage register 28. Since the output of the counter 26 in the initial state is zero information, the output of the multiplier 27 is also zero information.

When the signal from the output of the recorder is semi-quenched, the pulse former 19 produces a short pulse that arrives at the first input of the element I 20 and at the input of the one-shot 31 and starts it. The signal from the output of the one-shot 31 through the element OR 29 removes the signal of the initial installation from the counter 26. At the same time, the pulse from the output of the AND element 20 passes to the input to set the initial state of the pulse counter 21, to the control input to the storage register 28 and to the input of the delay element 30. On the leading edge of this pulse, information about the length of 25 3/4 bit interval from the output of the multiplier 27 is written to the storage register 28. The multiplier 27 multiplies the number from the output of the counter 26 by the number 0.75. At the initial time, the zero storage information is written to the storage register 28.

The delay element 30 is designed to ensure reliable recording of in30

ka 21 o The output of register 28 can be in an arbitrary state. The overflow pulse from the output of the counter 21 trigger 24, the output of which is the accumulation of the division ratio of the counter - 5 formations from the output of the multiplier 27 in

the register 28 before setting the counter 26 to the initial state and for reliably zeroing the counter 21. After the time determined by the delay element 30, it is the only one with the second input of the element 20, 40 whose output through the element 1-ШИ 29 is set to one and resolves passing through the AND 20 pulses from the output of the pulse former 19, the One-Vibrator 31 in its initial state on the inverse output has a signal-1, which through the second input of the OR element 29 arrives at the installation input of the initial state of the counter 26 and keeps it in this state Nii.

The single-oscillator 31 is a stand-by multivibrator with a restart, generating a pulse of at least the duration of the bit interval at the lowest possible frequency of received signals, and is designed to keep the counter 26 in its original state until information signals appear on

connected to the installation input of the initial state of the counter 26, the counter 26 is zeroed. The pulse from the output of the element 30 is connected

45 also with the input to the zero setting of the trigger 24, a zero is set at the output of the trigger 24, which prohibits the pulse propagation through the AND element 20 earlier than the output of the pulse counter 21, an overflow pulse occurs. Counters 21 and 26 are filled with pulses from input 11 of channel 2 of the input to the inputs for synchronization of the counters. When the 5g -jom of the first pulse arrives at the synchronization input of the counter 21, an overflow pulse is generated at its output, and the trigger 24 is set to one state, from which 50

input 7. The information outputs of the counter 26 are connected to the corresponding inputs of the multiplier 27, the output of which is connected to the input of the storage register 28. Since the output of the counter 26 in the initial state is zero information, the output of the multiplier 27 is also zero information.

When the signal from the output of the tape recorder is semi-quenched, the pulse former 19 produces a short pulse that arrives at the first input of the AND element 20 and at the input of the one-shot 31 and starts it. The signal from the output of the one-shot 31 through the element OR 29 removes the signal of the initial installation from the counter 26. At the same time, the pulse from the output of the AND element 20 passes to the input to set the initial state of the pulse counter 21, to the control input to the storage register 28 and to the input of the delay element 30. On the leading edge of this pulse, information about the duration of 3/4 bit interval from the output of the multiplier 27 is written to the storage register 28. The multiplier 27 multiplies the number from the output of the counter 26 by the number 0.75. At the initial time, the zero storage information is written to the storage register 28.

The delay element 30 is designed to ensure reliable recording of the

register 28 before setting the counter 26 to the initial state and for relieving the counter 21. reliably. Through the time determined by the delay element 30, which output 0 through the element 1-XI 29

connected to the installation input of the initial state of the counter 26, the counter 26 is zeroed. The pulse from the output of the element 30 is connected

5 also with the input to the zero setting of the trigger 24, a zero is set at the output of the trigger 24, which prohibits the impulses to flow through the AND element 20 earlier than the output of the counter 21 pulses, an overflow pulse occurs. Counters 21 and 26 are filled with pulses from input 11 of channel 2 of the input to the inputs for synchronization of the counters. When the first pulse arrives at the synchronization input of the counter 21, an overflow pulse is generated at its output, and the trigger 24 is set to one state, from which 0 is

The output 9 of the device's reception synchronization, the passage of 1 pulses through AND 20 is permitted and the receipt of the information bit 11;

When the next front of voltage is output at the output of the comparator 18, a short pulse is formed at the output of the pulse former 19, setting through the element 20 of the counter 21 to the initial state. At the same time, the bit interval information 5 multiplied by the multiplier 27 by the number 0.755 is fixed in the register 28 is stored, and the counter 26 and the trigger 24 are reset to the initial state by a signal from the output of the delay element 30.

The duration of the bit interval is determined by the signals corresponding to zero information. If, at the initial time, a time interval less than the bit interval was captured during start-up, which can occur when a single information signal is received or when switching tape recorder is switched, then at subsequent moments, when the signals are received from the output of the tape recorder of the corresponding zero information, the transition to tracking the true length of the bit interval is automatically made. Thus, the duration of each subsequent bit interval is determined based on the previous one, and therefore, the rate of incoming information is monitored.

When receiving only one information from 4-stness for connecting analog

The signal level is measured in the middle of the bit interval, however, as a result of the pulse at the overflow code, the 21 Adapters counter appears after 3/4 of the bit interval, the trigger 24 by a zero signal from its output blocks the passage pulse through the element And 20 with the output of the shaper. 19 pulse Thus, the zeroing of the counters 21, 26 when receiving a single information in the middle of the bit interval does not occur. Ld of obtaining information about the length of the bit interval, you must have at least one bit of zero information 1,

Decoding information is as follows.

The value of the signal from the output of the upper comparator 18 is exactly in the middle; the second half of the bit interval is compared with the same value when receiving an order 1; its bit. If the signal does not change, then a single information is decoded; if the signal value changes to

opposite, the null information is decoded. The signals from the output of the comparator 18 are fed to the first input of the comparison element 25 and to the information input of the trigger 22, output

5 which is connected to the second input of the comparison element 25. The recording of information into the trigger 22 is made on the falling edge of the pulse from the overflow output of the counter 21, When receiving

0 the next bit on the leading edge of the pulse at the overflow output of the counter 21, the trigger 23 records information from the output of the comparison element 25, which compares the information

5 at the output of the comparator 18 with the information at the output of the trigger 22 recorded when decoding the previous bit. On the trailing edge of the overflow pulse information in the trigger 22

0 is being updated.

Claims (1)

Invention Formula A device for interfacing a digital computer with (a tape recorder containing an output channel and an input channel, the device input for connecting the information output of a digital computer connected to the information input of the output channel, the device output The input of the tape recorder is connected to the analog output of the output channel, the input of the device for connecting the analog output of the tape recorder is connected to the analog input of the input channel, the output of the device for connecting the information input of the digital computer is connected to the information output of the input channel, and the input channel contains the first trigger element AND element OR element and a converter of rectangular pulses into a sinusoid, and, in the output channel channel, the information input of the first trigger is connected to the information input channel of the output, the output of the first trigger co It is one with the first input of the element AND, the output of which is connected to the first input of the element OR, the output of the converter of rectangular pulses into a sine wave is connected to the analog output of the output channel, and the input channel contains a top level comparator, a driver of pulses, the first trigger and the first counter, and in the channel An input input channel input is connected via a high-level comparator to the input of a pulse driver, the discharge output of the first counter is connected to the synchronization input of the first trigger, different In order to increase the reliability of information exchange due to auto-synchronization to the readable information-jjjm, a clock generator was inserted into it, the first and second outputs of the clock generator are connected respectively to the sync inputs of the output channel and the input channel, the sync output of the output channel is connected to the output devices for connecting to the first input, synchronizing the digital computer, the output channel of the input channel synchronization is connected to the output of the device for connecting to the second synchronization input of the digital computer, and vedeny frequency divider and a second trigger, wherein the channel vshoda synchronization input connected to the second input of the AND gate and via a frequency divider - to the input of the first synchronization flip-flop, a second 30 of the register, through the delay element - with the second input of the OR element and with the zero input of the third trigger, the output of the OR element is connected to the jp6poca input of the second counter, the bit the input of the OR element and with the sync output of which through the output channel synchronization multiplier, the output of the OR element is connected to the synchronization input of the second trigger, the output of which is connected to the input of the rectangular impulse converter to the information input of the register, the output of which is connected to the information input of the first counter. 4 O / a the nusoid, where the input element contains the AND element, the OR element, the second and third triggers, the second counter, the one-shot, the reference element, the delay element, the multiplier and the register, and in the input channel the synchronization input is connected to the synchronization inputs of the first and second counters, output the top level comparator is connected to the information input of the first trigger and to the first input of the comparison element, the second input and output of which are connected respectively to 5 the output of the first trigger and the information input of the second trigger, the output of which is connected to the information output of the input channel, the bit output of the first counter is connected to 0 synchronization inputs of the second, third triggers, the output of the pulse generator is connected to the first input of the AND element and through the one-shot one to the first input of the OR element, output 5 of the third trigger is connected to the synchronization output of the input channel and to the second input of the element I, the output of which is connected to the counting input of the first counter, to the synchronization input 0 register, through the delay element - with the second input of the OR element and with zero input of the third trigger, the output of the OR element is connected to the jp6poca input of the second counter, the bit It is single with the informatonic register input, the output of which is connected to the information input of the first counter. /four J5 sixteen fius.2 6 (Ryo-3