SU1406748A1 - Discrete phase-shifting device - Google Patents

Abstract

The invention can be used in automatic control and monitoring devices in channels of digital tracking systems. The discrete phase shifter includes a reference oscillator 1, a switch 4, a one-shot 3, a D-flip-flop 7, B, a register 6, a persistent storage 5 and a frequency divider 2. The discrete phase-shifting device has an increased speed. 2 Il.

Description

ate

O5

4i

ABOUT:.

LKM-tny

iodine.

Pus. /

The invention relates to the pulse technique and can be used in the automatic control and monitoring devices in the channels of the output tracking systems.

The purpose of the invention is ps) improving the speed of the device.

FIG. 1 shows a block diagram of the proposed device; in fig. 2 - time diagrams of his work.

The discrete phase-shifting device contains a reference oscillator 1, a divider 2 frequencies, a one-shot 3, a switch 4, a persistent storage device (ROM) 5, a register 6, the first D-flip-flop 7 and the second D-flip-flop 8.

The output of the reference oscillator 1 is connected to the C-input C input of the N-bit splitter frequency 2 (DF), which can be implemented, for example, on the basis of a counter with a presetting of a given type code 5333IE7 whose output is connected to the input of a single-oscillator (OV) 3, the single-oscillator 3 generates a pulse whose duration and temporary position excludes the possibility of the frequency divider passing an output signal of the exhaust signal 2 by the divider 2. The information inputs of the RF 2 are connected to the N-bit output of the switch 4, which can be implemented, for example, On the basis of the 533KI116 microcircuit, which multiplexes two ropes into one, the first and second N-bit inputs of which are connected to the outputs of ROM 5 and register 6, the output of OB 3 is connected to the V-preset input of the splitter 2 frequency and clocking C -the input of the second D-flip-flop 8. The output of the D-flip-flop 8 is connected to the control input of the switch 4 and the R-input of the installation in O

the first D-trigger 7. The output of the trigger 7 is connected to the informational D-BXO- house of the trigger 8. The clockwise C input of the D-trigger 7 is connected to the Start bus, which serves to command the output signal of the device. The inputs of the register 6 are connected to the inputs of the code and the length of the Record, which is used to record the code in register 6.

The device works as follows.

In the initial state, in the absence of comans; a, 1, on the phase shift in input

d

five

0 5 o ...

five

five

The signal of the device, 1) triggers 7 and 8 are in the state O. Commutato) 5 4, to the control input of which the output signal of the D-trigger 8 is fed, is in a state that determines the connection to the information inputs the divider 2 is the N-bit code frequency recorded in the ROM block 5. At the output of the one-shot 3, a pulse sequence is formed with a repetition period equal to (Fig. 2) defined by the N-bit code of the ROM block 5.

When a start is received from the bus to the clocking C-input of the D-flip-flop 7 of the front of the pulse command for the phase shift of the output signal (Fig. 25), the flip-flop 7 is set to state 1 (Fig. 2c) and its high output signal goes to informational D - trigger input 8. The first following the command for the phase shift, the output pulse ОВ 3, which arrives at the clocking C-input - П-trigger 8, sets its front to its state 1 (FIG. 21). The high-level output of the D-flip-flop 8 sets the D-flip-flop 7 to the state o and switches the switch 4. As a result, an N-bit code is connected to the information inputs of the frequency divider 2, which was previously recorded in the register 6 via the code buses and the bus Record. The next output pulse OV 3 by its low level presets the splitter 2 frequency in accordance with the code found in register 6. This output pulse OV 3 sets its D-trigger 8 to its initial state (Fig. 21) out second signal which switches the switch 4 in its original state. The next output pulse OV 3 will be shifted in time by an amount C equal to

  on

where j is the code value in ROM 5;

i is the code value in register 6; F „is the frequency of the signal of the reference oscillator 1.

Subsequent output pulses. OV 3 signals will be formed over a time interval equal to T ,, which will correspond to a phase shift cf equal to

tf claims

A discrete phase matching device that contains the reference retiepaTop, a switch, a simultaneous two, two triggers and a register, whose input is connected to the input buses of the code, which differs from the fact that, in order to increase speed, a permanent memory and frequency divider are entered into it whose output is connected to the one-shot input, the information inputs of the frequency splitter are connected to the switch outputs, and the C-input of the frequency splitter is connected to the output of the reference oscillator, the outputs

read only memory

So many

Q

0

five

Sogdinops with 110 1gpmp switch commutators, second BX (uU i K (iTopi4-o are connected to the register outputs, the course of which is connected to the pinch Record}, and the triggers are also of the I-trigger type, while the clock input of the first The D-flip-flop is connected to the Start bus, and its information input is connected to the signal source of the logical unit, the output of the second D-flip-flop is connected to the control input of the switch and the installation input to the first D-flip-flop, the output of which is connected to the information input of the second D-flip-flop, clocking input which is connected to the output of one ovibrator connected to the output of the device, and the input of the preset frequency divider.

TMOHfC

zzzrp

Tn9n.

Claims (1)

Claim A discrete phase shifter containing a reference oscillator, a switch, a single vibrator, two triggers and a register whose input is connected to the input bus lines of the code is distinguished by the fact that, in order to increase the speed, a permanent memory is introduced into it a device and a frequency divider, the output of which is connected to the input of a one-shot, the information inputs of the frequency divider are connected to the outputs of the switch, and the C-input of the frequency divider is connected to the output of the reference generator, the outputs of the permanent storage device are connected to the first inputs of the switch, the second inputs of which are connected to the outputs of the register, the second input of which is connected to the Record bus, and the triggers are made in the form of D-triggers, while the clock input of the first D-trigger is connected to the Start bus, and its information input is connected to the signal source logical unit, the output of the second D trigger is connected to the control input of the switch and the installation input to О of the first D-trigger, the output of which is connected to the information input of the second D-trigger, the clock input of which is connected to the output of one-shot pa connected to the output of the device and the input of the preset frequency divider.