SU1220007A1 - Multiplying device - Google Patents

Abstract

The invention relates to the field of computing and is intended to multiply a pulse frequency signal by a code in a wide frequency range. The purpose of the invention is to increase the reliability of operation with rapid changes in the frequency of input signals. The device contains two counters, two controllable frequency dividers, a frequency divider, a clock pulse generator, two registers and two multiplexers. The goal is achieved by introducing a circuit for writing a single code to the highest bit of the counter when it overflows with a corresponding change in the frequency of the pulses taken, with a frequency divider through a multiplexer. 2 Il. with s

Description

The invention contributes to multiple devices, using SoloC in computer technology and automatic control devices to convert data from the frequency-pulse code, namely, to multiply the numbers specified in the frequency and slant code by the parallel code. type

The purpose of the invention is higher reliability of operation with rapid changes in the frequency of input signals,

The FIG shows a structural cx of a multiplying device; Figure 2 is a diagram of the input driver ig-shulsoB and the timing diagram of its work.

The multiplying device (FIG. 1) contains a generator of 1 clock pulses, a divider, 2 frequencies, the first 3 and the second 4 g-1 lx controllers 5, the first 5 and the second 6 controlled frequency dividers. first 7 and second 8 counters first 9 and second 0 registers J for 4 driver j input pulses output 12 devices 5 inputs 53 device code 1SH-1NY unit 14 and zero potentials of device5 information; device 6 input devices ,,

Shaper 11 input pulses (fig ,, 2} control trigger 17, first in 18 and second 19 one-shot

The connections shown in FIG. the dotted lines are not mandatory, and

IIepe the follower device works as follows

In the initial state after; the arrival of the previous input; mp,: on the falling edge of which the counts; c and counter 8 are reset to the zero state ,. impulseJ- and from the zero output of the divider 2 (or from the generator 1 clock pulses) through r-hul. Istek-sor 4 and Ugflav - the 1st divider 6 often Tbij ensuring the division of the input frequency by N. x de N - Ko, n, j fed to the inputs 13a start ;; filling the counter 7 If before the next input ig-pulse arrives, the counter 7 overflows j at its overflow output appears ig-puls, which switches over the counter 8, and the frequency of the input pulses fed to the input of the counter 7 decreases twice. At the same time, the overflow pulse is fed to the resolution enable input of the counter 8 When, at the old

The 2000th digit of the counter 7 is recorded by the e / scnitsa, and the remaining bits are zeroed out. Subsequently, when riepenojiHeiiHH occurs, everything repeats. 5 Thus, in the counter 7, all the snooze contains the code of the most significant bits of the binary sum of pulses received by the current time, which guarantees a relatively stable value of the relative error of the estimate of the period of the input pulses. When the next input pulse arrives, the counter in counter 7 stops j and the code from it is 15, is written to register 9, and the code from counter 8 is rewritten to re-1 and 10, the input code of which determines the frequency of the signal from 1 tsu: w at the input of the divider 5 of the frequency of 20 pulses and equal to the frequency of the pulses of the maximum of the ml-multiplexer 4 before the input signal was received.

Thus, during the next period, at the output 12, it is formed with the frequency Nf, i.e., an operative multiply with more than

This is an error of 1/2 p where K is the counter size 7 for all frequencies of the input signals, except for the case of operation in the zero range, when during the period of the input pulses the counter 7 fails half time aanonHHTbCjj.

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A multiplying device, containing a clock generator,

a frequency divider, two multiplexers, two controllable ones: a frequency divider you have two registers and two counters, and the output of the clock generator C is connected to the clock inputs of the first

and the second to the 1st, 11th, and the divider input, n frequency, the outputs of which are connected to the informational inputs of the second and second multiplexers 5. The input of the first m3 of the multiplexer is connected to the clock input of the first control-. The frequency divider under consideration, the output of which is; 01-o is connected to the output of the device, and information inputs to the outputs of the first register information inputs, which are connected to the outputs of the first counter, the counting input of which is connected to the output of the second controlled divide; the frequencies whose control inputs are connected to the device code inputs, and the information input to the output of the second multiplexer, whose address inputs are connected to the outputs of the second counter and the information inputs of the second register, whose outputs are connected to the address inputs of the first multiplexer, clock inputs of the first and second registers and the reset inputs of the first and second counters are interconnected, characterized in that, in order to increase the reliability of operation during rapid changes in the frequency of the input signal s, it is entered in the formation, Vatel input pulses, comprising a monostable flip-flop and two, the output of the overflow of the first counter is connected to the write enable input

20007

of the same counter and the counting input of the second counter, the information input of the higher bit of the first counter is connected to the unit potential bus, and the remaining information inputs are connected to the device zero potential bus in the input pulse generator, the trigger installation input is connected to the information input of the device, etc. my register output is connected to the input of the first one-shot, the output of which is connected to the input of the second one-shot, the output of which is connected to the second input of the second register and in Odom reset trigger input pulse shaper inverse output trigger pulse shaper input connected to the input of the first counter blokirov20 ki.

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Claims (1)

Claim A multiplier device comprising a clock 40 frequency divider, two multiplexers, two controlled frequency dividers, two registers and two counters, and the output of the clock generator is connected to the clock inputs of the first 45 and the second multiplexer and the input of the frequency divider, the outputs of which are connected to the information inputs of the first and second multiplexers, the output of the first multiplexer is connected to the clock input of the first controlled frequency divider, the output of which is connected to the output of the device, and the information inputs are with the outputs of the first register, information the inputs of which are connected to the outputs of the first counter, the counting input of which is connected to. the output of the second controlled frequency divider, the control inputs of which are connected to the inputs of the device code, and the information input - to the output of the second multiplexer, the address inputs of which are connected to the outputs of the second counter and the information inputs of the second register, the outputs of which are connected to the address inputs of the first multiplexer, clock inputs the first and second registers and the reset inputs of the first and second counters are interconnected, characterized in that, in order to increase the reliability of operation at fast changes in the frequency of the input signals, an input pulse shaper is introduced into it, containing a trigger and two one-shots, the overflow output of the first counter connected to the recording enable input of the same counter and the counting input of the second counter, the information input of the highest level of the first counter connected to the unit potential bus , and the rest of its information inputs are connected to the bus of the zero potential of the device) in the input pulse shaper, the trigger installation input is connected to the information input device, the direct output of the register is connected to the input of the first one-shot, the output of which is connected to the input of the second one-shot, the output of which is connected to the clock input of the second register and to the reset input of the input pulse shaper trigger, the inverse output of the input pulse shaper trigger is connected to the block input 2θ of the first counter. Figure 1 SECOND 5