SU1405074A1 - Interpolator - Google Patents

Abstract

The invention relates to a computational technique, in particular, devices for implementing functions, and can be used to reproduce the non-linear dependencies of one variable. The purpose of the invention is to improve the accuracy of the interpolator. For this purpose, an interpolator containing accumulating adder 8, multiplier 7, memory block 6, switch 4, converter 3 into an additional code, counter 1 and register 2, memory block 5 is entered. 1 ill., 1 tab.

Description

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The invention relates to computing, in particular, devices for implementing functions, and can be used to reproduce the non-linear dependencies of one variable.

The purpose of the invention is to improve the accuracy of the interpolator.

The drawing shows the functional-: on the interpolator circuit.

Interpolator contains counter, register 2, converter 3 to doO

00500AA0000220000 10 00 OE E O O 00 O O 66 00

The functions are calculated based on the following relationships. Let 25 be the number formed by K by the leading terms of the argument X, where 2 K 4 m-1; go, is the length of the binary code of a number. The number X. is the node point number. Let iX be the number formed by m-K by the lower-order bits of the argument X so that X X + yХ 2, О 4Х. Then, using the formula -v, n interpolation by cubic Hermitian splines

35

(X) (X.) - 8 (dХ) + (X;) - 30 (lH) +

 f (X, 4,) -SOd-AX) f (X. + j) -S (l-dX) N1 + .N2 + N3 + N4 ,.

where f (X.,), f (X.), f (X.J, f (X ;,) -values of the function at the nodal points; SO (4X) s SI (4X) are basis functions. 45

The interpolator works as follows.

Before starting work in block 6, the memory records the function values at the nodal points with a shift by one CQ address so that the i-th value of the address code corresponds to the value of the function f | X;,).

In the initial state, the register 12 is reset, the address input of the ROM 11 nodan is logic level zero, the zero state of the outputs of the ROM 11 is zero. A clock is fed to the input of register entry 12. With a supplementary code, switch 4, memory block 5 and 6, multiplier 7, accumulating summator containing adder 8 and result register 9, and control block 10 containing, for example, read-only memory (ROM; 11, register 12 , element AND 13, element AND-NOT 14 and element 15 delay.

An example. firmware ROM 1 1 is shown in the table.

8 9

AT

C D

code 0101 appears at the start input of the single signal at the output of the ROM. After that, the arrival of each leading edge of the clock pulse corresponds to a new cycle of operation.

In the first cycle of operation, register 12 is written to od 0101, and the code 0010 appears at the output of the ROM. The signal from the fourth output of register 12 and the delayed clock pulse from delay element 15 form a negative pulse at output of AND-HE element 14, according to which counter 1 and register 2 are entered into the information from the interpolator input and set to zero. 9. The code of the high-order bits of the variable from counter 1 determines the address of the first interpolation node. At the output of memory block 6, the value of the function f (X,) appears. The direct code from register 2 through switch 4 is fed to the input of block 5, the output of which is assigned the value of the basis function 3 (LH) 5 because the control input is fed to the unit level from the second output of the register 12. Multiplier 7 multiplies the value of the function f (X, VT) by the value of the basis function 51 (xX). The calculated product is summed with the zero register code 9. In cycles from the second to the fourth, the interpolator works in a similar way.

In the fifth cycle, code 0110 is written to register 12, and code 0000 appears at the output of ROM 11.

the edge of the pulse from the element And 13 in the register 9 is written to the value f (X).

The next clock pulse writes code 0000 into register 12, returning the device to its initial state.

For functions that have a continuous third derivative in each interpolation interval, the error is .3

5 t 96 m ks

(X) - h

Claims (1)

Invention Formula Interpolator containing nakapli-. The adder, multiplier, first memory block, switch, converter to additional code, counter and. a register whose output is connected to the first information input of the switch, and the output of the first register bit is connected to the control input of the switch, the second information input of which is connected to the output of the converter to the additional code whose input is connected to the output ten 15 20 25 the register whose information input is the input of the lower bits of the interpolator argument, the input of the higher bits of which is connected to the input of setting the initial value of the counter1 (and the output of which is connected to the address input of the first memory block, the output of the multiplier is connected to the information input of the accumulating adder, the output of which is the output of the interpolator house, the inputs for recording the data of the counter and the register, and the reset input of the accumulating adder are connected to the input of the initial setting of the interpolator, the counting input of the counter and the synchronization input of the accumulating adder is connected to the clock input of the interpolator, which is due to the fact that, in order to predict the accuracy of the interpolator, a second memory block is inserted in it, the output of which is connected to the input of the first multiplier of the multiplier, whose input connected to the output of the first block of memory, and the output of the switch is connected to the address input of the second memory block.