SU1425841A1 - Digital filter with linear delta-modulation - Google Patents

Abstract

The invention relates to computing and communication technology. Its use in systems of digital information processing allows to increase the speed of a digital filter. The latter contains a linear delta-modulator 1, binary counters 2 and 3, a clock generator 4, a RAM block 5, an OR-NOT 8 element, a fixed memory block 9, Jlutchix 10, an equivalence element 11, a formation block 12 pulses, a reversible counter 13, accumulating adders 14 and 15 and a digital-to-analog converter 16. By introducing the element B and the BAN 7, synchronous reading of the quantization steps of the input signal — and the impulse response values of F1-shtra — is achieved, which reduces time costs on computation convolution. 1 hp f-ly, 3 ill.

Description

By this value, as a result of this 25 analog output converter and output 18, a count is formed that is outputted by the first filter outputs, a filter signal y (in pulse code modulation format), which is converted by analog-digital converter 16 to analog form y (t) exit 19.

Thus, in a digital filter with linear delta modulation completely. no overhead for recording accumulated

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A serial generator, the output of which is connected to the counting inputs of the reversible and first binary meters and the first input of the pulse shaping unit, the first output of which is connected to the synchronization inputs of accumulating adders, the second binary counter, the OR-BIN element, the output of which is connected to the control input zero

the values of the products and the delay of the timeframe type 35, the output of the overflow of the analogue converter and the first outputs of the filter, also

A comma generator whose output is connected to the counting inputs of the reversible and first binary meters and the first input of the pulse shaping unit, the first output of which is connected to the synchronization inputs of the accumulating adders, the second binary counter, the OR-BIT element, the output of which is connected to the control input zero

Names for the formation of addresses of the RAM block. The introduction of blocks 6 and 7 and the corresponding connections allows synchronous reading of the quantization steps of the input signal and values of the impulse response from the memory blocks, which reduces the time required to calculate the convolution (2) to

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the reading time from blocks 5 and 9 of the next 50 values of quantizing steps, the execution time of the multiplication operation by element 11; 55 time change state of the reversible counter 13 "

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This binary counter is connected to the clock input of the linear delta modulator, the output of the digital-to-analog converter is the third output of the filter, which is used to enter the filter: r. ; And the element and the banned, allowing the input of which is connected to the output of the clock generator., the output of the linear delta modulator is connected to the first information input of the multiplexer and information input of the RAM, the output of which is connected to the second information input of the multiplexer whose output is connected with the second input of the equivalence element, all the bits of the first binary counter are connected to the address inputs of the RAM block and the inputs of the AND element whose output is connected to the inhibiting The element of the pulse generator and the second input of the pulse shaping unit, the second input of which is connected to the installation input of the reversible counter, the control input of the operating memory unit is connected to the output of the element OR NOT, the output of the BAN element is connected to the input of the second binary counter, the outputs of which are connected to the inputs block of permanent memory and an element OR-KE.

2. A digital filter according to claim 1, characterized in that the pulse shaping unit is executed on the shift register of the leading edge driver, the OR element and the AND element, the output of which is connected to the transducer

the primary input of the element or, the output of the first bit of the shift register is connected to the first input of the element I, the second of which is combined with the input of the sync; the phonization of the shift register and is rm with the first input of the block, the outputs of the remaining bits of the shift register are connected to the same the inputs of the OR element, the output of which is connected to the input of the front-edge former and is the first output of the block, the information input of the shift register and the output of the front-edge former are the second input and output of the block, respectively.

Claims (2)

The claims are values, as a result of which at the output of block 14 is formed the value of E y _p . At the same time, a short pulse is generated at the second output 27 of block 12 (Fig. Zi), which arrives at the input of setting the zero state of the reverse counter 13, as a result of which (the outputs set the signal value to zero, which prepares the next accumulation cycle according to formula (2). The pulse duration from the output 26 of block 12, equal to the integer number of periods of the signal of the clock generator 4: is selected sufficient to perform the summing operation in block 14 and can be changed by changing the number of consecutive outputs of the shift register 20 connected to the inputs of the OR element 22. Therefore, by the falling edge of the signal from the output 26 value: Vy _n, c output unit 14 is written in the j unit 15 where it is summed with the pre 'value preceding case, a result of this the output 18 is formed readout filter output signal y _h (a pulse-format odovoy modulation), which is converted by DAC 16 to an analog form y (t) at the output 19. Thus, in a digital filter with linear delta modulation, the unproductive time spent on writing the accumulated values of the products and the delay in the formation of the addresses of the RAM block are completely eliminated. The introduction of blocks 6 and 7 and the corresponding connections allows you to synchronously read the quantization steps of the input signal and the impulse response values from the memory blocks, which reduces the time required for convolution calculation (2) to TD ^& * -SW ^ MIHS E ^ THU ⁴ >'-sts'] _? ^t C4 reading time from blocks 5 and 9 of the next values of the quantization steps .; ¹ execution time of the operation of multiplication by element 11; time change state of the reverse counter 13., 1. A digital filter with linear delta modulation, comprising a linear delta modulator, the information input of which is a filter input, a random access memory unit, a read-only memory block, the output of which is connected to the first input of the equivalence element, the output of which is connected to the control input of the reversible counter, outputs which is connected to the information inputs of the first accumulating adder., the outputs of which are connected to the information inputs of the second accumulating adder, the outputs of which are connected to the digital inputs of the analog-to-analog converter are the first outputs of the filter, a clock generator whose output is connected to the counting inputs of the reverse and first binary counters and the first input of the pulse forming unit, the first output of which is connected to the synchronization inputs of accumulating adders, the second binary 'counter, OR-HE element, output which is connected to the control input of the multiplexer, the overflow output of the first binary counter is connected to the clock input of the linear delta modulator, the output of the digital-to-analog conversion is the second output of the filter, characterized in that, in order to improve performance, the AND element and the PROHIBIT element are inserted into the filter, the permitting input of which is connected to the output of the clock generator, the output of the linear delta modulator is connected to the first information input of the multiplexer and information input of the RAM block, the output of which is connected to the second information input of the multiplexer, the output of which is connected to the second input of the element, equivalence, the outputs of the bits of the first binary counter sub yucheny to the address inputs of the memory unit and the inputs of the AND, whose output is connected to the inhibit input element and the second inverted input of the forming impul1 1425841 8 owls, the second output of which is connected to the installation input of the reversible counter, the control input of the RAM block is connected to the output of the OR-NOT element, the output of the FORBID element is connected to the input of the second binary counter, the outputs of which are connected to the inputs of the permanent memory unit 'and the OR- NOT. 2. The digital filter according to claim 1, characterized in that the pulse generating unit is made on a shift register, a leading edge shaper, an OR element, and an AND element, the output of which is connected to the first input of the OR element, the output of the first: shift register register connected to the first input of the AND element, the second input of which is combined with the synchronization input of the shift register and is the first input of the block, the outputs of the remaining bits of the shift register are connected to the same inputs of the OR element, the output of which is connected to the input of the front driver of the front and is the first output of the block, the information input of the shift register and the output of the shaper of the leading edge are the second input and output of the block, respectively. FIG. 2