SU1742997A1 - Residual class system code-to-voltage converter - Google Patents

Abstract

The invention relates to computing and can be used to interface computing devices operating in the system of residual classes with various terminal analog devices. The purpose of the invention is to increase the speed and simplify the converter. The converter of the code of the system of residual classes to voltage contains n registers 1.1-ln, the converter 2 codes, (p-1) summator 3.1-Z.P-1 modulo the bases of the system of residual classes, additional register 4, n digital-analog converters 5.1-B.p., analog adder 6. block 7 for outputting a result, block 8 for control, input information bus 9, output bus 10 and bus 11 Start of conversion. A positive effect is provided by the improvement of the algorithm for converting the code of the system of residual classes into a binary code. 1 hp f-ly, 1 ill., 1 tab. V and

Description

Z.p-1

9.1

2

yu yu

H) 4

The invention relates to computing and can be used to interface computing devices operating in the residual class system (SSC) with various terminal devices requiring analogue output, as well as in communication technology when using SSC in digital telephony.

The purpose of the invention is to increase the speed and simplify the converter.

The drawing shows a flowchart of the SOC to voltage converter.

Converter SOK to voltage contains input registers 1.1-1.P according to the number of bases of the system of residual classes, converter 2 codes, adders ЗЛ-З.п-1 modulo SOK bases, except the smallest, additional register 4, digital-to-analog converters 5.1- 5. p, analog adder 6, result output block 7, control block 8, input buses 9.1-9. P., Output bus 10, bus 11. Conversion start. The control unit 8 is configured on a pulse distributor 12, an AND element 13, an RS flip-flop 14, a pulse generator 15 and an element 1 & delays.

The converter works according to the following principle.

The number X represented in the SOC by the bases pi, paРп residues xi, X2хп

in the generalized position system (OPS), is written as follows:

X ai + Э2р1 + эзр1р2 + ... + anpip2 ... рп-1.

(one)

Find the coefficients ai, with their help, you can get the voltage Ux X-A,

Let X, Xi, Xa, .... Xn be integers in the number system of residual classes, so that

X (X1, X2Hp)

.0) .0)

Xn)

(2)

and X, X | Ј P - 1 for t 1, 2n, where P

 P1 P2 ... Pn.

Since Xi is a number in the O-P-1 region, Xi in the generalized positional system has the form

Xi (0, 0ai, en-1p)

OR X | - 8 | Р1 ф2 ... РМ + 31-М Р1 Р2 ...

pi + ... + an pi P2 ... Pn-1 (3)

From equations (2) it follows that the number X can be written as the sum of residual representations modulo P:

X, Х2Хп) ф1, 00) + (О, Х2. 0 ..., 0) +

... + (0, 0xn) s (xi + x2 + ... + xn) mod P

(four).

Then the digits of the sum Xi (the numbers X) in the OPS can be obtained from the digits Xi in the generalized positional system by the rule: the digit ai in the representation in the OPS is obtained by summing up the modulo PI of all the digits XL

Hah in representation in generalized

positional system and transfer, formed upon receipt of AM.

Consequently, on the basis of (2) - (4) A °, it is enough to calculate the coefficients of a generalized positional system of numbers

(O, 0, xi, 0 0), where I 1, 2 p to

by simple summation get the desired

coefficients ai of the number (xi, X2хп).

Example. We select the bases of the RCC pi 3, p2 5, pz 7 and draw up a table of coefficients ai numbers (0, xi, 0) by transferring them to OPS.

We transform the number X 82 (1, 2, 5) into a generalized positional system, for which we divide X into components Xi and choose from the table the corresponding coefficients, (xi. 0. 0) (1, 0, 1, 32 3, az 4; (O, X2, 0) - (0, 2, 0) - “and - 0, a2 - 4, az - 2; (O, O, xs) (0, 0, 5) O, 32 0, az 5 Using the rule, we get

transfer is taken into account 5 transfer is not taken into account

Produced summation by module, taking into account the carry, except for the last one, which is not taken into account, finally obtained

X (1, 2; 5). Verification shows that, indeed,

X ai + az Pi + az pi f2

 1 + 2-3 + 5-3-5 82.

Converter code JUICE to voltage works as follows.

In the initial state, the number to be converted into a voltage is written to the input registers 1, accumulating the adders 3 and the additional register 4 are zeroed. A short pulse is applied via bus 11 to the S-input, which sets the RS flip-flop 14 into one state, thereby allowing the passage of clock pulses from the generator of 15 clock pulses through the AND 13 element to the input of the distributor 12 pulses. At the outputs from the 1st to the nth distributor 12 pulses, pulses will start appearing at the second outputs of the control unit 8 and further to the control inputs of the transducer 2 codes. The converter 2 of the code can be executed as a combinational device or as a long-term memory with an address block and its task is to issue the coefficients ai, 32 ap generalized

position system for residues xi. For example, for the selected SOK and the number (1, 2.5) in the first clock cycle on the remainder xi 1 from the converter 2 codes, coefficients ai 1 and 32 3, az 4 will be output, which will be written into additional register 4 and adders 3 modulo except the smallest, respectively. In the second cycle, the remainder X2 2 from the converter 2 codes will be given the coefficients 32 4. A 2 which will be written to the adders 3. The transfer that is formed in the adder 3 modulo 5 when the numbers 3 and 4 are added will go to the input of the next adder 3 ( modulo 7). Similarly, in the third clock cycle on the xs 5 remainder of converter 2 of the code, a factor of 5 will be issued, which is summed up with modulo 7's adder 3 (the transfer from the last adder is not taken into account) and, therefore, the additional register 4 and adders 3 will write 1 , 2, 5. All signals aj corresponding to the residuals recorded in the input registers 1 will be output from the signals of the control block 8 from the converter 2 of the code. At the (pN) -th clock cycle the pulse is at the (n + 1) -th the output of the distributor 12 pulses, which post IT on

five

the first output of control unit 8 and the input of delay element 16. The signal from the first output of the control unit 8 will allow the output of information (numbers ai) from the additional register 4 and adders 3, which will go to the inputs of digital-to-analogue converters 5 having a quantization step, respectively

1 D.P1 A, Pi P2 A

t

Pi-Pz ... Pn-i D. Thus, in digital-to-analogue converters 5, the values ai will be multiplied by the corresponding quantization steps and the products obtained will go to the input of the adder 6. Finally, the output value of the adder 6 will be obtained

Ux ai A-f 32 pi

+ an pi P2

Pn

D + ... 4- -i -A X- A

five

0

five

0

five

O

five

The signal arriving at the third output of the control unit 8 from the output of the delay element 16 will open the result output unit 7 and the desired voltage can be read on the bus 10. In the same cycle, a single signal is fed to the R input of the RS flip-flop 14 and sets it to the zero state, by prohibiting the passage of clock pulses through the element I 13, and on the input buses 9 to registers 1, the next number is written to the RNS to be converted into voltage. After zeroing the adders 3 and the additional register 4, the conversion can be continued.

Claims (2)

1. Conversion of the code of the system of residual classes into a voltage containing n registers by the number of bases of the system of residual classes whose inputs are the input buses of the code being rewritten, the control unit whose input is the input bus of the transformation start, and the first output is connected to the control. inputs (p-1) adders modulo m, except for the smallest, the bases of the system of residual classes, the first inputs and outputs of the 1st of which, where I 1, 2 (p-1), are connected with the corresponding l-th outputs of the code converter and with the inputs (+1) of the digital-to-analog converter respectively, the output of which is connected to (the corresponding input of the analog sum j-mater, the first input of which is connected to the I output of the first digital-to-analogue converter-.l the receiver, and the output is connected to the input of the output unit 1, the output of which is an output bus characterized in that. that, in order to improve speed and, - / simplify the converter, an additional register is entered into it, the inputs and outputs of which are connected to the corresponding additional outputs of the code converter and the inputs of the first analog-to-analog converter, respectively, and the control input is connected to the first output of the control unit, the second output of which is connected to the control input of the output unit, and the group of outputs is connected to the corresponding control inputs of the code converter, whose information inputs are th register connected to the respective outputs vy10 15 base of the system of residual class | except for (n-1) -th, is connected to the second in (1 + 1) -th adder modulo-based residual classes system. 2. The converter according to claim 1, that is, the fact that the control unit is in the form of a pulse distributor, RS is a ger. And, the pulse pulse delay element, whose output is connected to the first input of the device. And swarm the input and output of which are connected with the output RS Tpnrrepa and the pulse distributor, and the outputs left are the output group of the block, the output the input of the element is delayed by the R input of the RS flip-flop, the S input of which is the input of the block, the output of the element OtlidO 1 vr w ff4f w - / - - - ii i / ITIC BAw / twlTl “W / L% w 1 the transfer paths of the l-ro modulo adder is the second output of the block. 20 t 0 five the base of the system of residual classes, | except for (n-1) -th, is connected to the second input of the (1 + 1) -th adder modulo the base of the system of residual classes. 2. The converter according to claim 1, that is, in that the control unit is designed as a pulse distributor, an RS flip-flop. An element, a delay element and a pulse generator, the output of which is connected to the first input of the element And, the second input and output of which are connected respectively to the output RS Tpnrrepa and the input of the pulse distributor, n outputs of which are a group of outputs of the block, (n + 1) - i the output is the first output of the block and is connected to the input of the delay element and the R input of the RS flip-flop, whose S input is the input of the block, the output of the delay element / ITIC BAw / twlTl "W / L% w 1 Jack is the second output of the block.