SU1562972A1 - Servo analog-to-digital converter - Google Patents

Abstract

The invention relates to the field of automation and computer technology and can be used to convert rapidly changing analog signals into a digital code. The invention makes it possible to improve the accuracy of converting an analog value to a code by reducing the dynamic error. To do this, the next analog-to-digital converter containing a zero-body 12, a subtractor 11, a digital-to-analog converter 7, a reversible counter 1, the first accumulating adder 2, two multipliers 3 and 4 multiplications, a generator 8, controlled by voltage, block 9 module extraction and distributor 16 pulses. 1 il.

Description

The invention relates to computer-aided computing and can be used to convert high-speed analog signals.

IN DIGITAL CODE

The drawing shows the functional diagram of the Converter.

The next analog-to-digital converter contains a reversible counter of pulses 1, accumulating adder 2, first 3 and second 4 multiplying blocks, accumulating adder 5, digital adder 6, digital-analog converter 7, generator 8 controlled by voltage, block 9 allocating module , input bus 10, comparison unit 11, containing zero-body 12 and subtractor 13, output bus 14, clock bus 15, distributor 16 pulses.

The next analog-to-digital converter operates as follows. In the initial state, the reversible counter of pulses 1, the adders 2.5 and 6 are in the zero state (the installation diagram in 0m is not shown). The input bus 10 receives the signal to be analog-to-digital conversion. Using clock pulses arriving at the clock bus 15 and pulse distributor 16, the discretization step of the analog-digital time conversion is set. The generator 8, controlled by voltage, at zero voltage at the output of block 9, the module produces a pulse with a frequency f 1 / t, where t.HCKp is the sampling time step, and with increasing difference between the current value of the input value and the signal with the DAC 7 modulo, which allocates the module 9 allocation module, the frequency of the pulses from the generator 8 increases proportionally,

The value of the signal at the output of the zero-organ 12 determines the counting direction in the reversible counter 1 pulses. Moreover, if the output of the zero-body is 1, then a sum operation is performed, if O is, then the subtraction operation.

As soon as the magnitude of the difference between the input signal and the signal coming from the output of the CDL 7, at discrete instants of time, reaches the level of the zero-body response 12,

o

five

0

five

0

five

0

five

0

the output generates a logic unit level signal, which is fed to the control input of the pulse 1 counter reversal. Depending on the magnitude of the difference in modulus, the number of pulses in one reversal pulse is recorded in a reversing pulse counter 1 proportional to the second derivative of the input signal at a given time, Further, the code of the pulse counter 1 is summed by the signal taken from the first output of the distributor 6 pulses using a digital adder 2 with the code recorded in its memory on the previous In the conversion step, as a result, at the output of accumulating adder 2, a code is generated that is proportional to the value of the first derivative of the signal being converted at the current sampling time. Subsequently, the estimates of the second derivative and the first derivative of the input signal are fed to the inputs of multiplication blocks 3 and 4 these estimates are fixed coefficients, which are defined by -. Under the condition of stable operation of the A / D converter, the second cycle of operation of the 16 pulse distributor is summed using the accumulating adder 5 of the output code of the accumulating adder 2 with the code recorded in the accumulating adder 5 in the previous conversion cycle. In the third operation cycle of the distributor, the output codes of multiplication blocks 3 and 4 and the drip adder 5 are summed up using a digital adder 6. Subsequently, the digital ad analogue converter 7 converts the output code of the digital adder 6 to an analog value that is subtracted from the input the signal and using the null organ 12 determine the sign of the tracking error, etc. Based on the algorithm of the next ADC, digital memory adders should provide both summation of codes and their subtraction. This is done using an additional code, which can be obtained by the fact that the most significant bit of the reversible pulse counter 1, as well as the accumulating adders 2 and 5, are significant. If all the listed significant bits are 0, then the output 15 if 1 -

dit is the summation operation, then the subtraction.

At the instants of sampling the input signal with respect to time, a signal proportional to the absolute value of the error signal Ј (t) appears at the output of the module allocation unit 9. In this case, from the generator output 8, pulses are received at the counting input of the reversible counter 1 pulses, whose frequency is proportional to | Ј (t) | . The number of pulses recorded in the reversible counter 1 at time t (sampling time) is determined by the expression

X (t) X (t) + h sign (t) (f + using respectively the first j

c / 2

second 4 multiplicators,

+ f / Ј (t) I) d

(one)

where h0 is the counting unit of the reverse

pulse counter; X (tc) is the number of pulses recorded in a reversible pulse counter at time t0j

X (t) is the number of pulses recorded in the reversible pulse counter at the current time;

signЈ (t) -3HaK of the error signal, which determines the counting direction;

fQ is some initial sampling rate corresponding to the zero value of the error signal Ј (t).

The operation of the rest of the circuit is synchronized by pulses from the distributor of 16 pulses, the period of which is constant T0 const.

At each moment in time, at the output of accumulating adder 2, a code appears equal to the sum of the code at the outputs of the reversible counter 1 and the code written in the memory register. This code corresponds to the value of the coordinate at the output of the memory accumulator at time t0 (k-l) T0 The accumulative accumulator 5 works in the same way. Thus, at clock points, the output coordinates of memory accumulators change according to the law

N (kT0) N (k-l) T0J + h (kTe), (2) where N (kT0) -H are the output co-N (k-l) T0J ordinates of memory adders at discrete instants of time kT0 and (k-l) T

about

is the value of the input coordinate of the memory adder at the time instant kT0. to formula (2) Z-transform

AE, find the transfer function of the memory adder,. N (Z) Z

w (z) h (z) En -

(3)

15

At each clock point, the code that arrives at the inputs of memory accumulators is multiplied by

constant coefficients about (and

using respectively the first j

c / 2 С

and

using respectively the first j

second 4 multiplicators,

Taking into account formula (3), the Z-transformation of the compensation voltage II ,, at the output of the D / A converter 7 at discrete instants of time is

UK (Z) 0 (1 X (Z) + o (, + (| -) 7X (Z),

(z)

(four)

where X (Z) Z is the image of the output signal (CT2) 1 at discrete instants of time kT0.

Let us consider the dynamic error of the proposed following ACI. In this case, the generator 8 is an inertialess linear element, i, e, its frequency linearly depends on the error signal

fOP k rSMfЈ (t) l.

In equation (1), the discrete time-time factor kT0 is substituted for the current time t, and instead of 10 (k-l) T0. If the time interval T0 is chosen sufficiently small, on which we can assume that Ux const, then equation (1) can be represented as

X (kT0) X (k-I) T0 + h0f0T0signЈ (kT0) -f

+ T0krSH Ј (kT0)

(five)

The initial frequency of the generator 8 can be selected from the ratio

fo i / to,

the value of the additional signal in equation (5) is equivalent to the quantization noise

y (kT0) h0foT0sign Ј (kT0), will not exceed the counting unit of the reversible counter L0. In the following, we can assume that

The ADC is large enough and the quanto vania noise can be ignored.

Applying the Z-transform to equation (5), obtain an image of the output coordinate of the reversible counter 1,

ZT0 kr

X (z)

Z-l

i "fe (z)

(6)

Since the Z-signal transform

the mismatch and input signal are related by

Ј (Z) UX (Z) - Uk (Z),

Equation (6) is substituted into Equation (4) and, taking into account the last equation, the transfer function of the next-to-ADC

fm ()

) - () 3 + Tekr ,, Hr (I-Z) 4 + eC40-Z-) -H;

(7)

Giving in to the input of the next ADC current

Ux (t) signals

(g

 0,1,2,3, ...), it is easy to find the values of the corresponding established errors at discrete points in time.

In particular, if a parabolic function Ux (t) R / 2-t2 is taken as the input signal, for this matrix the Z-transformation is

T1 / 7h - bnzCZ + ii UW 2 (Z-1) 3

Then, substituting the last expression in equation (7), we determine the steady-state error at the time of closure

 T-ilisbC 2 Ј (z):

about

(eight)

".

Thus, after the decay of the transition process in the proposed next ADC, the latter can accurately track the parabolic input function.

By the appropriate choice of parameters, the footprint of the current ADC: TQ, kri) H, o ((

0 (4 provides stability of the transient process in the next ADC. In particular, the following parameters are chosen:

Values from ratios:

that () re

M

"/.- d

about (2

1 hch

(Y- &

- m /

Lo (9)

Where

p is the time constant of the next-to-right ADC.

Then the listed parameters are selected from the condition of the roots of the characteristic equation of the following ADC

i-zHs (bЈ, 3 + H "(-) H

/ U () 4-1-0 about

(YU)

0

25

thirty

35

40

45

50

55

in the circle of radius 1 / Т0 with the center at the point (-1 / Td, J0, the necessary quality of the ne-1 transition process can be ensured, in particular, the absence of oscillation.

In order for the next ADC to track input signals fairly quickly, the value of | must be chosen from the conditions

2

Tone

and).

 max where WMC, RC- the maximum frequency

Claims (1)

input signal Ux. Invention Formula A next analog-to-digital converter containing a serially connected digital-analog converter, a comparison unit, a reversible pulse counter and a first accumulating adder, the second inputs of which are connected to its corresponding outputs, the second input of the comparison unit being input bus, characterized in that the accuracy of the transform ... not by reducing the dynamic tracking error, a second accumulating adder, a digital adder, two multiplication units, a selection unit Odul, pulse distributor and generator controlled by voltage, the output of which is connected to the clock input of the reversible pulse counter, and the input to the output of the allocation unit of the module, the input of which is connected to the second output of the comparison unit, the outputs of the reversible pulse counter through the first multiplication unit are connected to corresponding to the first inputs of the digital adder, the second and third inputs of which are respectively connected to the corresponding outputs of the second accumulating adder and to the corresponding outputs of the second block multiplying, the inputs of which are combined with the corresponding first inputs of the second accumulating adder and connected to the corresponding outputs of the first accumulating adder, the second inputs of the second the accumulating adder is connected to its corresponding outputs, and the clock inputs of the digital adder, the first and second accumulating adders are connected respectively to the first, second and third outputs of the pulse distributor, whose input is the clock bus, and the outputs of the second accumulating adder are output bus, and the outputs digital adder connected to the corresponding inputs of the digital-to-analog converter.