RU2744337C1 - Digital-to-analog converter in a residual class system - Google Patents

Abstract

FIELD: computing technology.SUBSTANCE: invention relates to the field of automation, information-measuring and computing technology and can be used to convert a modular code into an analog electrical signal. The essence of the invention lies in the formation at the output of the analog equivalent of the input digital value according to the functional dependence: f(ϕ)=[1+sin(ϕ)-cos(ϕ)]/2.EFFECT: technical result consists in increasing the conversion accuracy. An additional effect is increase in functionality, expressed in the application of the entire volume of numbers P of a given system of residual classes.1 cl, 2 dwg, 3 tbl

Description

The invention relates to the field of automation, information-measuring and computing technology, and can be used to convert a modular code into an analog electrical signal.

A device is known (US Pat. 2253943 C1, Russian Federation, IPC Н03М 1/66 (2006.01). Appl. 12/22/2003; publ. 06/10/2005.), Containing information inputs, display devices, harmonic oscillator, phase shifter at the angle π / 2 , controlled phase shifters, analog multiplier, integrator, output. The disadvantage is low accuracy.

Known device (US Pat. 2289881 C1 Russian Federation, IPC Н03М 1/66 (2006.01). Appl. 19.07.2005; publ. 20.12.2006.), Containing information inputs, harmonic oscillator, controlled phase shifters, phase shifter at an angle π / 2 , attenuator, balanced phase detector, output. The disadvantage is low accuracy.

The closest to the claimed invention is an invention (US Pat. 2290754 Russian Federation, IPC Н03М 1/66 (2006.01). Appl. 11.07.2005; publ. 27.12.2006.), Containing information inputs, a harmonic oscillator, controlled phase shifters, phase shifter at an angle π / 2, attenuator, balanced phase detector, output. The disadvantage is low accuracy, determined by the approach to the formation of the resulting analog signal, giving within -P / 4 <A <P / 4 a deviation of up to 10% of the required value.

The technical problem to be solved by the claimed device consists in the implementation of another method of forming the output analog equivalent of the input digital value, presented in the system of residual classes.

The technical result is expressed in increasing the conversion accuracy.

управляемого фазовращателя на угол кратный π/2 соединен с вторым входом j+1-го управляемого фазовращателя на угол кратный π/2, при этом выход n+1-го управляемого фазовращателя на угол кратный π/2 соединен с первым входом первого аналогового перемножителя и через второй фазовращатель на угол π/2 с первым входом второго аналогового перемножителя, выход которого соединен с входом второго фильтра низких частот, выход которого соединен с третьим входом сумматора сигналов, при этом выход i-го

управляемого фазовращателя соединен с вторым входом i+1-го управляемого фазовращателя, при этом выход n-го управляемого фазовращателя соединен с вторыми входами первого и второго аналогового прермножителя, при этом выход первого аналогового перемножителя через первый фильтр низких частот соединен с вторым входом сумматора сигналов, при этом вход постоянного сигнала объединен с первым входом сумматора сигналов, выход которого соединен с выходом устройства.The technical result is achieved by the fact that the digital-to-analog converter in the system of residual classes, containing n information inputs of the device, where n is the number of bases of the residual class system, n controlled phase shifters, a harmonic oscillator, the first phase shifter at an angle l / 2, the output of the device, the input rank number, n + 1 controlled phase shifters at an angle multiple of π / 2, a second phase shifter at an angle of π / 2, first and second analog multipliers, first and second low-pass filters, a constant signal input, a signal adder, while the output of the harmonic oscillator is connected with the second input of the first controlled phase shifter and the input of the first phase shifter at an angle of π / 2, the output of which is connected to the second input of the first controlled phase shifter by an angle multiple of π / 2, while the information inputs of the device are connected to the first inputs of the corresponding controlled phase shifters at an angle multiple of π / 2 and the corresponding controlled phase shifters, at the input of the rank of a number is connected to the first input of the n + 1-th controlled phase shifter by an angle multiple of π / 2, while the output of the j-th

of the controlled phase shifter by an angle multiple of π / 2 is connected to the second input of the j + 1-st controlled phase shifter by an angle multiple of π / 2, while the output of the n + 1 controlled phase shifter by an angle multiple of π / 2 is connected to the first input of the first analog multiplier and through the second phase shifter at an angle π / 2 with the first input of the second analog multiplier, the output of which is connected to the input of the second low-pass filter, the output of which is connected to the third input of the signal adder, while the output of the i-th

controlled phase shifter is connected to the second input of the i + 1-th controlled phase shifter, while the output of the n-th controlled phase shifter is connected to the second inputs of the first and second analog multiplier, while the output of the first analog multiplier through the first low-pass filter is connected to the second input of the signal adder, while the input of the constant signal is combined with the first input of the signal adder, the output of which is connected to the output of the device.

FIG. 1 shows a block diagram of a digital-to-analog converter in the residual class system.

FIG. 2 shows two functional dependences for the values of the angle in the first coordinate quarter.

Table 1 shows the results of calculating the numbers T1 _j (γ _j ).

Table 2 shows the results of calculating the numbers T2 (r _A ).

Table 3 shows the results of calculating the numbers T3 _j (γ _j ).

The essence of the invention lies in the formation at the output of the analog equivalent of the input digital value according to the functional dependence (Fig. 2):

where ϕ is an angle ranging from 0 to π / 2, which gives a maximum deviation from the ideal linear characteristic of about 2.1%, and this is many times better than that of the prototype. The formation of ϕ is carried out through low-frequency filtering of the result of multiplying the tonal harmonics with the arguments α = ωt + ϕ _α and β = ωt + ϕ _β :

Accordingly, sin (ϕ) and -cos (ϕ), taking into account (2), can be obtained from the expressions:

в которой значения вычетов числа А=(γ₁, .. γ_n) подаются на входы реализуемого устройства. В качестве одного из способов выполнения (1) для угла ϕ в пределах от 0 до π/2 предлагается сместить значение А в первую четверть объема чисел за счет расширения диапазона в четыре раза

что достигается вводом дополнительного основания p_n+1=4. Таким образом, необходимо решить задачу о нахождении вычета γ_n+1, и дальнейшем преобразовании числа А=(γ₁, .. γ_n, γ_n+1) в фазу гармонического сигнала, пропорционально позиционному представлению. Поскольку А определенно располагается в первой четверти диапазона Р⁽²⁾, то вычет γ_n+1 может быть найден как остаток по модулю p_n+1 из позиционного представления, полученного на основе исходной СОК по основаниям p₁, .. p_n:Let us now consider the process of forming the argument ϕ through ϕ _α and ϕ _β . Let a residual class system (RNS) be given with odd coprime bases p ₁ , .. p _n and the range

in which the values of the residues of the number A = (γ ₁ , .. γ _n ) are fed to the inputs of the device being implemented. As one of the methods for fulfilling (1) for the angle ϕ in the range from 0 to π / 2, it is proposed to shift the value of A to the first quarter of the volume of numbers by expanding the range by four times

which is achieved by introducing an additional base p _{n + 1} = 4. Thus, it is necessary to solve the problem of finding the residue γ _{n + 1} , and further transforming the number A = (γ ₁ , .. γ _n , γ _{n + 1} ) into the phase of the harmonic signal, in proportion to the positional representation. Since A is definitely located in the first quarter of the range P ⁽²⁾ , then the residue γ _{n + 1} can be found as the remainder modulo p _{n + 1} from the positional representation obtained on the basis of the original RNS on the bases p ₁ , .. p _n :

- вес ортогонального базиса в исходной СОК, полученный из решения сравнения

r_A - ранг числа А в исходной СОК по основаниям p₁, .. p_n.Where

is the weight of the orthogonal basis in the original RNS obtained from the comparison solution

r _A - the rank of the number A in the original RNS by bases p ₁ , .. p _n .

The argument ϕ, taking into account the periodicity of the sine function, is determined by the expression:

- вес ортогонального базиса, полученный из решения сравнения

Перепишем (6) в согласии с (2) в виде ϕ_α и ϕ_β с учетом выражения (5) и того факта, что фазовращатели формируют отрицательный набег фазы:Where

is the weight of the orthogonal basis obtained from the comparison solution

Let us rewrite (6) in accordance with (2) in the form ϕ _α and ϕ _β taking into account expression (5) and the fact that the phase shifters form a negative phase incursion:

Let's rewrite (7), replacing, for clarity, parts of the expression calculated in a tabular way in the phase shifters themselves (RF patent No. 2253943, Fig. 2), by T1 _j (γ _j ), T2 (r _A ) and T3 _j (Y _j ):

Thus, the argument ϕ is realized and, on its basis, expression (1) is realized.

It should be noted that the branching of the microwave signal lines in FIG. 1 should be accompanied by a power divider and amplifiers to increase the amplitude of harmonics to unity, but these elements are omitted to simplify the circuit.

An additional effect is an increase in functionality, expressed in the use of the entire volume of P numbers of a given RNS, in contrast to the prototype, where only the range -P / 4 <A <P / 4 is stipulated.

Shown in FIG. 1 digital-to-analog converter in the system of residual classes contains information inputs of the device 1.1-1.n, an input of rank 2, the first and second phase shifters at an angle π / 2 3, a harmonic oscillator 4, controlled phase shifters at an angle multiple of π / 2 5.1-5. n + 1, controlled phase shifters 6.1-6.n, first and second analog multipliers 7, constant signal input 8, first and second low-pass filters 9, signal adder 10, device output 11.

соединен с вторым входом управляемого фазовращателя на угол кратный π/2 5.j+1, при этом выход управляемого фазовращателя на угол кратный π/2 5.n+1 соединен с первым входом первого аналогового перемножителя 7 и через второй фазовращатель на угол π/2 3 с первым входом второго аналогового перемножителя 7, выход которого соединен с входом второго фильтра низких частот 9, выход которого соединен с третьим входом сумматора сигналов 10, при этом выход управляемого фазовращателя 6.i

соединен с вторым входом управляемого фазовращателя 6.i+1, при этом выход управляемого фазовращателя 6.n соединен с вторыми входами первого и второго аналогового прермножителя 7, при этом выход первого аналогового перемножителя 7 через первый фильтр низких частот 9 соединен с вторым входом сумматора сигналов 10, при этом вход постоянного сигнала 8 объединен с первым входом сумматора сигналов 10, выход которого соединен с выходом устройства 11.The output of the harmonic oscillator 4 is connected to the second input of the first controlled phase shifter 6.1 and the input of the first phase shifter at an angle π / 2 3, the output of which is connected to the second input of the controlled phase shifter at an angle multiple of π / 2 5.1, while the information inputs of the device 1.1-1.n connected to the first inputs of the corresponding controlled phase shifters at an angle multiple of π / 2 5.1-5.n and the corresponding controlled phase shifters 6.1-6.n, while the input of the number rank is connected to the first input of the controlled phase shifter at an angle multiple of π / 2 5.n + 1 , while the output of the controlled phase shifter at an angle multiple of π / 2 5.j

connected to the second input of the controlled phase shifter at an angle multiple of π / 2 5.j + 1, while the output of the controlled phase shifter at an angle multiple of π / 2 5.n + 1 is connected to the first input of the first analog multiplier 7 and through the second phase shifter at an angle of π / 2 3 with the first input of the second analog multiplier 7, the output of which is connected to the input of the second low-pass filter 9, the output of which is connected to the third input of the signal adder 10, while the output of the controlled phase shifter 6.i

connected to the second input of the controlled phase shifter 6.i + 1, while the output of the controlled phase shifter 6.n is connected to the second inputs of the first and second analog multiplier 7, while the output of the first analog multiplier 7 through the first low-pass filter 9 is connected to the second input of the signal adder 10, while the input of the constant signal 8 is combined with the first input of the signal adder 10, the output of which is connected to the output of the device 11.

и

то согласно (7) и (8) можно рассчитать табличные числа T1_j(γ_j), Т₂(r_A) и T3_j(γ_j) в зависимости от известных вычетов и ранга. Управляемые фазовращатели 5 и 6 осуществляют формирование суммарного набега фазы гармонического сигнала от генератора 4 (фиг. 1), что аналогично вычислению ϕ_α и ϕ_β (8). Далее на блоках 7 происходит перемножение сигналов так, что на первый из них гармоника приходит с дополнительной задержкой -π/2, а на второй -π, после чего осуществляется низкочастотная фильтрация на 9 (выражения (3) и (4)).The device operates as follows. Let a system of residual classes (RNS) be given with odd coprime bases p ₁ , .. p _n , in which the values of the residues of the number A = (γ ₁ , .. γ _n ) are fed to the inputs of the device 1.1-1.n, and to the input 2 - the value of the rank of the number A: r _A. Since for the original and extended RNS, the values

and

then according to (7) and (8) it is possible to calculate the tabular numbers T1 _j (γ _j ), T ₂ (r _A ) and T3 _j (γ _j ) depending on the known residues and rank. Controlled phase shifters 5 and 6 perform the formation of the total phase incursion of the harmonic signal from the generator 4 (Fig. 1), which is similar to the calculation of ϕ _α and ϕ _β (8). Further, on blocks 7, the signals are multiplied so that the harmonic arrives at the first of them with an additional delay -π / 2, and at the second -π, after which low-frequency filtering is carried out by 9 (expressions (3) and (4)).

Then, after low-frequency filtering on blocks 9 and addition by 10 s with a constant signal value (current or voltage) from input 8, the size of a half of the amplitude of the harmonics applied to the multipliers 7, expressions (1) are realized.

Example.

то согласно (7) и (8) можно рассчитать табличные числа T1_j(γ_j), Т2(r_A) и T3_j(γ_j) (табл. 1-3) в зависимости от вычетов и ранга: T1₁(1)=2, T1₂(2)=2, T1₃(2)=2, T2(1)=1, T3_j(1)=2, Т3₂(2)=3, Т3₃(2)=4. Управляемые фазовращатели 5 и 6 осуществляют формирование суммарного набега фазы гармонического сигнала от генератора 4 (фиг. 1), что математически соответствует вычислению ϕ_α и ϕ_β из выражения (8):Let a system of residual classes (RNS) be given for three (n = 3) odd coprime bases 3, 5 and 7, in which the values of the residues of the number A, for example 37 = (1,2,2), are fed to the device inputs 1.1-1.3 , and at input 2 - the value of the rank of the number A: r _A = 1. Since for the original and extended RNS, the values

then according to (7) and (8) it is possible to calculate the tabular numbers T1 _j (γ _j ), T2 (r _A ) and T3 _j (γ _j ) (Tables 1-3) depending on the deductions and rank: T1 ₁ (1 ) = 2, T1 ₂ (2) = 2, T1 ₃ (2) = 2, T2 (1) = 1, T3 _j (1) = 2, T3 ₂ (2) = 3, T3 ₃ (2) = 4 ... Controlled phase shifters 5 and 6 carry out the formation of the total phase incursion of the harmonic signal from the generator 4 (Fig. 1), which mathematically corresponds to the calculation of ϕ _α and ϕ _β from expression (8):

Further, on blocks 7, the signals are multiplied so that the harmonic arrives at the first of them with an additional delay -π / 2, and at the second -π, and low-frequency filtering by 9, which makes it possible to implement expressions (3) and (4):

Then, as a result of addition by 10 s of a signal (current or voltage) constant from input 8, the size of a half of the amplitude of the 7 harmonics applied to the multipliers, the expression (1) is realized:

f (ϕ) = [1 + 0.52568-0.85068] /2 = 0.3375.

To assess the conversion accuracy, compare the result with the ideal value obtained as the division of the number A = 37 by the volume of RNS P ⁽¹⁾ = 105: 37/105 = 0.3524. The discrepancy is 1.5%, which fits the stated accuracy.

The resulting device reflects the principles of building a DAC based on the properties of the residual class system. From the point of view of practical application, the converter realizes the possibility of outputting information in analog form from digital modular computational structures with the maximum possible speed.

Claims (1)

A digital-to-analog converter in the system of residual classes, containing n information inputs of the device, where n is the number of bases of the system of residual classes, n controlled phase shifters, a harmonic oscillator, the first phase shifter at an angle π / 2, the output of the device, characterized in that the input of the number rank is introduced, n + 1 controllable phase shifters at an angle multiple of π / 2, a second phase shifter at an angle of π / 2, the first and second analog multipliers, the first and second low-pass filters, a constant signal input, a signal adder, while the output of the harmonic oscillator is connected to the second input the first controlled phase shifter and the input of the first phase shifter at an angle of π / 2, the output of which is connected to the second input of the first controlled phase shifter at an angle multiple of π / 2, while the information inputs of the device are connected to the first inputs of the corresponding controlled phase shifters at an angle multiple of π / 2 and the corresponding controlled phase shifters, while the input of the rank of the number with connected to the first input of the n + 1-th controlled phase shifter by an angle multiple of π / 2, while the output of the j-th

of the controlled phase shifter by an angle multiple of π / 2 is connected to the second input of the j + 1-st controlled phase shifter by an angle multiple of π / 2, while the output of the n + 1 controlled phase shifter by an angle multiple of π / 2 is connected to the first input of the first analog multiplier and through the second phase shifter at an angle π / 2 with the first input of the second analog multiplier, the output of which is connected to the input of the second low-pass filter, the output of which is connected to the third input of the signal adder, while the output of the i-th

controlled phase shifter is connected to the second input of the i + 1-th controlled phase shifter, while the output of the n-th controlled phase shifter is connected to the second inputs of the first and second analog multiplier, while the output of the first analog multiplier through the first low-pass filter is connected to the second input of the signal adder, while the input of the constant signal is combined with the first input of the signal adder, the output of which is connected to the output of the device.

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