SU1316091A1 - Device for encoding analog signals - Google Patents

Abstract

This invention relates to automation. The use of discrete transmissions in systems, for example, audio signals, makes it possible to improve coding accuracy. The device contains a subtractor 1, an analog-to-digital converter (AC) 2, an adder 3, a digital-to-analog converter (D / A converter) 4, a predictor 5 and a decimator 9. Introduction of switches 6 and 7, an attenuator 8 and a control unit 10 provides reduction of the noise introduced. CPU 2 and LLAn 4, and the specific execution of the predictor 5 allows to increase the sampling rate more than sixteen times, which is also; l: shata coding accuracy. 2 hp f-ly, 4 silt, 1 tab. sl so about: about with

Description

I13

The invention relates to automation and can be used in discrete transmission systems, such as audio signals.

The purpose of the invention is to improve coding accuracy.

FIG. I shows a block diagram of a coding device; Figures 2 and 3 are block diagrams of a predictor of a control unit, respectively; in fig. 4 - BP; charts of the device.

The device for encoding an analog signal contains a subtractor 1, an analog-to-digital converter 2 (ADP), an adder 3, a digital-to-analog converter D (D / A converter), a predictor 5, first and second switches 6 and 7, an attenuator 8, a decimator 9, and a control unit 10 . In FIG. 1, informational input 11, synchronization input 12 and outputs 13 are designated.

Predictor 5 is made (Fig. 2) from the first to the fourth registers 14-17, the first and second adders 18 and 19, the first and second switches 20 and 21. FIG. 2, information inputs 22, control input 23, first and second synchronization inputs 24 and 25, outputs 26 are designated.

Attenuator 8 is a precision controlled voltage divider.

Decimator 9 is a serial connection of a digital low-pass filter, made in the form of a non-recursive filter with a finite impulse response, and a sampling frequency compressor (for example, a register) whose sync inputs are combined and are the synchronization input of the decimator.

The control unit 10 is executed (FIG. 3) on the decoder; 27, register 28, generator 29, pulse distributor 30, first, second and third triggers 31-33, first, second and third driver 34-36 pulses. FIG. 3 are designated information inputs 37, synchronization input 38 from the first to the eighth outputs 39-46. The first pulse shaper 34 is used to generate control signals for switches b and 7 and is a signal level converter. The second pulse shaper 35 provides for the differentiation of the negative front of the incoming pulse. Tre6091

The pulse former 36 serves to output synchronization pulses to blocks 2-5 and can be made as a block of keys. The decoder 27 implements the following truth table:

Pulse distributor 30 includes a counter and a decoder.

FIG. 4 denotes: a) a pulse of external synchronization at the input 12;

b) the pulse at the output of the trigger 32 of the control unit 10; c) a pulse at the output of the trigger 31 of the control unit 10; d) pulses at the output of the generator 29 of the control unit 10; e) impulses on

the outputs 42-45 of the control unit 10 (at the clock inputs of the ATP 2, the adder 3, and the inputs 24 and 25 of the predictor 5, respectively); i) the output signal t of the tigger 33 (input 23

predictor 5); k) a pulse at the time of synchronization of register 28 of control unit 10; l) pulse at output 6 of control unit 10. (at the synchronization input of the D / A converter 4); m), n) impulse (; s with I. U onKn trster 32 n 31 block 1 D) of control.

The RLBOG device for encoding analog signals is based on the well-known encoding method with a prediction when not the input signal itself is quantized, but the difference between it and its predicted value. The code of the input signal is obtained as a result of the addition of the code of the predicted value and the code of this difference - the prediction error. Prediction will be effective if the encoding is performed at a frequency that exceeds the Kotelnikov sampling rate, when successive signal samples become correlated. In the device implementation example, the sampling frequency is 768 kHz, thu is sixteen times higher than the frequency of 48 kHz received in broadcasting.

The device works in the following way.

The analog audio signal is fed from input 11 to subtractor 1, where it is amplified in such a way that the full quantization scale is used and at the same time the clipping of the signal is low. At the other input of the calculator 1, the value of the predicted signal arrives, therefore, at the output of the subtractor 1, a prediction error signal is generated, equal to the difference between the input and predicted signals. The error signal gain factor in the subtractor 1 is determined by the control signal from the control unit 1. From the output of the subtractor 1, the prediction optic signal arrives at the signal input of the A / D converter 2, the synchronization pulse of which is generated, with the control unit 10. With the arrival of a positive front at the synchronization input 12, the first and second triggers 31 and 32 of the control unit 10 are set to the zero state, since their B-inputs have a logical O level. The logic level 1 from the inverse output of the trigger 32 transfers the counter to the distributor 30 pulses into the direct counting mode, and the logic level O from the output of the trigger 31 starts the generator 29, which begins to generate rectangular clock pulses in the form of a meander with a period of “60 ns, the positive front of the first clock pulse g generators of 29, generates at the output 42 of the control unit 10 by

5 about - g

five

0

five

Rinat ejii.Hbii i synchronization pulse LII 2 in the first tacton interval. At the outputs of ADC 2, a code appears corresponding to the value of the analog signal error. This code, represented as the sign of the error signal (the high bit of the ADC 2) and the error value code (from the sixth to the first bit), goes to the information inputs of the first switch 6. Depending on the control signal, the first switch 6 connects the prediction error code to the wire. the youngest bits will give the peppy info1 ion inputs of the adder 3, or it will shift them to the left by one, two, three bits. To the second information inputs of the adder 3, the predicted value of the input signal is supplied from the outputs of the predictor 5. Thus, at the outputs of the adder 3, the code of the true value of the input signal is calculated, which is stored in the adder 3 by the synchronization pulse from the output 43 of the block 10, which is formed with the arrival of the third clock pulse from the generator 29. This code in the adder 3 remains unchanged until the arrival next sync pulse. It should be noted that the positive edge of the synchronization pulse of the adder 3 is delayed relative to the positive front of the ADC sync pulse 2 on the NS, which provides the time required for the ADC 2, PG 20 NS, triggering two codes in the adder 3 60 NS to trigger and pass the code through the first switch 6 3 not, i.e. guarantees the correctness of the code at the output of the adder 3. The code from the output of the adder 3 is fed to the decimator 9 and the predictor 5. The first and second synchronization pulses of the predictor 5 are formed in control block 10 at outputs 44 and 45 during the fourth and fifth clock pulses, similar to the synchronization pulses of the adder 3. The control signal of the predictor 5 is generated by the third trigger 33 of the control unit 10 (output 41). The switches 20 and 21 of the predictor 5 are closed in such a way that when the logic inputs O are fed to their control inputs, the outputs of the -1-switches 20 and 21 are connected to the second inputs, and when the logic 1 is fed to the first. Predictor 5 works according to the following expression

Y (pT) X (p-1), - L ,,

V (nT) - IG.1 by signal (code) in

time point PT; , 2,. . . ,

T is the sampling period; X (pT) - input signal (code);

4, CG (p -)) (p-2) j-X (n-2) (n-3) T,

The code from the outputs of the adder 3 is fed to the reg ister 1A and the adder 18, where it is added to the inverse of the value of the previous counting code, i.e. The value of / a is determined, and to the switch 21. Since the outputs of this switch 21 are connected to its second inputs (at its control input is a logical O level), the code from the outputs of adder 3 goes to the second inputs of adder 19, on the front inputs of which at this moment there is a value supplied from the inverse outputs of register 15 via switch 20. Therefore, with the arrival of the first synchronization pulse of the predictor 5, the sum xC (n-1) is written to register 16, and the register 15 from the outputs of adder 18 is equal to 3, Xt (nl) (n-2) T. Simultaneously with the arrival of the first sync pulse, the control inputs of the switches 20 and 21 are fed to the control inputs of input 23 and they connect the first inputs to their outputs. Moreover, the first inputs of the switch 20 are connected to the forward outputs of the register 15 in such a way that the code from the output of the register 15 is shifted by one bit to the left, i.e. it is reduced by two. Thus, the first inputs of the adder 19 receives the code 2D, and its second inputs - the code of the partial sum X (nl) TJ- and, from register 16. With the arrival of the second synchronization pulse of the predictor 5, the code from the output of adder 19, equal to the predicted value of the subsequent the input signal Y (nT) X (p-1) T + 2 4 -4j, write to register 17. At the same time, the second synchronization pulse code from the outputs of the adder 3 is written into the predictor 5 register 1A, as it is necessary for the predictor 5 to work The next sampling period. In addition, the difference code is 4 ,. recorded in register 15 will also be used in the next sampling period as, since it is removed from the inverse outputs of register 15.

1L

After writing the code and the register I7 of the predictor 5, it enters the second switch 7 and the control unit 10. According to the table

In truth, the decoder 27 of the control unit 10 generates a positional control code, which is fed to the input of the register 28. On the positive edge of the synchronization pulse, which is tried by the driver 36, during the second half of the fifth clock interval, i.e. on the negative front of the fifth clock pulse (see fig. 4k), the control code is written

register 28. Next, this code immediately comes from the outputs 39 of block 10 to the control inputs of the first switch 6 and the second switch 7. The second switch 7 connects to the inputs

D / A converters 4 eleven consecutive bits of the predictor 5 output code, either from 15 to 5, or from 14 to 4, or from 13 to 3, or from 12 to 2, i.e. so as to maximize the use of the dynamic range of the DAC 4. To the first (most senior) bit of the D / A converter 4, regardless of the control code, the highest bit of the code from the output is supplied. predictor 5 since he is

sign. The first switch 6 also switches the outputs of the A / D converter 2 to the corresponding inputs of the adder 3. At the same time, the control code from the outputs of the register 28 goes to the driver 34, which generates the control signals necessary for the operation of the attenuator 8 and the subtractor 1. On the positive edge of the sixth clock pulse of the generator 29 (see Fig. 4) the driver 36 generates a DAC 4 synchronization pulse, according to which the code from the corresponding outputs of the switch 7 is written to it. Simultaneously from the second output of the distributor 30 pulses there is a denial Yelnia pulse is supplied to the adjusting input of the second flip-flop 32. As a result, the output of flip-flop 32 is set to logic-zero level,

which puts the counter in the distributor 30 in parallel recording mode. The code from the outputs of the switch 7 is converted into a DAC 4 into the corresponding voltage J inverted relative to the input code of the DAC 4 and, consequently, the input signal of the device. Output Voltage DAC 4. is supplied to the attenuator 8. At the output of the attenuator 8, the voltage is removed

  3

such a cht (1by restore the amplitude 11redski niog (1 value input signal, distorted as a result of switching the signal at the input of the DAC A. i. oo6xo) that not only the signal itself decreases at the output of the attenuator 8, but also the error introduced by inaccurate levels CLP A. The signal from the output of the attenuator 8 is fed to the second input of the subtractor 1, in which the prediction error signal is generated. With the arrival of the seventh clock pulse from the generator 29 of the control unit 10, the imaging unit 35 produces a short positive pulse, which ivaet on the output of the first flip-flop 31 logic one level, and stops the generator 29. With the arrival of the next clock pulse in the control unit 0 only work povtorits device as described vshe.

From the outputs of the adder 3, the sampling codes of the input signal with a frequency of 768 kHz are fed to the information input of the decimator 9, and the external synchronization signal with a frequency of 768 kHz is received at its synchronization input. The digital filter included in the decimator 9 suppresses the frequency components lying out of band a useful audio signal (similar to an analog low-pass filter with a passband of 0–20 kHz), and the sampling rate compressor lowers the sampling rate to a standard 48 kHz, skipping to the outputs of the decimator 9 only to Each sixteenth code from the output of the digital filter. Thus, at the outputs of the decimator 9, sample codes of the input analog audio signal with a frequency of 48 kHz are formed, corresponding to a sixteen-bit linear coding.

The device for coding analog signals, due to the additional processing of the predicted value of the input signal using the second switch 7 and attenuator 8, controlled by the control unit 10, allows to reduce the noise introduced by the DAC 4 by more than 10-14 dB, A The additional processing of the prediction error signal by the compiler 1 and the first switch 6 makes it possible to preserve the condition of insignificant noise introduced by the ADC 2. In addition, the use of loop about 6091

Interconnection of the Prdsk Cha- nal 3, Pypol- HfMiHci o in accordance with the original scheme, gives you the possibility of an increase. more than discrete -IRM n 16 rp: comparing with iine) with the received; and) coded sound signals, which could be used to increase the accuracy of coding pas 12 dB.

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Claims (1)

Invention Formula -one. A device for coding analog signals to signals containing a subtractor, the output of which is connected to the information input of the analog-digital converter, a digital-analogue converter, an adder, whose outputs are connected to the corresponding The 0 information inputs of the decimator and the predictor, the outputs of which are connected to the corresponding first inputs of the accumulator, the first information input of the subtractor is the informative input of the device, the outputs of the decimator are outputs of the device, characterized in that, for the purpose of coding accuracy, the device is entered 30 switches, attenuator and control unit 1; , the first outputs of which are connected to the corresponding control inputs of the first and second switches, the outputs of which are connected respectively to the second inputs of the adder and information inputs of the digital-analog converter, the output of which is connected to the information input of the attenuator, the second outputs of the control unit are connected to the manager inputs of the subtractor and attenuator, the output of which is connected to the second information input of the subtractor, outputs of the analog-digital converter 45 are connected to the information inputs of the first switch; the corresponding information inputs of the second switch and the control unit are combined and connected to the corresponding outputs of the predictor; the third, fourth and fifth outputs of the control unit are connected respectively to the control input and the first and second predictor synchronization inputs, the sixth,  the seventh and eighth outputs of the control unit are connected to the synchronization inputs of the digital-analog and analog-digital converter and the adder, respectively; clock inputs; ..i lgipa op;) n block yiipajs ichnn unite and nl jgs with input siikhro (ngii device. 2, The device according to claim 1, of which is Dj e so that, with a view to T1v1n1c neither speed, the predictor is made on registers, adders and KOMMif TflTOpax, the outputs of the first register are connected to the corresponding nepBi.iH input; lm of the first adder, the outputs of which are connected to corresponding information inputs of the second register, the first and second outputs of which are connected to the corresponding information inputs of the first switch, the outputs of the first and second switches are connected to the corresponding inputs of the second adder, whose outputs The dinene with the corresponding information inputs of the third and fourth registers, the outputs of the third register are connected to the first information inputs of the second switch, the second information inputs of which are combined with the corresponding second inputs of the first adder and information inputs of the first register and are the information inputs of the predictor, the control inputs of the switches are combined and are the predictor control input, the synchronization inputs of the second and third registers, and the synchronization inputs of The first and fourth registers are respectively combined and are the first and second sync inputs / g and the predictor. The outputs of the fourth register are the predictor outputs. Qt1 (1 . 1 Royce mu pp. I, that is, with the control unit on the register, generator, pulse distributor, formulated pulse, trigger and decoder, the output 1 1 of which is connected to the information inputs of the register The outputs of which are connected to the corresponding inputs of the first pulse generator, the outputs of the first and second triggers are connected respectively to the input of the generator and the controller of the pulse distributor, the first and second outputs of which are respectively via the second pulse shaper and are only connected to the installation inputs of the first and second triggers, the output of the 1-generator is connected to the inputs synchronization of the third pulse generator and pulse distributor, the third outputs of which are connected to the corresponding installation inputs of the third trigger and the corresponding the control inputs of the third pulse generator, the first output of which is connected to the register synchronization input, the inputs of the decoder are the information inputs of the block, the inputs the synchronizations of the first and second triggers are combined and are the sync input of the block, the outputs of the register and the first pulse shaper in each, the first and second outputs of the block, the output of the third trigger and the second to sixth, the outputs of the third pulse shaper are the third to eighth outputs of the block. F1 / g.