SU1132805A3 - Digital-to-analog converter - Google Patents

Digital-to-analog converter Download PDF

Info

Publication number
SU1132805A3
SU1132805A3 SU762309106A SU2309106A SU1132805A3 SU 1132805 A3 SU1132805 A3 SU 1132805A3 SU 762309106 A SU762309106 A SU 762309106A SU 2309106 A SU2309106 A SU 2309106A SU 1132805 A3 SU1132805 A3 SU 1132805A3
Authority
SU
USSR - Soviet Union
Prior art keywords
output
input
interpolator
filter
significant bits
Prior art date
Application number
SU762309106A
Other languages
Russian (ru)
Inventor
Джон Джинджелл Майкл
Original Assignee
Интернэшнл Стандарт Электрик Корпорейшн (Инопредприятие)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Интернэшнл Стандарт Электрик Корпорейшн (Инопредприятие) filed Critical Интернэшнл Стандарт Электрик Корпорейшн (Инопредприятие)
Application granted granted Critical
Publication of SU1132805A3 publication Critical patent/SU1132805A3/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/68Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using pulse rate multipliers or dividers pulse rate multipliers or dividers per se
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00Conversion of analogue values to or from differential modulation
    • H03M3/30Delta-sigma modulation
    • H03M3/50Digital/analogue converters using delta-sigma modulation as an intermediate step
    • H03M3/502Details of the final digital/analogue conversion following the digital delta-sigma modulation
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/3002Conversion to or from differential modulation
    • H03M7/3004Digital delta-sigma modulation
    • H03M7/3015Structural details of digital delta-sigma modulators
    • H03M7/3031Structural details of digital delta-sigma modulators characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path
    • H03M7/3042Structural details of digital delta-sigma modulators characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path the modulator being of the error feedback type, i.e. having loop filter stages in the feedback path only
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/3002Conversion to or from differential modulation
    • H03M7/3004Digital delta-sigma modulation
    • H03M7/3015Structural details of digital delta-sigma modulators
    • H03M7/302Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M7/3024Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
    • H03M7/3026Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a multiple bit one

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Computational Mathematics (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
  • Networks Using Active Elements (AREA)
  • Oscillators With Electromechanical Resonators (AREA)

Abstract

1444216 Digital - to - analogue conversion STANDARD TELEPHONES & CABLES Ltd 20 Feb 1975 7157/75 Heading H3H An analogue output is derived from a P.C.M. signal by increasing its sampling rate in interpolator 1, converting only the most significant bits to a pulse density signal in a rate-multiplier 3, and low-pass filtering 4 to give the analogue output. Noise is reduced by feeding back the least significant bits through a filter 12. The filter may comprise one or more delays whose outputs are combined with different weighting factors: several examples are described, Figs. 4, 8, 10, 11, not shown. The interpolator may be simply a recirculating register, Fig. 6, not shown, for merely repeating each P.C.M. word, e.g. 32 times or may be a linear interpolator, Fig. 7, not shown. D-to-A converter 3 comprises a synchronous binary counter 5, Fig. 2, fed with fast clock pulses fc, binarily weighted frequencies being obtained at its outputs A, B, C, D which are gated by the 4 most significant bits of the interpolated P.C.M. signal to produce a pulse train E of mean density corresponding to these 4 bits.

Description

Изобретение относится к области ] импульсной техники и может быть применено в системах связи с кодовоимпульсной модуляцией.The invention relates to the field of] pulse technology and can be used in communication systems with code-pulse modulation.

Известен цифроаналоговый преобра-зователь, содержащий прецизионные резисторы, источник опорного напряжения^ ключи и операционный усилитель[1]Known digital-to-analog Converter containing precision resistors, a reference voltage source ^ keys and an operational amplifier [1]

Данный преобразователь сложен в изготовлении; так как для достижения высокой точности требуется индивидуальная подгонка прецизионных резисторов.This converter is difficult to manufacture; since to achieve high accuracy, individual adjustment of precision resistors is required.

Известен также цифро-аналоговый преобразователь, содержащий умножитель частоты, выход которого соединен с входом фильтра низких частот, выход которого соединен с выходной шиной [2] .Also known digital-to-analog Converter containing a frequency multiplier, the output of which is connected to the input of the low-pass filter, the output of which is connected to the output bus [2].

Недостатком данного преобразователя является ограниченная точность, обусловленная погрешностями аналоговых элементов (прецизионных резисторов и ключей), используемых в устройстве. ;The disadvantage of this converter is the limited accuracy due to the errors of the analog elements (precision resistors and keys) used in the device. ;

Цель изобретения - повышение точности преобразования.The purpose of the invention is improving the accuracy of the conversion.

Подставленная цель достигается тем, что в цифроаналоговый; преобразователь, содержащий умножитель час~зо тоты, выход которого соединен с входом фильтра низких частот,' выход которого соединен с выходной шиной, введены блок селекции, сумматор, компаратор, фильтр сигнала ошибки и интерполятор, выход которого подключен к первому входу сумматора, выход которого соединен с входом блока селекции и первым входом компаратора, второй вход которого подключен к выходу блока селекции и входу умножителя частоты, а выход через фильтр сигнала ошибки к второму входу сумматора.The set goal is achieved by the fact that in digital-analog; a converter containing a frequency multiplier whose output is connected to the input of a low-pass filter, the output of which is connected to the output bus, a selection block, an adder, a comparator, an error signal filter, and an interpolator are introduced, the output of which is connected to the first input of the adder, the output of which connected to the input of the selection block and the first input of the comparator, the second input of which is connected to the output of the selection block and the input of the frequency multiplier, and the output through the error signal filter to the second input of the adder.

На чертеже представлена структурная схема устройства.The drawing shows a structural diagram of a device.

Преобразователь содержит последовательно соединенные интерполятор 1, сумматор 2, блок 3 селекции, умножитель 4 частоты, фильтр 5 низкихThe converter contains a series-connected interpolator 1, adder 2, block 3 selection, frequency multiplier 4, filter 5 low

Claims (1)

ЦИФРОАНАЛОГОВЫЙ ПРЕОБРАЗОВАТЕЛЬ, содержаний умножитель частоты, выход которого соединен с входом · фильтра низких частот, выход которого соединен с выходной шиной , о т личающийся тем, что, с целью повышения точности преобразова- . ния, в него введены блок селекции, сумматор, компаратор, фильтр сигнала ошибки и интерполятор, выход которого подключен к первому входу сумматора, выход которого соединен с входом блока селекции и первым входом компаратора, второй вход которого подключен к выходу блока селекции и входу ^умножителя частоты, а выход - через фильтр сигнала ошибки к второму .входу сумматора.DIGITAL ANALOG CONVERTER, contains a frequency multiplier whose output is connected to the input of a low-pass filter, the output of which is connected to the output bus, which is characterized by the fact that, in order to increase the accuracy of the conversion. In this case, a selection block, an adder, a comparator, an error signal filter, and an interpolator are inserted into it, the output of which is connected to the first input of the adder, the output of which is connected to the input of the selection block and the first input of the comparator, the second input of which is connected to the output of the selection block and the input of the multiplier frequency, and the output is through the filter of the error signal to the second input of the adder. «. SU ш, 1132805 >". SU w, 1132805> 1 11328051 1132805
SU762309106A 1975-02-20 1976-01-08 Digital-to-analog converter SU1132805A3 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB715775A GB1444216A (en) 1975-02-20 1975-02-20 D/a converter for pcm

Publications (1)

Publication Number Publication Date
SU1132805A3 true SU1132805A3 (en) 1984-12-30

Family

ID=9827708

Family Applications (1)

Application Number Title Priority Date Filing Date
SU762309106A SU1132805A3 (en) 1975-02-20 1976-01-08 Digital-to-analog converter

Country Status (19)

Country Link
JP (1) JPS51135354A (en)
AR (1) AR212019A1 (en)
AT (1) AT377397B (en)
AU (1) AU497002B2 (en)
BE (1) BE838666A (en)
BR (1) BR7601013A (en)
CA (1) CA1093697A (en)
CH (1) CH607456A5 (en)
DE (1) DE2605724C2 (en)
DK (1) DK148866C (en)
ES (1) ES445387A1 (en)
FR (1) FR2301971A1 (en)
GB (1) GB1444216A (en)
IN (1) IN143625B (en)
IT (1) IT1054867B (en)
NL (1) NL7601414A (en)
NO (1) NO143776C (en)
SE (1) SE410929B (en)
SU (1) SU1132805A3 (en)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5228205A (en) * 1975-08-28 1977-03-03 Sony Corp Station selector unit
GB1580447A (en) * 1976-12-01 1980-12-03 Post Office Code converters
NL7801909A (en) * 1978-02-21 1979-08-23 Philips Nv DEVICE FOR DECODING A SIGNAL CODED WITH ADAPTIVE DELTA MODULATION.
DE3021012C2 (en) * 1980-06-03 1985-08-22 ANT Nachrichtentechnik GmbH, 7150 Backnang Generalized interpolative method for the digital-analog conversion of PCM signals
US4313173A (en) * 1980-06-10 1982-01-26 Bell Telephone Laboratories, Incorporated Linear interpolator
GB2107949B (en) * 1981-10-15 1985-04-11 Standard Telephones Cables Ltd Digital decoder
DE3203012A1 (en) * 1982-01-29 1983-08-04 Siemens AG, 1000 Berlin und 8000 München Method and circuit arrangement for generating interpolation values between stored samples
US4786923A (en) * 1982-09-07 1988-11-22 Canon Kabushiki Kaisha Image recording system for image recording in response to signals entered from a recording information generating unit
USRE34660E (en) * 1983-07-29 1994-07-12 Burr-Brown Corporation Apparatus and methods for digital-to-analog conversion using modified LSB switching
EP0437301A3 (en) * 1983-07-29 1991-09-25 Burr-Brown Corporation Apparatus and methods for digital-to-analogue conversion
JPS60106229A (en) * 1983-11-14 1985-06-11 Rohm Co Ltd D/a converting circuit of digital pwm circuit
DE3535021A1 (en) * 1984-10-02 1986-04-17 Canon K.K., Tokio/Tokyo DIGITAL / ANALOG CONVERSION DEVICE
JPS6184118A (en) * 1984-10-02 1986-04-28 Canon Inc Digital-analog converter
JPS6184120A (en) * 1984-10-02 1986-04-28 Canon Inc Digital-analog converter
JPS6184119A (en) * 1984-10-02 1986-04-28 Canon Inc Digital-analog converter
JPH0824267B2 (en) * 1984-10-02 1996-03-06 キヤノン株式会社 Data processing device
JPS6184117A (en) * 1984-10-02 1986-04-28 Canon Inc Digital-analog converter
GB2183115A (en) * 1985-11-15 1987-05-28 Philips Electronic Associated Digital to analogue converter
DE3709207A1 (en) * 1987-02-28 1988-09-08 Standard Elektrik Lorenz Ag CIRCUIT ARRANGEMENT FOR CONVERTING DIGITAL TONE SIGNAL VALUES TO ANALOG TONE
GB9103777D0 (en) 1991-02-22 1991-04-10 B & W Loudspeakers Analogue and digital convertors
GB2319411B (en) * 1996-11-18 2000-11-15 Fujitsu Ltd Modem signal transmission and/or reception apparatus

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3110894A (en) * 1959-04-09 1963-11-12 Itt Digital-to-analog converter
US3532864A (en) * 1967-08-08 1970-10-06 United Aircraft Corp Linear interpolation function generation

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
1. Патент US 3810157, кл. 340-347 ОА, Н 03 К 13/02,07.05.74. 2. Electronic Deeigh, 1968, I том. 16, W 22, с. 75, рис. 27 (про тот п). *

Also Published As

Publication number Publication date
CH607456A5 (en) 1978-12-29
SE410929B (en) 1979-11-12
AT377397B (en) 1985-03-11
DE2605724A1 (en) 1976-09-02
NO143776C (en) 1981-04-08
IT1054867B (en) 1981-11-30
ATA121476A (en) 1984-07-15
ES445387A1 (en) 1977-06-16
NO143776B (en) 1980-12-29
BE838666A (en) 1976-08-18
AU1110076A (en) 1977-08-18
AU497002B2 (en) 1978-11-16
SE7601666L (en) 1976-08-23
FR2301971A1 (en) 1976-09-17
FR2301971B1 (en) 1982-07-23
GB1444216A (en) 1976-07-28
DK148866B (en) 1985-10-28
DK148866C (en) 1986-04-21
DK64976A (en) 1976-08-21
BR7601013A (en) 1976-09-14
AR212019A1 (en) 1978-04-28
DE2605724C2 (en) 1986-01-23
JPS51135354A (en) 1976-11-24
NL7601414A (en) 1976-08-24
CA1093697A (en) 1981-01-13
JPS5542774B2 (en) 1980-11-01
IN143625B (en) 1978-01-07
NO760428L (en) 1976-08-23

Similar Documents

Publication Publication Date Title
SU1132805A3 (en) Digital-to-analog converter
US4509037A (en) Enhanced delta modulation encoder
US4890106A (en) Apparatus and methods for digital-to-analog conversion using modified LSB switching
US4345241A (en) Analog-to-digital conversion method and apparatus
EP0152922A3 (en) Method and system for processing digital video signal incorporating phase-correction feature
US4542371A (en) Method of converting a digital signal into an analog signal and a converter therefor
US4929947A (en) Constant width pulse distribution in a digital to analog converter for serial digital data
US4144577A (en) Integrated quantized signal smoothing processor
JP3326619B2 (en) PWM circuit
RU2771066C1 (en) Multi-channel analog-to-digital converter
USRE34660E (en) Apparatus and methods for digital-to-analog conversion using modified LSB switching
GB1463806A (en) Radar systems including digital processing arrangements
SU1005321A2 (en) Device for measuring noise level in speech pauses
SU1356184A1 (en) Balanced modulator
JP3230227B2 (en) A / D converter
SU1555806A1 (en) Shaper of recurrent frequency-modulated signals
SU1130881A1 (en) Device for reproducing periodic signals
SU1309055A1 (en) Device for simulating short-circuit signal
SU1109859A1 (en) Two-channel harmonic oscillator
SU599335A1 (en) Digital double-phase sine-shaped signal generator
SU1672570A1 (en) Delta-sigma encoder
SU1667038A1 (en) Special signal generator
SU1142848A1 (en) Interpolator
SU1316091A1 (en) Device for encoding analog signals
SU1417189A1 (en) Follow-up a-d converter