SU896632A1 - Digital extrapolator - Google Patents

Description

(54) DIGITAL EXTRAPULATOR

one

The invention relates to computing and can be used in digital automatic control systems.

A first-order extrapolator is known that fills the time intervals between code sends as a function of time varying linearly, spydr registers of memory, adders and counters 1.

The disadvantage of such a device is the low accuracy of the construction.

Closest to the present invention is a digital extrapolator comprising a memory register, a parallel adder, a code-frequency converter, a reversible counter, and an AND 2 element.

A disadvantage of the known digital extrapolator is that the information on the penultimate step of extrapolation is not taken into account, therefore the accuracy of extrapolation is low.

The purpose of the invention is to increase the accuracy of extrapolation.

The goal is achieved by the fact that a digital register containing the first register, the first element I, the first parallel adder, a code-frequency converter and a reversible counter, the input of the first register and the input of the current value of the reversing counter, is connected to the information input of the first register the register is connected to the first input of the element I. The second input of which is connected to the clock input of the extrapolator, the first and second outputs of the first parallel adder are connected to the subtractive and summarize To the 10 inputs of the reversible counter, the third output of the first parallel adder is connected to the code-frequency converter input, the output of which is connected to the counting input of the reversible counter, the output of which is the output of the scraper, the two parallel adders, the second register and the second element I, are entered the first input of the second parallel adder is connected to the output of the first element And, the second

20 input of the second parallel adder under the keys to the information input of the scraper, the output of the second parallel adder is connected to the input of the second register, to the first input of the first parallel adder and to the first input of the third parallel adder, the output of the second register is connected to the first input of the second element And the second input which is connected to the clock input of the extrapolator, the output of the second element And. connected to the second input of the third parallel adder, the output of which is connected to the second input of the first parallel adder.

 The drawing shows a block diagram of a digital extrapolator.

The digital extrapolator contains the first register 1, the element I 2, the first parallel adder 3, the frequency converter 4, the reversible counter 5, the second paral adder 6, the third parallel adder 7, the second register 8, the second element And 9, clock input 10 extrapolator, information input 11 of the extrapolator, exit 12 of the extrapolator.

The digital extrapolator works as follows.

The arrival of the current value of the input code n, its previous value on the clock pulse is rewritten into the second parallel adder 6, and the reversible counter 5 is zeroed. After that, the current code value X t vi} i is written to the first register 1, to the reversible counter 5 and fed to the second input of the second parallel adder 6, in which the first final difference is calculated

vNrnl Xlnl-Xln-i.

The difference code obtained in the second parallel adder 6 enters the second register 8, to the first input of the first parallel adder 3 and to the first input of the third parallel adder 7, which already has the code V NC-0 3-xr -111, half - rented in the previous cycle of work of the extrapolator. And the clock pulse rewritten from the second register 8 through the second element and 9. From the output of the third parallel adder 7, the second difference V is exceeded. vN f WQ - SjV t is fed to the second input of the first parallel adder 3, where the sum VNtn VNtvVlV HCfi is calculated, which using the converter 4 converts the frequency frequency to the pulse frequency. The output frequency of the 4 code-frequency converter is. Р | Г-РОЧН г 1, where FO is the reference frequency; R is the code width.

The frequency from the output of the converter 4, the code frequency, is fed to the input of the reversible counter 5, the control inputs of which are connected to the outputs of the sign bit of the first parallel adder 3. Depending on the sign of the code. The reversible counter 5 performs the summation or expansion of the incoming pulses.

The invention makes it possible to increase the accuracy of the extrapolator.

Claims (2)

1. Besekersky V. A. Dynamic synthesis of automatic control. M., Science, 1979, 2. USSR author's certificate W 694865 cl. G 06 F 15/20, 1979 (prototype).