SU828199A1 - Parallel digital integrator with floating point - Google Patents

Description

one

The invention relates to the field of computing, in particular to digital integrating machines, and can be used in homogeneous computing systems.

A parallel digital integrator 1 is known, consisting of two adders and a multiplying device. The disadvantages of this device include the fact that in the process of programming it is necessary to scale the variables.

The closest in technical essence to the invention is a parallel floating point digital integrator 2 containing an integrator adder, a counter, a shift register, the first inputs of which are information inputs of the integrator, the remainder integrator, the output of which is the information output of the integrator, the first a decoder, a multiplier, a normalization driver, the first inputs of which are integrator control inputs, and a second decoder.

The disadvantage of this integrator is the low measurement accuracy.

The aim of the invention is to improve the accuracy of work.

The goal is achieved by the fact that the proposed integrator additionally introduces a third decoder, an overflow signal generator, two groups of elements I, the outputs of the senior Q. bits of the adder of the integrand function are connected respectively to the inputs of the multiplier, the outputs of which are connected to the inputs of the adder of the integral residue, the outputs of the senior and the sign bit of the adder of the integrand function is connected to the second and third inputs of the normalization signal former, the first output of which is connected to the second entrances

the adder of the integrand function, the first decoder and counter and the first input of the third decoder, the first and second outputs of which are connected respectively to the first and second inputs of the overflow signal generator and the second decoder and the second and third inputs of the shift register, the first and second outputs of the shift register are connected to the third and fourth inputs of the second decoder, the first output of which is connected to the third input of the overflow signal generator and to the first inputs of elements AND of the first group, outputs cat ryh connected to inputs of elementary K bits.

the integrator of the integrand, the second output of the decoder is connected to the fourth input of the overflow signal generator and to the first inputs of the AND elements of the second group, the outputs of which are connected to the inputs of the higher D bits of the integrator. The third output of the shift register is connected to the second inputs of the first elements of the first and second groups, the fourth output to the second inputs of the second elements of the first and second groups, and the fifth output to the second inputs of the third elements of the first and second groups. The second output of the normalization signal generator is connected to the second input of the third decoder, the third inputs of the adder of the integrand function, the first decoder and the counter, the output of which is connected to the fourth input of the normalization signal generator, the output of the first decoder and the first integrator output information, and the first input of the integrator residual. The third inputs of the elements of the first and second groups are connected to the information input of the integrator. The third input of the third decoder and the fifth input of the normalization signal generator are connected to the integrator's control input. The output of the overflow signal generator is connected to the control output of the device.

On the outline there is a structural scheme of the integrator.

It contains an adder 1 of the integrand function, a counter 2, a shift register 3, an adder 4 of the integral residue, decoders 5, 6, 7, a multiplier 8, a normalization signal generator 9, an overflow signal generator 10 and a group of AI elements, 12.

The integrator works as follows.

The weights of the initial values of the integrands and their increments are pre-aligned.

In register 3, the pulse, which determines the difference of weights of the integrand function and its increments, is shifted left or right according to the signals produced by the decoder 5 to increase or decrease the weight of the input increment, respectively. The decoder 6 generates the sign of the difference in weights of the integrand function and its increments. At the same time, the positive sign of the weight difference is generated when the pulse is in the higher de register 3 when the input from the decoder 5 is a signal to increase the input increment weight, and negative when the pulse is in the lower section of the register 3 and when the signal comes from the decoder 5 to decrease the weight of the input increment. When the pulse is re-recorded in the low or high register register 3, it is generated by the driver

10 overflow signal. With a positive sign of the weight difference and the signal coming from register 3, the corresponding element AND 12 is given an increment of the integrand function, the weight of which is more than a quantum and is summed up in the adder 1 s / C with the higher bits of the integrand function. And with a negative sign, the weights are distinguished by the corresponding element 11, the increment, the weight of which is less than a quantum and is summed with the lower order bits of the function. At the same time, the higher L bits of the integrand function simultaneously arrive at the inputs of the multiplier 8, where they multiply by the increment of the variable integration and the result is summed by the parallel code in the adder 4 s / (the remainder bits. And if the result of the summation results in an overflow of the adder grid 4, then an increment of the integral is output from it. At the end of the integration operation, the values calculated in the adder 1 of the integrand function are analyzed by the shaper 9, which produces normalization signals to the left ( automatically), in the adder 1, the code of the integrand function is shifted to the left (right), in the counter 2. single pulses are subtracted (added up), and the decoder 5 generates a signal for changing the weight of the input increment. The signal for increasing the weight of the input increment the decoder 5 produces in the following cases :

- when the input signal at its input increases the weight of the input increment and in the absence of normalization signals;

- when the input signal at its input increases the weight of the input increment and when the normalization signal arrives to the left;

- in the absence of a signal to increase the weight of the input increment and when the normalization signal arrives to the left.

The signal to reduce the weight of the input increment is produced when there is no signal to increase the weight of the input increment and when the normalization signal arrives. The signal for increasing the weight of the output increment is generated by the decoder 7 by the signal of normalization to the left or by the signal of increasing the weight of the increment of the variable integration. If these signals are received simultaneously, then the decoder 7 will generate one signal for increasing the weight of the output increment, and the second will be memorized. The latter is issued only when there is no signal to increase the weight of the increments of the variable integration and there is no normalization signal to the right. When outputting an increase in weight signal of the output increment in adder 4, the residual code is shifted to the left by one bit.

The introduction of new blocks into the integrator allows one to increase the computational accuracy due to the fact that the loss of input increments smaller than a quantum is eliminated.

Claims (2)

1. Analog and analog digital computer technology. M., Mechanical Engineering, . 2. Report "Parabola-2 State. per. No. 69018223, technical description, p. 8-29 (prototype).