SU630628A1 - Multiplier - Google Patents

Description

one

The invention relates to computing.

Known and1fro.yvo duplicating device containing registers, elements AND, OR 1.

The disadvantage of this device is complexity and low speed.

The closest are: The technical solution to the invention is a multiplication device containing two reversible counters, an impulse generator, the output of which is connected to the first inputs of the first and second And elements, and through the delay element to the first inputs of the third and fourth And 2 elements. .

Its disadvantage lies in its low speed.

The purpose of the invention is to improve the speed of the device.

This is achieved by the fact that the device contains an adder and two comparison circuits, the first group of inputs each of which is connected to the corresponding group of information inputs of the device, the second group of inputs to the outputs of the corresponding reversible counter and the first group of inputs of the adder-subtractor, outputs The first and second comparison circuits are connected to the second inputs of the first, second, third, fourth, respectively.

ALE: cops I, the outputs of the first, second, third, fourth elements AND, respectively, to the inputs of the first and. second reversible counters 1 and the second group of inputs of the adder-subtractor.

The drawing shows a fused circuit diagram of the device.

The device contains reversible countercards / 1 and / 2, elements AND 2-5, generator im.uli, element 7 delay, circuits §1 and §2 comparison, adder-subtractor 9.

The operation of the device is based on the representation of the product of the two signals .g / in the form of the sum of the individual increments of Ar, which is calculated by the formula DgA-. y + y A.v + A.t: At /. (1)

(Expression (1) is simplified, if iy and и and Aiy) single increments and changes in signals .V 11 y occur only at different points in time. Then correlation (1) is converted to.

y if al- 1

AGL, if Ar / I A.v 0 O, if A. Ar / 0.

Claims (2)

Selection of single increments of the input signals X and y and their separation in time are carried out by two digital tracking systems, formed by the comparison circuit Si, elements I 2, -3, roar € rsi, now m counter / 1 for factors. ti x-scheme 82, element i. And 4, 5, counter / 2 dl y; generator of 6 clock pulses and delay element 7 with the help of pho, rm, iro | axii sncnals x l y, which are output signals of reversive counters 1 and / 2 Any increments of the input signals X and y are converted into the sum of unit increments of x and y Indeed, let equality be observed at the time of Gs. zh lo; At У УО, г х-у к 1/0 2о, and at the moment i there is a change in the factor X and the value + YES. Then, using the comparison circuit of §1, the inequality of the signals X and x is revealed, and it opens the element AND 2. A pulse begins to arrive at the summing input of the reversible counter. The arrival of a long pulse means the increase in the unit of the youngest digit, the number of l: ..., i.e., in the case of a single unit, of rotation. At the same time, the element 2 gives pulses to the control input of the sum of the signal y in the adder-subtractor 9. At every single change and signal x, the signal y is added to the sum of the subtractor. equal in digital form, the magnitude of the averaging is YES :, the signal x becomes the different value of the signal x, i.e. A A --- Ao – g YES. It is obvious that the content of the a-subtractor is increased by .. 2) A. X: Wo - A X and becomes equal to 2 2о-Ьгг. ГоУо + г / ОДА D.г) г / о ХУО X Vp After this, the comparison circuit closes the element .and 2 and stops receiving pulses "and the input of the reversing 0: counter 1. Thus, the input of the proposed device will be the signal code, which is the input", and the codes of the x and y signal codes. The operation of the device for negative increments (i-YES-) with a change in the signal y and is similar. In order to exclude the fault of the 1pr and the simultaneous change of the signals A- and y of the changes of the signals x and y are separated in time by means of the delay element 7. The accuracy of the work is not limited and depends on the size of the digital blocks included in the device. The proposed device, in contrast to the prototya, has a factor of ten times faster than the speed, since the work is carried out with a pair of parallel codes. And there is no time delay necessary to receive a signal that the meter is overrun. .ica. In addition, the application of the proposed device is possible without additional autonomic | .1Nykh devices, namely, without devices for generating individual increments and without an adder at the output of the device. It is necessary to make a device for obtaining a work code. The invention is a multiplying device containing two reversible counters, an I-Miases generator, the output of which is connected to the first inputs of the first and second elements AND, and through the delay element to the first inputs of the third and fourth elements And, characterized in that the device’s speed, it contains a sum, a subtractor and two comparison circuits, the first group of inputs of each of which is connected to the corresponding information input of the device, and the group of inputs to the outputs of the corresponding version of the counter and the first group of inputs of the adder-subtractor, the outputs of the first and second comparison circuits are connected. To the second inputs of the first, second, third, fourth And elements, the outputs of the first, second, third, fourth And elements, respectively, are connected to To the turns of the first and second reversible counts 1 k.v and to the second group of inputs the sum of the jura-subtractor. Sources of information taken into account pr.i and expertise: 1. USSR author's certificate number 310257, G 06 F 7/52, 1970. 2. Authors certificate of USSR L 135599, G 06 F 7/52, 1968.