SU1218367A1 - Digital device for controlling motor velocity - Google Patents

Abstract

The invention relates to the field of control systems controlled by computer devices and is intended to control the speed of an engine. The purpose of the invention is to reduce the engine speed control time. The digital engine speed control device includes a counter with a variable conversion factor, AND element, a computing unit, a speed control unit, a control unit and a pulse sensor. In the computing unit, the engine rotational speed is calculated by the formula, t, m, 60 "f W - k -, where k --- is a constant value for the device, its value is stored in the device; f is the pulse frequency; Z is the number of pulses coming from the sensor per revolution of the needle shaft; m is the number of pulses accumulated in the counter with a variable conversion factor; n is the number of pulses accumulated in the computing unit. 3 il. S

Description

one

The invention relates to control systems controlled by computing devices and is intended to control the speed of the engine.

The purpose of the invention is to reduce the time of regulation of the rotation speed of the engine.

FIG. 1 is a block diagram of the device; in fig. 2 is a diagram of a computing unit; in fig. 3 is a control block diagram.

The device consists of an AND 1 element, a counter 2 with a variable: a conversion factor, a computing unit 3, a speed control unit 4 implemented on the basis of a pulse width modulator, a control unit 5, and a pulse sensor 6.

The scheme of the computing unit 3 consists of the divisor 7, the multiplier 8 of the subtractive unit 9, the element 10, the counter 11 and the unit 12 for generating the conversion factor.

Divider 7 is completed according to the standard division scheme without restoring residues and with a divider shift to the right.

The multiplier 8 is made in the well-known multiplication scheme by the high bits ahead with the multiplicative shift to the right. It consists (not shown) of an adder, a register, a multiplier register and a multiplication control block, the adder being connected to the multiplicand register, the multiplier register is connected to the input of the multiplication control block, and the outputs are connected to the adder register register multiplier and register multiplier. The inputs and outputs of the multiplier 8 are connected to the multiplication control unit.

The subtracting .block 9 is complete according to the scheme of the parallel binary adder of numbers in the return code with group transfer by four bits. Consists (not shown) of the addition control function blocks, four entry schemes, four transfer schemes and four binary sum schemes, the input circuits connected to the corresponding transfer schemes and binary sum schemes, the transfer schemes are connected to the corresponding binary sum schemes also consistently among themselves

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and the output of the subtracting unit 9 is connected to the addition control unit. 5 A schematic of the control unit 5 is shown in FIG. 3. The control unit consists of the display unit 13, the memory unit. 14, control unit 15 with a keyboard, a memory register 16, elements 10 OR 17, 18, a trigger 19, a pulse generator 20, a frequency divider 21 and a pulse generator 22.

The speed control device comprises a motor 23.

15 The device operates as follows.

Using the keyboard control unit 15, the rotation speed setpoint of the engine 23 is entered into the memory register 16, the value of which is indicated in the display unit 13. The Start command issued from the keyboard control unit 15 switches on S the pulse generator 20, and through the OR 18 element trigger 19

 set to unit, and element AND 1 of the digital speed control system, element 10 of the computing unit receives resolution signals that transmit pulses from the pulse sensor 6 of the digital speed control system to counter 2 and pulses from the frequency divider 21 to the counter 11 of the computing unit. the front of the enable signal, pulse generator 22 produces a pulse that flips counters 2 and 11 and prepares them for operation. Subsequently, the signal of the resolution comes from the speed control unit 4 after issuing control actions to the engine 23. After accumulation in the counter 2 of the digital pulse rate rate control system, determined by the coefficient. recalculation of the counter 2, as well as after the overflow of the counter 11 of the computing unit (the latter is possible at low speeds of the engine 23 at the moment of its start), the trigger 19 of the control unit 5 through the element OR 17 receives a signal that sets the trigger 19 to zero, after which element AND 1 of the digital control device and element 10 of the computing unit do not transmit pulses to counters 2 and 11.

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in computing unit 3, the rotational speed of the engine 23 is calculated using the formula

W K -GP

where K ---- is a constant for a given device, its value is stored in memory 14;

f is the pulse frequency with frequency divider 21;

Z is the number of pulses coming from the pulse sensor 6 speed for one revolution of the shaft of the engine 23; m is the number of pulses accumulated in counter 2 (conversion factor);

n is the number of pulses accumulated in the counting device 1 1.

; In the divider 7 of the computing unit 3 according to the formula (1), the contents of the counter 2 (t) are divided by the contents of the counter 11 (n). Then, in multiplier 8, the result of the division is multiplied by the coefficient K stored in memory unit 14. In subtraction unit 9, the difference between the rotational speed is determined after calculating the input from the multiplier 8 and the rotational speed setpoint in memory register 16. The subtraction unit performs subtraction with a predetermined accuracy required to set the rotational speed of the engine 23. The difference signal from the subtraction unit 9 enters the conversion factor generation unit 12, which is uniquely determined by the incoming difference the value of the conversion factor, which also improves the speed of the device. .

As a block for the formation of conversion factors, a permanent memory device (ROM) is used on the chip 556 PT4. The difference from the subtractive unit 9 is fed to the input bus (address bus), the value of the conversion factor corresponding to the difference is output from the output bus (data bus).

12183674

The conversion factor, which is inversely proportional to the difference from subtraction unit 9, is then transferred to the count 5.

Synchronization of the computing unit is as follows. Since the divider 7, the multiplier 8 and the subtracting unit 9 must operate sequentially, each of the listed devices starts its work when the leading edge of the work enable pulse arrives at its input, and, in turn, after performing the corresponding operations, generates output pulses permitting subsequent devices to work.

Difference from subtraction unit 9.

2Q enters the speed control unit 4, which converts the digital value into a pulse-width signal. The signal causes the necessary change in the speed of the engine 23,

25 after which the control cycle is repeated.

Claims (2)

1. Digital device for control. motor speed, comprising a motor, a pulse speed sensor connected to the motor shaft, a first pulse counter, a control unit and a pulse width unit 35 modulators for speed control. engine, characterized in that, in order to reduce the time of regulation of the rotational speed of the engine in the device, it is 40, the first and second elements are given AND, the second pulse counter and the successively single divider, multiplier, subtraction unit and conversion factor generation unit, 45 whose output is connected to the first input of the first pulse counter, the second input of which is connected to the output of the first element I, the third input to the first output of the control unit 50, the second output of which is connected to the first input of the first element I connected to the second input to the speed sensor output , the first output of the first pulse counter. 55 is connected to the first input of the control unit, the second output is connected to the first input of the divider connected by the second input to the first output of the second. of the second pulse counter, the second output of which is connected to the second input of the control unit, the first input of the second pulse counter is connected to the first output of the control unit, the second input is connected to the output of the second element And, the first and second inputs of which are connected to the second and third outputs the control unit, respectively, the first output of the pulse-width modulator unit for controlling the speed of the engine is connected to the engine, the second output is connected to the third input of the control unit, and the first and second inputs are respectively to the first and second outputs With the signals of the subtracting unit and with the second input of the unit for generating conversion factors, the synchronization-pulse splitter input is connected to the fourth output of the control unit, a. the second divider output is with the second input of the multiplier, the second output of which is connected to the second input of the reading unit, the third input of the multiplier and you: the reading unit is connected to the fifth and sixth outputs of the control unit connected to the fourth output of the fourth multiplier and multiplier . 2. The device according to claim 1, wherein the control unit contains a memory block, a control key, a memory register, two liTM elements, a clock generator, a pulse divider, an RS-trigger, output connected to the second output of the control unit, pulse generator, the output of which is connected to the first output of the control unit, the first output of the control keyboard via the memory register is connected to the indicator and to the sixth output of the control unit, the first and second inputs of the control unit through the first the element OR is connected to the second input of the RS trigger, the second input connected to the output of the second OR element, the first input of which is connected to the third input of the control unit and the second input to the second output of the control keyboard and to the input of the pulse generator whose output is connected to the seventh output the control unit and, through a pulse divider, to the third output of the control unit, the outputs of the memory unit are connected to the fifth output of the control unit, the second output RS of the trigger is connected to the fourth output of the control unit. rig.}  about / J /four