SU1659986A1 - Linear interpolator - Google Patents

Abstract

The invention relates to computing and can be used in computer numerical control systems. The purpose of the invention is to reduce the hardware cost and the amount of interpolator memory. The linear interpolator contains a controlled clock generator, a coefficient code register, a higher increment code write counter, a pulse distributor, a matrix of memory elements of steps, a trigger, output drivers. The interpolator has a logical unit input, a setup input, a start input, a slope coefficient input, record inputs, a larger increment input, a step increment output along the leading coordinate, an output along another coordinate. The line segment is specified by the value of the larger increment and the control code, stored respectively by the higher increment counter and register. The matrix of memory elements for each value of the control code contains the first half of the sequence of incremental increments along the slave coordinate, which are symmetrical about its center. When the pulses are distributed by the pulse distributor towards the higher bits, the first half of the sequence of incremental increments is read, and when the pulses are distributed towards the lower bits, the second half is read. The D-flip-flop state determines the direction of pulse distribution. The number of interpolation cycles counted by the counter is equal to the value of the larger increment. 1 hp f-ly, 4 ill. cl

Description

The invention relates to computing and can be used in computer numerical control systems.

The purpose of the invention is to reduce hardware costs and the amount of permanent memory.

Figure 1 shows the structural scheme of the proposed interpolator; Fig. 2 is a functional diagram of the implementation of a controlled clock generator; fig. 3 - organization of memory elements; on

4 is an example of the organization of the pulse distributor and triggers 6.

The linear interpolator contains a controlled oscillator of 1 clock pulses, a register 2 of the coefficient code, a counter 3 records of a higher increment code, a distributor of 4 pulses, a matrix of 5 step memory elements, a trigger 6, output drivers 7 and 8 pulses. The interpolator has an input of 9 logical units, an input of 10 initial settings, an input 11 of start, an input 12 of a slope coefficient, an input of 13 entries.

Os

the next

h with about

input 14 records, input 15 larger increments, output 16 step increments in the leading coordinate, output 17 step increments in another coordinate.

The generator 1 consists of the first element And 18, the generator 19 pulses, the first 20 and second 21 D-flip-flops, the second element And 22.

The pulse distributor 4 contains the elements 2I-OR and D trigger 24i 24 |. When the power is turned on, a negative pulse is applied to the specified input from an external device, which sets the internal elements of the generator 1 to its initial state.

Register 2 is used to store the control code supplied to the input 12 of the control code from an external device. The control code is written to register 2 by a negative drop of the write signal at its control input. The specified input of register 2 is connected to input 13 of the record of the control code of the interpolator.

Counter 3 is designed to determine the end of the interpolation of a segment. The input of the record of the counter 3 is connected to the input 14 of the record of the higher increment code of the interpolator, the information input is connected to the input 15 of the higher incremental code. The active signal level of the write to the counter of the higher incrementing code is zero. This signal is also fed to the inputs of the initial installation of the distributor of 4 pulses and trigger 6. In this case, the unit is recorded in the lowest bit of the distributor of 4 pulses and the zero state of all subsequent bits is set, as well as the trigger state is set to one.

Distributor 4 impulses It is a block that, when a series of pulses arrives at its input, pulses alternately from each of its outputs. The outputs of pulse distributor 4 and register 2 select the contents of the matrix of 5 step memory elements.

The matrix 5 of the pitch memory elements may be a ferrite, transistor RAM, or semiconductor memory integrated circuits on bipolar transistor structures, or ROM, for example, consisting of two input cells AND, or a diode array.

The trigger 6 switches the direction of the pulse distributor in the pulse distributor 4. The high bit output of the distributor 4 is connected to the control input of trigger 6, the direct and inverse outputs of which are connected to

the first and second inputs of the shift direction of the distributor 4 pulses.

Output shapers 7 and 8 are intended for rationing the output

signals for the duration. This normalization is necessary when ferrites are used as a matrix of memory elements of steps.

The outputs of the output drivers 7 and

8 are connected respectively to the output of 16 step increments along the leading coordinate and the output 17 step increments along the slave coordinate of the linear interpolator.

The interpolator works as follows.

In the well-known interpolator, the matrix of memory elements of steps has 2P addresses and n bits, and the units are written

2 (2K-1) -th addresses, where K 1, 22P 1, 1 1,

2.3 (1)

For example (see Fig. 3), for five bits (p 5) and 32 addresses (2 elements matrix has single states of memory cells:

in the 1st category de - in 1,3,5,7,9,11,13,15,17 ...

addresses; in the 2nd category de-2,6,10,14,18,22,26.30 addresses; 3 rd de address: 4,12,20,28 addresses; in the 4th category de - in 8 and 24 addresses; in the 5th category de - 16 address.

The indicated memory allocation corresponds to the operation of the digital sequential transfer integrator. The following is characteristic of the organization of the memory: the arrangement of units in bits

matrixes of memory elements symmetrical with respect to the memory cell with the address:

/ h Ј-

Thus, reduction is possible.

tabular data of the matrix of memory elements twice by writing the units in accordance with formula (1) into memory cells with addresses from 1 to 2 and reading their contents during the interpolation process twice: starting from the 1st address to 2H in in the forward direction (corresponds to reading the contents of the memory cells in the well-known interpolator with addresses from 1 to) and from the address to the 1st in the opposite direction

(corresponds to reading the contents of memory cells in the well-known interpolator with addresses from 2P).

We consider the organization of the matrix of memory elements on a specific example.

(p 5).

The contents of the matrix of memory elements in the well-known interpolator shows that the distribution of units is symmetrical with respect to address 16. Obviously, the volume

the matrix can be halved by reading its cells 16 strokes in the forward direction, and starting from 16 clocks in the opposite direction. Let the control code be 10010, where the one on the left corresponds to the youngest bit of the control code, i.e. With such a control, the $ 1 code in 9 clock cycles generated 9 pulses, the distribution of which in 32 clock cycles is shown in Fig. 36.

In the proposed interpolator, the matrix of memory elements has twice the volume. The contents of the matrix of 5 elements of the memory of steps is shown in FIG. With the control code 10010, 5 pulses were read in the first 16 clock periods of time (Fig. 3g). In this case, the dispenser 4 pulses during the first 16 cycles performs the distribution in the forward direction. In the 16th clock cycle, it changes the direction of the distributor, which allows to generate 4 pulses in the next 16 cycles (see Fig. 3e).

The total sequence obtained in the first and second 16 cycles (Fig. Ze) does not differ from the sequence formed by the known interpolator.

When the rising edge of the control signal appears at the input 11 of the interpolator trigger, the clock pulse generator 1 at its output generates a sequence of pulses until the overflow signal of the counter 3 records the higher increment code. The control signal from the overflow output of the counter 3 is fed to the stop input of the generator 1.

In the proposed interpolator, step increments along the leading coordinate are formed in each interpolation beat, therefore the number of interpolation steps equals the larger increment (PS). Step increments along the driven coordinate are formed at the output of the matrix 5 step memory elements. At the same time, the value of the control code stored in register 2 must be such that, for the number of clock cycles equal to BP, at the output of the matrix 5 step memory elements, MP-pulses are formed, where MP is the value of the smaller increment.

The number of pulses in | at the expense of the 1st bit of the control code during the time of the PSU is expressed by the ratio

-

BP +2

I -1

il

ts.ch

where | q.ch is the integer selection operator; eleven.

In order for the number of clock cycles equal to the PSU, at the output of the matrix of memory elements, MP pulses must be formed, the ratio 52aibj Mn must be satisfied

where ai is the value of the digit in the i-th bit of the control code.

Thus, the task of determining the control code is reduced to determining

10 ai, 32an by known values of BP and MP

using the above ratios. Here, the bi values are found and the MP value is balanced by them.

In the proposed interpolator, the segment is specified by a direct value of the larger increment and the value of the control code.

When the power is turned on, an impulse arrives from the external device at input 10 of the initial installation of the interpolator, which sets the controlled oscillator 1 to the initial state. At the output of generator 1, no pulses are generated.

The register 2 from the external device records the value of the control code supplied to the input 12 of the control code of the interpolator. The record in the register is made by the zero level applied to the input 13 of the record of the control code of the inter- poltor.

The counter 3 records the value of the power supply unit fed to the input 15. The power supply is written to the zero level supplied to the input 14 of the recording of the power supply unit 5 of the interpolator. This signal is also fed to the inputs of the initial installation of the distributor 4 and trigger 6. In this case, the unit is written to the low-order bit of the distributor 4 and set to the zero-left state of all subsequent bits, and also sets the trigger 6 to the single state .

The controlled clock generator is triggered by the rising edge 5 of the trigger signal, which is fed to the trigger input 11 of the interpolator. At the output of generator 1, a sequence of pulses of a given frequency is formed. This sequence of clock pulses is fed to the counting input of counter 3, the input of the distributor 4 and the input of the generator 7. At the output of the matrix of the step memory elements 5, a sequence of pulses is formed corresponding to a smaller increment (on the driven coordinate).

The distributor 4 carries out the distribution (fig. 3b) in the forward direction for 2 periods of time. In the cycle at the output of the higher bit of the distributor, a signal of the logical unit is formed, ensuring the trigger 6 is set to the zero state. The latter, in turn, changes the direction of shift of the distributor 4. In the subsequent cycles, the cells of the matrix 5 are read in the opposite direction.

With the arrival of each pulse from generator 1, the contents of the counter 3 of the BP record are reduced by one. When the generator 1 produces a number of pulses equal to the PSU, an overflow signal is generated at the output of the PSU counter, leading to the installation of generator 1 to its initial state, in which no pulses are output to the output of the clock generator.

The proposed linear interpolator is built on elements that are part of commercially available microcircuits, series 155,555,531.

The distributor 4 can be synthesized in various ways.

The implementation of the matrix 5 and the formers 7 and 8 does not differ from their implementation in the known interpolator.

The controlled clock generator operates as follows (variant).

In the initial state, the trigger 20 and 21 are reset. This is achieved in the initial turn-on by applying to the second input of the element I 18 a reset pulse upon power-up. When a leading edge appears at the input 11 of the interpolator launch, the second trigger switches to the state of logical one, and when the front edge of a pulse forms by generator 19, another trigger also switches to the single state. In this case, the transmission of pulses to the output of element 22 from generator 19 is permitted. These actions ensure a synchronized start of the interpolator operation to the leading edge of the pulse from generator 19.

In this linear interpolator, the volume of the matrix of memory elements of steps is equal to. Thus, the reduction of the volume of the matrix of memory elements by half was achieved. In addition, the pulse distributor bit is reduced by half, indicating a reduction in hardware costs.

Claims (2)

Claim 1. Linear interpolator containing a controlled clock generator, coefficient code register, large increment code code write counter, pulse distributor, step memory elements matrix, first and second output shapers, outputs which are connected respectively with the first and second information outputs of the interpolator, the input of the control code of which through the coefficient code register connected to the information input of the matrix of memory elements of steps, the address input of which is connected to the information output of the pulse distributor, the information input of which is connected to 0 by the output of a controlled clock generator, with information inputs of a larger code incrementing counter and the first output driver, the device start input is connected to the startup input of a controlled clock generator, whose stop input is connected to the overflow output of a larger code incrementing counter, information input which is connected to the input 0 tasks of a larger increment of the interpolator, the output of the matrix of memory elements of steps is connected to the input of the second output pulse shaper, characterized in that, in order to reduce the equipment costs and the amount of permanent memory, a D-flip-flop is added to it the installation R-input of which is connected to the input of the initial installation of the pulse distributor, the recording input 0 a higher increment code write counter and a higher increment interpolator code write input, the initial setup input of which is connected to the initial setup input of a controlled clock pulse generator, the input of which logical unit is connected to the output of the logical unit of the linear interpolator, direct and inverse trigger outputs are connected respectively to the first and second inputs of the shift direction of the pulse distributor, the high-order output of which is connected to the inverse control S-input of the trigger, in ormatsionny D-input of which is connected to a common bus, The 5th input of the register coefficient control code entry is connected to the input of the linear interpolator control code record. 2. An interpolator in accordance with claim 1, from a field station so that the controlled clock generator contains the first and second elements AND, the first and second D-flip-flops, the generator of pulses, the output of which is connected to the first input of the second element AND 5 and the control input of the second D-flip-flop, the output of which is connected to the second input of the second element AND whose output is the generator output, the output of the second flip-flop is connected to the information input of the first D-flip-flop, the inverse setup inputs of the second and first D-flip-flops are connected to the output of the first element And, the first and second inputs of which are respectively the stop input of the clock generator and the input of its initial installation, the information input of the second trigger is connected to the input of the logical unit of the generator clock pulse, and the control input is connected to the start input. / 4 15 1 KZ, H, 7 FIG. 2