SU1309042A1 - Device for finding faulted blocks and elements - Google Patents

Abstract

The invention relates to the field of computer technology and can be used in specialized systems, microprocessor control complexes and devices. The purpose of the invention is to increase the speed of the device by reducing the enumeration of the columns of the fault table. The device contains a register of 1 columns of the fault table, a register of 2 parameters of the object, a comparison block 3, a logic block 4, an evaluation register 5, a block 6 for allocating the first unit, an encoder 7, a second memory block 8, an output register 9, an AND-NE element block 10 , block 11, result register 12, indication block 13, first memory block 14, control block 15, device Start 16 input, device information 17 group of inputs. 2 Il. (LP so about so about n (oo

Description

 The invention relates to computing and can be used in specialized computing systems, microprocessor control complexes and devices.

The aim of the invention is to improve the speed of the device by reducing the enumeration of the columns of the fault table.

FIG. 1 shows the structure of the device; in fig. 2 is a functional block diagram of the control unit.

The device contains (Fig. 1) register 1 columns of the faulty table, object parameter register 2, comparison block 3, logical block 4, evaluation register 5, first-unit allocation block b, encoder 7, second memory block 8, output register 9, block of elements AND-NE 10, block of elements AND 11, result register 12, display block 13, first memory block 14, control block 15, device start 16, device information device 17 group.

The control unit 15 (FIG. 2) comprises a pulse generator 18, an AND element 19, a pulse counter 20, a decoder 21, and a trigger 22.

All device registers have a typical structure on static triggers, which allows

direct code when submitting control

The signal C ,, the storage of the code and the issuance of the forward (by signal C) or reverse (by signal Cj) code stored in the register, while the initial (zero) state is set by signal C ,. Encoder 7 is a generic device that converts a unitary code to a binary positional code. The display unit 13 is implemented in the form of p LEDs, each of which is connected to potential inverse outputs of the trigger blocks of block 12. Blocks 8 and 14 are permanent memory devices with electric or ultraviolet erasure of information that can be written to any fault tables. Moreover, one and the same fault table is recorded in memory block 8 and memory block 14, but in memory block 8, the record is written in such a way that it is read in rows, and in memory block 14 - in columns. Block 6

The allocation of the first unit in a binary code is realized either as a shift register or as a device in order to provide speed.

Logic block 4 is a logic combinational circuit that implements a logical function of the form

those. At each i-th output of block 4, conjunctions are formed between the values of all other outputs of block 3 and the inversion of the considered i-ro output of block 3.

Each of (|| functions fj is realized with the help of one element NOT and one n-bit element AND, moreover, n-1 (except i-ro) outputs of block 3 are connected respectively to 1, 2, ..., i-1, i + 1,., .., n inputs of the corresponding element AND in the iM bit of block 4, and the i-th output of block 3 before connecting to the input of the element AND passes through the element NOT.

When describing the operation of the device, the following designations are used:

- code parameters of the object;

X

 fault table column code; - line code of the fault table;

take the value 1 or 0 depending on the value of the parameter;

- logical functions implemented at the outputs of the bits of the unit of 3 comparisons (binary codes of the object parameters and columns of the fault table);

- logical functions implemented at the outputs of the bit of logical block 4;

f, f, fj, ... are the logical functions implemented on the inverting outputs of the bits of the logic block 4; f fj f, ... are logical functions implemented at the outputs of block 11. C d is the signal to receive the address in the memory block Cd is the installation signal

of the original (zero) state of the corresponding block:

C ,, - code recording signal

on register

Cj is the signal for reading the direct register code; Cj is the read signal of the reverse register code;

. - reading information from the memory block.

The device works as follows.

The Start signal (fig. 1 and 2) starts the operation of the counter 20 of the control unit 15, which outputs a pulse from the zero output of the decoder 21. In this case, all registers 1, 2, 5, 9, 12 and (blocks 6, 8, 14 are set to The initial (zero) state, for this, the zero output of the decoder 21 is connected to the zero inputs C of all the listed devices.

The second pulse of the control unit 15 (from the first output of the decoder 21 is receiving (signal C | register 2) an object parameter code per register 2 object parameters.

The third pulse is fed to the census of the reverse code from register 2 (signal Cj of register 2) to the block 6 for allocating the first unit, and the fourth and fifth pulse for selecting the first unit in the return code of the object parameters (i.e. the first zero in the parameter code object). With the sixth pulse, the code of the first unit through the encoder 7 is written into the address register of the memory block 14 (which is part of any serial read-only memory).

The seventh pulse reads information from memory block 14 and writes it to register G. For this, the eighth output of the decoder 21 must be connected to the control input of register 1 (the code write signal C to register 1) and to the control input of memory block 14 (Cjp signal reading information from the memory at the specified address). -Eight pulses reverse code X and direct code X-, i.e. respectively, the contents of register 1 and the contents of register 2 (signals C are readings of the offset code and C is a read signal of the direct code) are read, pass through blocks 3 and 4, and by simultaneously starting the signal C, writing the code to register 5, write logical function in the register 5.

g

c f, g

g L

Then f is X &X; and the resultant n-bit bottom of the function f, written in register 5, has the form f

 (.Af) J.

To correctly record the value of the generated functions fj (j 1,2, ..., p), the duration of the control pulse simultaneously applied to the corresponding control inputs of the register I (signal Cj) and register 2 (signal Cj) of register 5 and the control input code (signal C) must be longer than the response time of the NAND and NAND logic elements in structures 3 and 4. This condition is easily satisfied for any logical basis (for example, the typical K 155 logic) by choosing a clock the frequency of operation of the counter 20 in the control unit 15.

A ninth pulse is performed by mixing the reverse code of register 5 (i.e., a function ff ft is generated while writing to the extraction unit 6. The tenth and eleventh pulses are necessary for the operation of block 6. The twelfth pulse records through the encoder 7 to the address register memory block 8 (signal) of reception of the code address code of memory block 8). The same pulse produces the initial setting (signal Cd) of the output register 9. The thirteenth pulse reads the contents of memory block 8 (signal Cgp) at the address recorded in the previous clock of control block 15. For this, simultaneously with the signal Cfr, a signal C is applied to the ret

gistr 9. The fourteenth pulse of the control unit 15 simultaneously reads the direct register code 5 (function f;) by applying the signal Cj to the register 5 of the direct register code 9 (signal C) and the reverse code of the register 2 (signal C) and the reception signal C, register 12 results.

At this point, the operation of the device ends and the fifteenth impulse of the control unit 15 can serve as an external termination signal. After fifteen clocks of the control unit 15, in the register target of the device speeding up, two memory blocks, a block for allocating the first unit, an encoder, an output register, AND-EY block, AND block, logical

pe 12 results are the recorded functions f. i (X; & X) & f. , and the 15th unit, the evaluation register and the control unit connected by the input to the device Start input, the first group of outputs to the corresponding inputs of the object parameter register and the register

since the LEDs of the display unit 1 3 are connected to inverse outputs

register, the result is displayed. , - (0 / lp with

ruschii code COD; one; (,, /, ..., p; ± 1

f,.,., f 5 which is the 20 columns of the fault table.

Boron numbers of faulty blocks of the controlled object (if you count from top to bottom, that is, from 1 to n).

The sixteenth impulse (the impulse of the output pits to the corresponding control inputs of the first memory block, and the third group of outputs to the corresponding control inputs

Replenishing the counter 20) sets the 25 inputs of the result register, the output control unit 15 to the initial (zero) state, automatically preparing it for the next work cycle.

Thus, in the device for reducing the search of the columns of the Fault Table compared with the object code, the object parameter code is additionally associated with a row of the unregister table, the second memory block, the allocation unit of the first unit and the evaluation register connected by a group of information inputs to the output group

30 logic blocks, and a group of outputs with a group of first inputs of a block of elements and with a group of first inputs of a selection unit of the first unit connected by a group of second inputs to

35 group of outputs of the register of parameters

The number of which coincides with the number of the entered column of the fault table such that the zero element of the main diagonal row coincides with the zero value of the 40 inputs of the first memory block and the group parameter of the parameter code, and the zero elements of the nondiagonal rows of the column correspond to the unit values of the corresponding parameters parameter code or single 45 sing outputs with a group of second inputs to elements of off-diagonal rows of a column-block of AND-NOT elements connected

. The values of the corresponding parameters of the parameters code parameters correspond to zero.

Claims (1)

Invention Formula the group of outputs to the group of second inputs of the block of elements And, connected by the group of outputs to the group of informational 50 inputs of the result register, the group of outputs of the first memory block is connected to the group of information inputs of the columns of the fault table; Device for searching faulty blocks and elements, containing the register of columns of the fault table of the 55 inputs of the object parameter register with the number of parameters connected to the group of information the object register of the object object inputs device; the input group is los by the number of parameters of the block connected to the group the object, the result register, the connection outputs of the comparison block. not a group of outputs with corresponding inputs of the display unit, a comparison unit connected by the first group of inputs to the corresponding bit outputs of the register of columns of the fault table, and the second group of inputs to the corresponding bit outputs of the object parameter register. excellent with that In order to improve the speed of the device, two memory blocks, a first unit allocation unit, an encoder, an output register, an AND-S block, an AND block, a logical the unit, the evaluation register and the control unit connected by the input to the device Start input, the first group of outputs to the corresponding inputs of the object parameter register and the register the second outgroup - to the corresponding control inputs of the first memory block, and the third group of outputs - to the corresponding control the inputs of the result register, the output the register, the second memory block, the allocation unit of the first unit and the evaluation register connected by a group of information inputs to a group of outputs logical block, and a group of outputs with a group of first inputs of a block of elements and with a group of first inputs of a selection unit of the first unit connected by a group of second inputs to group of parameters register outputs object and to the group of the first inputs of the block of NAND elements, and the group of outputs to the group of inputs of the encoder associated with the group of outputs with the address group Understanding the address inputs of the second memory block connected by a group of outputs to a group of information inputs of the output register connected by a group of outputs to a group of second inputs of a block of elements And connected by a group of outputs to a group of information 50 inputs of the result register, the group of outputs of the first memory block is connected to the group of information inputs of the register of columns of the faults table, the group of information 55 entries of the object parameter register sixteen 9ig.2