RU1812628C - Device for detection of group synchronization codes - Google Patents

Abstract

The group synchronization code detection device can be used in automation and computer devices. The device contains: 2 pulse counters. 2 AND elements, RS-flip-flop, decryption unit, storage device, 2 pulse shaper, N data decryption channels, N memory blocks, N D-flip-flops. N shift registers, N matching elements, input bus, clock bus, reset bus, output bus. 2 ill.

Description

The invention relates to pulsed technology and can be used in automation and computing devices.

The purpose of the invention is to increase the reliability of detection.

On the. FIG. 1 shows an electrical functional diagram of a device; in FIG. 2 is an example embodiment of a decryption unit.

The group synchronization code detection device comprises first and second pulse counters 1 and 2, first and second elements 3 and 4, RS flip-flops 5, decryption unit 6, memory 7, first and second pulse generators 8 and 9, N decryption channels data 10.1-10N, N memory blocks 11.1-11..N, M, O-flip-flops 12.1-12.N, N shift registers 13.1-13N, N matching elements 14.1-14.N.

The counting input of the first counter 1 pulse is connected to the bus 15 clock pulses, the counting input of the second counter 2 pulses is connected to the output of the first element And 3, the output of the second element And 4 is connected to the output bus 16 and the R-input of the RS-flip-flop 5. each of data decryption channels 1.Q.1-10.N consists of a memory block 11.1-11.N, the output of each of which is connected to the D-input of the 6-trigger 12.1-12.N, the output of which is connected to the information input of the shift register 12.1-12.N, the outputs of which are connected to the inputs of the matching element 14.1-14.N, and the outputs of the elements with the slots of each of the N channels of data decryption 10.1-10.N are connected to the corresponding inputs of the second element And 4, the output of which is connected to the installation input of the first pulse counter 1, the output of which is connected to the first input of the element And 3, the outputs of the least significant bits are connected to the corresponding address the inputs of the memory blocks 11.1-11.N of each of the N channels of the decoder00

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data 10.1-10.N, the high-order outputs are connected to the corresponding inputs of the decryption unit 6, the outputs of which are connected to the corresponding inputs of the resolution of the memory blocks 11.1-11.N of each of the N channels of data decryption 11.1-10.N, the information inputs of the blocks memory 11.1-11.N of each of N data decryption channels 10.1-10.N are connected to the input bus 17, the write-read inputs of which are connected to the output of the first pulse shaper 8, the input of which is connected to the clock bus 15, with the counting inputs of the registers Shear .13.1-13.N of each of N to data decryption 10.1-10.N and with the input of the second pulse former 9, the output of which is connected to the C-input of the D-flip-flops 12.1-12.N of each of the N decryption channels 10.1-10.N, and the outputs of the storage device are connected to . corresponding information inputs of the first pulse counter 1, address inputs - with the corresponding outputs of the second pulse counter 2, the installation input of which is connected to the reset bus 18 and the S-input of the RS-flip-flop 5, the direct output of which is connected to the second input of the first element And 3 .,

Consider the operation of this device in the case when information is transmitted in groups of words. Each group consists of 64 sixteen-bit words. In each group, four words are assigned for synchronization (group synchronization codes). In words with serial numbers 10, 26, and 42, there is a direct code for the sequence de Bryuzhna, and in the 58th word. is the inverse sequence code of de Bruizhne. The memory block 11.1-11.N in this device performs the function of a shift register, the bit of which should be 64x16 1024 bits, which corresponds to the capacity of one group of words. As memory it is necessary to use random access memory (RAM). Since the group synchronization code contains four words, this device must have four channels, with the first three channels detecting 10, 26, and 42 (direct de-Bruisign sequence code), and the fourth channel - 58 words (reverse Bruzhina). -Therefore, the first three channels will be identical, and the fourth channel will be different: from the first three only by the matching scheme. . Since the neighboring words included in the group synchronization code are 16 information / element words apart, i.e. 1 6x16 256 bits, therefore, the information capacity of the memory block 11.1 should be 256 bits, and the total information capacity of the RAM memory for our case is 256x41024 bits.

A part of this device, which consists of trigger 5, element 3, counter 2, and programmable memory 7, serves to programmatically adjust the address of memory block 11.1-11 for input information (for a group of words) to enter this device in synchronous work. During synchronous synchronous operation, the 10th words of each group of words are recorded in the memory block 11.1 of the first channel, the 26th words in

5 memory block 11.2 of the second channel, 42 words into memory block 11.3 of the third channel, and 58th words into memory block 11.4 of the fourth channel.:.

The device operates as follows,. : - -, ...:. .

Information from the output bus 17 is fed to the data inputs of all RAM memory blocks 11.1-11.4. The Reset signal from bus 18 sets

5 trigger 5 to the single state, and counter 2 to the zero state. The counter 2 sets at the output of the storage device 7 the contents of the zero cell, which is supplied to the installation inputs

0 counter 1. According to the clock signal from the clock bus 15, the address of counter 1 is first set. This counter sets the address of the memory cells of all memory blocks, and decryption block 6, which is a logical circuit, in high order counter 1 selects one of four memory units. The fundamental point in the operation of this device is that

0 operating time of one clock pulse, the input information is recorded in one specific cell of the memory unit with the address set at the output of counter 1, and information is read from

5 cells of all memory blocks 11.1-11.4 with the same address, i.e. while the information is being read, the decryption unit 6, at all its outputs, generates a chip selection signal for all four memory blocks.

0 Signals that control the recording and reading of information in the memory units are generated in signal conditioner 8.

In FIG. 2 shows the electrical circuit of this shaper. The information from the outputs of the memory blocks 11.1-11.4 is fed to the data inputs of the corresponding .D-flip-flops 12.1-12.4. According to the signals received from the shaper 9, the information from the outputs of the memory blocks 11.1-11.4 is copied to

 triggers 12.1-12.4. The information then goes to the inputs of the shift registers 13.1-13.4. According to the clock pulses coming from the clock bus 16, information is recorded in the shift registers. Therefore, for each clock pulse, the minimum element of input information will be recorded in a specific memory cell with the address indicated in counter 1, and the Minimum information element will be read from all memory blocks with the same addresses, and this information will be recorded in the corresponding shift registers 13.1- 13.4, The size of the shift registers is sixteen binary bits, which allows them to record completely sixteen-bit words. If the 20th word is completely written to the shift register 13.1, at the same time the 26th word is completely written on the shift register 13.2, and the 42nd word is completely written in the shift register 13.3, and the 58th word is written in the shift register 13.4. This arrangement of information on the shift registers is explained by the fact that 256 bits (memory cells) are located between memory cells with identical addresses of neighboring memory blocks - the same amount; how many minimal information elements are located between adjacent 1 group synchronization codes. With this arrangement of information, it will coincide on all elements of coincidence 14.1-14.4 and at their outputs all signals of coincidence. These signals are supplied to the inputs of the And 4. element. Information characterizing the detection of group synchronization codes at the output of the And 4 element only appears when coincidence signals appear at all inputs of this circuit. This device works in such a way when the input information and the address of the recording memory cell are located in such a way that the 10th information words will be completely recorded in the memory block 11..1, the 26th words in the memory block 11.2 and etc. This arrangement of information and the address of the recording memory cell is a special case. In general, this arrangement is random. The group synchronization code detection device is cycled. Each cycle consists of a group of words consisting of 64 words. The cyclic operation of this device leads to the fact that the relative position of the information and address does not change 6t cycle to cycle. A circuit consisting of a trigger 5, an AND element 3, a counter 2, a storage device 7, provides a change in the relative position between the information and the memory address from cycle to cycle, which ensures finding the necessary relative position of the information and memory address. Consider

5 how this part of the device works.

As soon as counter 1 counts 1024 clock pulses (full cycle), an output signal of the end of the cycle will be generated at its output, which, passing through the And 3 element, will increment 10 read the address of counter 2 by one. At the output of the storage device 7, the start address will change. According to the data clock pulse, the starting address is written to counter 1, which will change the mutual arrangement of information and the address of the memory blocks, if in this case the desired coincidence does not occur, the next pulse of the end of the cycle from counter 1 will change the address of counter 1 along the same chain this will continue until the information and memory address are in a position where the 10th information word is completely recorded on the first channel, the 26th word in the second channel, 42 in the third channel, and the 58th word is in the fourth channel. In this case, the detection signal from the output of the AND 4 element is supplied to the installation input of the trigger 5 and sets the era to the zero state. This closes

0 element And 3 for the passage of the pulse® end of the cycle. In addition, the detection signal will reset counter 1 to the zero state, which will ensure normal synchronous operation of the device.

5 An algorithm in which the start addresses of counter 1 are programmed is recorded. memory cells 7. depends on the arrangement of the group synchronization codecs within the information and. The time at which this device entered. in synchronous operation depends on the optimality of this algorithm.

The invention also includes a Group 5 synchronization code detection device containing a first pulse counter, the counting input of which

connected to the clock bus, a second pulse counter, the counting input of which is connected to the output of the first element

0 And, the second element And, the output of which is connected to the output bus, the RS-trigger and the input bus are switched off by the fact that, in order to increase the reliability of detection, a reset bus is introduced into it, the first

5 and a second pulse shaper, a storage device, a decryption unit and N data decryption channels, each of which consists of a memory unit, the output of which is & d in. With the D-input of the D-trigger, the output of which is connected to the information

the input of the shift register, the outputs of which are connected to the inputs of the match element, and the outputs of the match elements of each of the N channels of data decryption are connected to the corresponding inputs of the second element And, the output of which is connected to the R-input of the RS-trigger and the installation input of the first pulse counter, the output of which connected to the first input of the first AND element, the low-order outputs are connected to the corresponding address inputs of the memory blocks of each of the N data decryption channels, the high-level outputs are connected to the corresponding inputs of the decryption unit, the outputs of which are connected to the corresponding inputs of the memory blocks of each of the N data decryption channels, the information inputs of the memory blocks of each of the N decryption data channels are connected to the input bus, the write-read inputs of which are connected to the output of the first pulse shaper, whose input is connected to

clock bus, with counting

inputs of the shift registers of each of N

data decryption channels and with input

second pulse shaper output

which is connected to the C-input of the D-flip-flops

each of the N channels of data decryption, and the outputs of the storage device; t8a are connected to the corresponding information inputs of the first counter of pulses, the address inputs are connected to the corresponding inputs of the second counter

/ name; installation input of which

connected to the reset bus and S-input

RS trigger, my output is

connected to the second input of the first element And.:. ;