SU1561074A1 - Device for determining ratio of 16/90 sets - Google Patents

Abstract

The invention relates to computing and can be used in the construction of data bank management systems. The purpose of the invention is to expand the field of application of the device by implementing a comparison of all the relevant elements of the two sets. The device contains two switches 3 and 4, two registers 5 and 6 signs, a block 10 of comparison, the element NOT 14, elements OR 9 and a decoder 8

Two blocks 1 and 2 of memory, an encoder 7, two counters 11 and 12, three elements AND 16,17 and 20, a second element NOT 15, a delay element 19 and an OR element 18 of the initial installation are entered into it. After the comparison operation code is input to the device input, the elements of the sets are received alternately at the information inputs of the comparison blocks and, if the comparison criteria are fulfilled, the set ratio code appears at the output of the device. 1 il.

Description

| The invention relates to computing and can be used in data bank management systems.

 The aim of the invention is to expand the field of application of the device by implementing a comparison of all relevant; -; elements of two sets.

The drawing shows a diagram of the device.

The device contains blocks 1 and 2 of memory, switches 3 and 4, registers 5 and 6 signs, encoder 7, decoder 8, elements OR 9, comparison blocks 10, counters 11 and 12, output element OR 13, elements NOT 14 and 15, elements And 16, 17 ,, the initial installation element OR 18, the delay element 19, the AND element 20, the inputs 21 and 22, the start input 23, the outputs 24 and the clock input 25 "Comparison unit 10 checks the following comparison relations:,,, , It outputs a signal at its output only when the comparison relation, specifically determined by applying a single signal to the corresponding control input, is not satisfied between the codes on the groups of its information inputs and there is a signal at its enable input.

The encoder 7 outputs a signal at its output when a single signal is applied to its control input.

Blocks 1 and 2 of the memory store the elements of the compared sets. The last element of each set is marked with a unit in the 0th digit. The remaining elements of the sets are marked with a zero. The address of the elements of a set is an integer in the range from 1 to L, where L is the number of elements of the sets. The compared sets have the same dimension. Blocks

0

five

0

five

0

five

0

five

1 and 2 output the contents of the corresponding memory cells to their outputs and maintain it there when submitting the corresponding address to the address input about

The elements of sets consist of n components. Let lists be given, pg, ...,

p VYI and components defining the elements of two sets A and B to be compared (p, f are the numbers (names) of the components, i 1,2, ..., m,). Then, the criterion for comparing the elements of the sets A and B is

C ,, 9VG,) L (b, 2) A. ..)

where and oh element component

sets A, B. element component

sets B, 9 - one of the relations:

Ґ,,,, Each component of the elements of the sets in registers 5 and 6 corresponds to one bit.

The device works as follows.

According to the group of 21 entries in the bits of the register 5, the units corresponding to the list X are written. Similarly, the bits of the register 6 in the group of 22 inputs write the units corresponding to the list Y0 Switches 3 and 4 are configured to output components of the elements of the sets A and B in accordance with lists X and Y.

Decoder 8 analyzes the number of units in register 5. If register 5 contains a code containing m units, a signal appears at the m-th output of the decoder 8. This signal, via the OR 9 elements, goes to the enable inputs of comparison blocks 10 of the first by ha th Consequently, the results of the comparison of the components of the elements of the sets A and B are taken into account.

In the initial state, the counters 11 and 12 contain information related to the previous comparison of some two sets (with the power supply the previous one will be some kind of dummy comparison). The result of the previous comparison is blocking the supply of clock pulses from the input 25 of the device.

Starting the device is accomplished by applying a signal to the input 23 of the device. On this signal, the contents of counters 11 and 12 become equal to one. Blocks 1 and 2 of memory produce at their outputs the first elements of sets A and B. From the output of counter 11. The signal arrives at the first control input of the included comparison units 10. The components of the elements selected by the switches 3 and 4 are checked by the comparison units 10 for the first comparison operation.

If the comparison criterion is satisfied, then a single signal from the output

At the outputs of the following. The blocks of the HE element 14 do not enter the third input of the element AND 17, the first input of which is supplied with a single signal from the output of the element NOT 15 (since the elements of the sets are not the last). The clock pulse received from the input 25 of the device increases the value of the counter 12 by one unit of blocks 1 and 2, and the elements of the sets A and B of the lower 10 appear to compare them. If the comparison criterion is met, the next clock pulse increases the value of the counter 12 by one more. The following elements of the sets are compared, and so on, while the outputs of blocks 1 and 2 do not match the components of the last elements of the sets. A single signal from the output of block 2 blocks the increment of the counter value 12 "In case of successful comparison of the last elements of set A and B, single inputs of the element 20 receive single signals from the control outputs of blocks 1 and 2 (delay element 19 compensates for transient time during comparison) . When the signal arrives at the control input of the encoder 7, the latter outputs at code 24 a code corresponding to the ratio found.

5610746

If, for any comparison, the comparison criterion is not fulfilled, then a single signal from the output of the element

with OR 13 will assign the contents of the counter 12 a value equal to one. In addition, the signal from the output of the element OR 13 is fed to the second input of the element And 16. The incoming sync pulse 10 increases by one

the value of counter 11, the elements of the sets A and B are compared, starting again from the first elements, to the execution, of the following comparison operation.

15 Further operation of the device is similar to that described. The search finally determines the relation for which the comparison operation is performed for all elements of the sets A and B.

20 The comparison operation code is fed to the input of the device. Let there be two sets, the relationship between which must be determined. Solving this problem requires applying the following

25 algorithms: selection of comparison operation; submission to the information inputs of the first element set comparators; comparison of elements of sets; if the comparison criterion is not met,

30 then the transition to claim 1; if the elements of the sets are the last, then go to step 8; submission to the information inputs of the comparators of the following elements of the multi

0

five

0

Steps to p.Z; issuing a comparison operation code.

Claims (1)

Invention Formula A device for determining the set ratio containing the first and second switches, the first and second attribute registers, n comparison blocks, the output OR element, the NOT element, a group of n OR elements, the decoder, and the information inputs of the first and second attribute registers are the inputs of the first and second device characteristics, and the outputs are connected to the control inputs of the first and second switches, respectively, 1st, where i 1, ..., n, n is the number of relations of the output group of the first and second switches connected to the first the second group, the pami inputs of the 1st comparison block, the output of which is connected to the corresponding input of the output element OR, the output of which is connected to the input of the element NOT, the outputs of the first register) signs are connected to the inputs of the decoder, j-th (jf, 2 ,,. ., n-1), the output of which is connected to the inputs of the OR elements of the first through jth groups, and (j + O of the decoder's output is connected to the comparison resolution input of the nth comparison block, the output of the j-ro element of the OR group is connected with the comparison resolution input j-ro comparison block, ke control inputs (Tc 1, 2.0.6) of all the blocks Neither are combined, characterized in that, in order to expand the scope of application due to the possibility of comparing all the corresponding elements of two sets, the first and second memory blocks, the encoder, the first and second counters, the first, second and third elements AND, the second element are entered into it. NOT, the OR element of the initial installation, the delay element, with the 1st group of outputs of the first and second memory blocks connected to the i-th groups. the information inputs of the first and second switches, respectively, the output of the k-ro bit of the first counter is connected to the k-th control inputs of the comparison blocks, and the k-th input of the encoder, the control input of which is connected to the output of the first element five 0 five 0 This AND, the first input of which is connected via the delay element to the zero-bit output of the first mA block, and the second input is connected to the zero-bit output of the second memory block and through the second element to the first input of the second AND element, the output of which is connected to the counting the input of the second counter, the installation input in the unit state of which is connected to the output of the OR element of the initial installation, and the output bits of the second counter are connected to the address inputs of the first and second memory blocks, the clock input of the device is connected to the second the input of the second element AND and the first input of the third element AND, the second input of which is connected to the output of the output element OR, and to the first input of the element OR of the initial installation, the second input of which is connected to the input of the installation in the unit state of the first counter and the device start input, the third input the second element AND is connected to the output of the first element NOT; the output of the encoder is the output of the device relation found. Editor N. Gorvat Compiled by V. Kozlov Tehred L.Olninyk Proofreader N. King Order 977 Circulation 568 VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, Raushsk nab. 4/5 Subscription