SU1254475A1 - Device for transforming coordinates - Google Patents

Abstract

The invention can be applied in specialized computers in processing, measuring and transforming the coordinates of a vector. The device reduces the cost of equipment. The proposed device proposes an algorithm for processing the iterative transformation expressions, which consists in rotating the vector in the first quadrant of the plane. As a result, the memory capacity is reduced by a factor of 8. The device for coordinate transformation contains the first and second multiplexers, the first, second and third registers, the counter, the memory block of the iteration constants, the first and second shifters, the first and second adders, the control unit, the inputs of the abscissa and ordinates of the device, the angle of rotation of the device , the abscissa and ordinate outputs of the resulting vector, the launch input. By introducing a new algorithm for processing sign bits, the control unit was able to significantly reduce the amount of memory of the iteration constants. 4 ill., I table. i (L C to ate 11 vj 01

Description

one

The invention relates to computational and can be used in specialized devices of coordinate transformations.

The aim of the invention is to reduce equipment by eliminating the need to store source data with sign bits.

Figure 1 shows the functional diagram of the device; 2 is the same as the control unit; on fig.Z - the same, the block of the analysis of signs; Fig. 4 shows conversion diagrams. vector.

The device contains the first 1 and second 2 multiplexers, the first 3, the second 4 and the third 5 registers, counter 6, memory block 7 of the iteration constants,. the first 8 and second 9 shifters, the first 10 and second 11 adders, control unit 12, inputs 13 of the abscissa and 14 ordinates of the device, input 15 of the angle of rotation of the device, outputs 16 of the abscissa and 17 ordinates of the resulting vector of the device, input 18 of the start of the device, driver 19 pulses, first 20, second 21 and third 22 shift registers, first 23, second 24 and third 25 triggers, pulse generator 26, character analysis unit 27, first 28, second 29, third 30, fourth 31, fifth 32,. the sixth 33 elements AND, the first 34, the second 35 elements OR, the inputs 36 of the mode setting feature, 37 the sign of the magnitude of the abscissa sign, 38 sign of the correction, 39 sign of the magnitude of the sign of the ordinate of the device, the outputs 40 of the sign of the change of the abscissa and ordinate, -41 abscissa transformations, 42 resets, 43 receptions, 44 ordinate conversions, 45 clocks, 46 controls for entering the angle code, 47 controls a memory block of iteration constants, 48 shifts, 49 clocks, 50 shift amounts, 51 loop controls. The character analysis block contains the first 52, the second 53 the third 54, the fourth 55, the fifth 56, the sixth 57 T riggers, the first 58, the second 59, the third 60, the fourth 61, n / i-the second 62, the sixth 63 multiplexers, the decoder 64 , the first 65, the second 66, the third 67, the fourth 68 elements AND, the first output 69 of the decoder, the first 70, the second 71 elements OR, the element EXCLUSIVE OR 72, the first 73, the second 74, the third 75 clock inputs.

15

544752

the outputs of signs are 76 abscissas and 77 ordinates.

The device operates as follows.

5 The computational process is an iterative transformation of coordinates, described in detail in the prototype. Its implementation uses a functional constant table 0 of the form

kj X. cos tf; - In sin (f.;

 (one)

, kij cosqij + X- sinCfj,

which are selected from a memory at a cumulative address made up of x-coordinate codes; and y-, the segment code of the angle tp and the cycle number j.

In the proposed device, such an organization of the computational process is used, which allows to exclude sign bits during the formation of the functional table, then the volume of the table is reduced by a factor of 8 to 5. Source data marks are otherwise accounted for.

Codes of coordinates of the vector and the code of the angle of rotation in the general case are presented in an additional form. The coordinates x, y are input to the adders 10.11, where, depending on the sign, the conversion is carried out into a direct form, the values of the sign bits being fixed in the control unit 12. The angle code is entered into the angle register 5, and if 5 is represented in an additional form, then it is not translated into a direct form. As a result of turning the vector on

additional angle (- - tf) the resulting vector is connected by simple relations with the desired vector

X Uko; y-X) (aa o, Consider the process of rotating the desired vector R, located in the fourth quadrant, by a negative angle tp, while it must take a position R. However, since the rotation will be made by an additional angle, then the vector will take the position Translation of the coordinate codes from the additional form to the direct one will translate the vector RKQ to the position K. Now it is necessary that the vector R

5 before the start of rotation, it occupies the same position relative to the OY axis, which is occupied by the initial vector relative to the OX axis. This can be done by entering

0

3

-In the action of a new vector operation, which we call the change. The essence of this operation is for a given vector in finding some vector symmetric with respect to the bisector of the coordinate angle. It should be noted that the Change operation is performed when the source vector is transferred to the first quadrant of the 2nd and 4th quadrants, i.e. with a negative value of the product of the signs of the coordinates (sign x; sign y. 1) of the original vector. After performing the Change operation, the vector takes the R position and the process of transformation (rotation) begins in the positive direction. In the process of vector rotation, the vector can go beyond the 1st quadrant, therefore, after performing the next conversion cycle, the signs of the coordinates are checked and, if the vector comes out, it returns the Tth quadrant by transferring the corresponding coordinates and then undergoes operation Turn. The conversion continues.

Translations of the original and then about the inter-vector vectors, as well as the execution of the Change operation, should be remembered, since this information will allow you to obtain the coordinates of the desired one using the coordinates of the resulting vector. The execution of the Change operation is taken into account by summing their total modulo 2 P. As for fixing the signs of coordinates, the order of fixation is directly dependent on the current value of P, in particular at P 0, the signs of the coordinates are fixed according to their belonging, i.e. the sign of the x coordinate is stored in some storage element intended for the X coordinate; with P 1, the signs of the coordinates are fixed in the reverse belonging, i.e. the sign of the x coordinate is stored in the memory element intended for the coordinate ij, and the sign of the coordinate tj is respectively in the element x. Assuming that the Change operation was used after the source vector was converted to the 1st quadrant, and also after the second cycle was completed, the resulting coordinate coordinates are formed as follows:

544754

sign x.sign y ,. sign y, sign X - ...

PE

sign Ud. sign x ,. sign j sign OUSE ...

The formation of these products of characters is well replaced by a logical operation modulo 2 summation, if one accepts that (-) - and 10 (-f).

After the end of the last (M-1) -th computational cycle of the transformation, the resulting vector RJ will be obtained, according to the coordinates of which using the generated values

sign X, sign y P, as well as the sign of the angle code signCf are the coordinates of the desired vector R.

Thus, after recording the initial 20 X, 1 | in adders 10.11, the translation of the corresponding direct-contained content and the fixation of characters in the control device determines the value of P, which controls the multiplexers 1 and 2, so that when P O (no Change operation), the contents of adders 10.11 are sent registers 3 and 4 shift, and when P 1 (performed

30 operations Change) - vice versa in 4 and 3. Adders 10.11 are zeroed.

Now begins the usual process of transformation in accordance with the algorithm of the table-iterative transformation of coordinates. The input of memory block 7 of the iteration constants receives the highest p-bit segments of the coordinate codes X and tj from registers 3 and 4, the leading t-bit segment, the code of the angle 0 Cf from register 5, and also the contents of the counter 6 cycles. The mentioned code segments form a set which is the address by which from block 7 of the memory of iteration constants

5, constants of the form (1) are read. These constants without shift, since the zero clock is executed, are sent through the shifters 8 and 9 to the adders 10 and 11. This completes the zero stroke. In the following, the first clock cycle, the contents of registers 3 and 4 are shifted by p bits to the left and the code segments follow into the places of the older ones, which is equivalent to increasing them by 5 times. At this address, constants are read from the block of iterative memory constants, which are now shifted by shifters 8 and 9

f bits to the right, and then go to adders 10 and 11, where they are added to the results of the previous clock cycle. Shifters 8 and 9 in the 1st cycle shift the constants by ip ra: views to the right. After processing the last (p - 1) -th segments of the coordinate codes, the henna ends (p - 1) -th clock and the next computational cycle.

After the end of the zero cycle in the adders 10 and 11, the coordinates of the intermediate vector obtained by rotating the original vector by the angle corresponding to the highest (zero) segment of the angle code cp, will be formed. After each cycle, an analysis of the signs of the intermediate vector coordinates is carried out, their fixation, transfer, if necessary, to the direct code, calculating the value and sending the content adders 10 and 11 to registers 3 and 4, according to its value, from registers 3 and 4. five

ten

15

20

the completion of computational tact,

and shift register 22 controls shift

tel 8 and 9.

Consider the operation of the control unit 12 in conjunction with the operating part of the proposed device.

The trigger signal on bus 18 excites the pulse shaper 19, generating a single pulse, which has the following actions: starting on setting the registers 20-22 of the shift in the high bits of which is recorded from one; writing to the adders 10 and 11 of the coordinate codes applied to the buses 13 and 14, and writing to the register 5 the angle of the code of the angle qi through the input 13 of the device, setting the triggers 23 and 24 to a single position.

The signal from the single output of the first trigger 23 lowers the generator 26 of pulses, the pulses from the output of which, resolved by the signal from the single output of the trigger 24, the AND 28 logic element arrive at synchronization to the input of the counter for 6 cycles and delivers the 25th input of the shift register 20. TO

The signal by which the register is shifted by m bits to the left, the next segment of the angle code is entered into processing, and also the contents of the counter are 6 cycles by 1. The contents 30 of the counter determine the number of the current cycle, the memory area in which the function table is stored, used in this cycle.

Starting from this moment, the next conversion cycle is executed. As a result of the execution of the last (M-1) -th cycle in the adders 10 and 11, the coordinates of the resulting vector will be formed. Using the accumulated information about the values of f, sign X, sign y, as well as the value of the sign bit of the angle code sign s, the control unit 12 translates the coordinates of the resulting vector into the appropriate form and sends them by direct or cross-linking implemented by multiplexers 1 and 2, in registers 3 and 4 coordinates. Registers 3 and 4 will contain 1 coordinates of the desired vector R. The control block & 12 is implemented on shift registers 20-22, with register 20 pre-processing the coordinate codes, the results of the 55 cycle and the translation of the coordinates of the resulting vector into the coordinates of the desired one. Shift register 21 controls jag

45

50

at the moment of arrival of the first pulse from the generator, a single signal from the first output of the register 20 acts on the block 27 of character analysis of the record, the current values of the signs of the coordinates, received through inputs 37 and 39 from the sign bits of the adders 10 and 1 Generator pulses 26 entering the clock input of the register 20, shift the units sequentially to the second, third, and so on. bits The pulses from the second and third outputs of register 20, just like the first impulse, organize the operation of the block 27 of analysis. Signs. At the outputs of the block 27 for analyzing the signs at the time of the appearance of a pulse from the fourth output of the register 20, the signals sign X ;, sign Y; and P, the first two signals through logic gates And 31 and 32, allowed by the fourth pulse, arrive at adders 10 and 11, if necessary, transfer the coordinate codes to a direct form. The signal P controls the position of the multiplexers 1 and 2, with which the P operation is executed. The impulse from the fifth exit at exit 49 records the contents of the adders in registers of the 3 and 4 coordinates. On the falling edge of the last sixth pulse, adders, trigger 24, are reset via output 4.

the completion of computational tact,

and shift register 22 controls shifters 8 and 9.

Consider the operation of the control unit 12 in conjunction with the operating part of the proposed device.

The trigger signal on bus 18 excites the pulse shaper 19, which generates a single pulse, which has the following actions: initial setting of shift registers 20-22, in the high-order bits of which the unit is written; writing to adders 10 and 11 of the coordinate codes applied to the buses 13 and 14, and writing to the register 5 of the angle code of the angle qi through the input 13 of the device; installation of flip-flops 23 and 24 in a single position.

The signal from the single output of the first trigger 23 lowers the generator 26 of pulses, the pulses from the output of which are allowed by the signal from the single output of the trigger 24 logic element And 28 arrive at the synchronizing input of the shift register 20. TO

at the moment of arrival of the first pulse from the generator, a single signal from the first output of register 20 affects the block 27 of the character analysis of the record, the current values of the coordinate signs received through inputs 37 and 39 from the sign bits of the adders 10 and 11. The generator 26 pulses arrive at the synchronizing input of the register 20, shift the units sequentially to the second, third, and so on. bits The pulses from the second and third outputs of the register 20 in the same way as the first impulse organize the operation of the block 27 of analysis. Signs. At the outputs of the block 27 for analyzing the signs at the time of the appearance of a pulse from the fourth output of the register 20, the signals sign X ;, sign Y; and P, the first two signals through logic gates And 31 and 32, allowed by the fourth pulse, arrive at adders 10 and 11, having converted the codes of the coordinates into a direct form, if necessary. The signal P controls the position of multiplexers 1 and 2, with which the change operation is performed. The impulse from the fifth exit at exit 49 records the contents of the adders in registers of the 3 and 4 coordinates. On the falling edge of the last sixth pulse, adders, trigger 24, are reset through output 42.

is set to the zero position (a cyclic shift of the register is carried out, with a unit of the sixth power going to the first, and the preliminary processing, the x and y coordinates, ends.

The next stage is the execution of measures.

Since the trigger 24 is in the zero position, the signal from its zero output resolves the AND 29 gate, and now the pulses from the generator arrive at the clock input of the third shift register 22. The signal from the second output does not pass through the prohibited element And 30, and the shift of the registers 3 and 4 does not occur in the zero cycle. The signal from the third output establishes - the trigger 25, a high level from a single 20 output of which on output 47 permits reading of the iteration constants from memory block 7. Shift register 21 is designed to set the shifters 8 and 9. The first output of the 25 shift shift register 21 sets the shiftrs 8 and 9 to the mode when the constants read from the memory without shifting pass to the input of the adders, the signals from each The subsequent output of the register 21 increases the shift by r bits. The signal from the fifth output of register 22 on output 45 controls the summation of the constants read from memory 7 in adders 10 and 11. On the falling edge of the sixth output, the trigger 25 is reset, the register 21 is shifted and the register 22 is cycled , at which the unit of the sixth bit falls into the first bit of the register 22.. The next tact begins.

A single signal from the second output of the register 21 to the output 50 sets the shifters 8 and 9 into modes in which they shift the constants by p bits to the right, at the same time the same signal through the logical element OR resolves the AND 30 element through which the signal from the second output register 22 passes to output 48 and shifts registers 3 and 4 coordinates by p bits to the left. In the following, the implementation procedure is also repeated. The read and shifted constants are summed with the contents of adders 10 and 11, Register 21

shifts one more position to the right, etc. After the last clock cycle has been completed, the pulse from the p-th output of the register 21 is cyclically rewritten to the first bit, the falling edge of this pulse is applied through the logic element OR 34 to set the trigger 24, and also to the output 51, shift the angle register 5 by m bits left and increase counter 6 cycles per unit.

Control unit 12 proceeds to processing the cycle results. The pulses from the generator 26 through the allowed logical element AND 28 are fed to the register 20, which processes the results of the cycle, similarly to the processing of the initial data. The described work order is repeated until the end of the last (M-1) -th cycle, when the contents of counter 6 cyclo.v become equal to (M-1), in this case, the signal from the output of the counter on input 36 goes to control unit 12, where resolves the logical element AND 39 and initiates the block 27 of character analysis for processing the conversion results in order to determine the coordinates of the desired vector. This processing is carried out under the control of register 20 and, after its completion, the signal from the sixth output of register 20, through element 33, clears trigger 23, which in turn blocks the pulse generator 26. Conversion complete. The desired vector is in registers 3 and 4 coordinates,

Let us now consider the operation of the block 27 of the analysis of signs, in which two modes can be distinguished: the processing of the initial and intermediate vectors and the processing of the resulting vector. These modes set the signals from the counter 6 cycles.

The zero signal level from the cycle counter determines the first processing mode. The signs of adders 10 and 11 on inputs 37 and 39 arrive at the inputs of flip-flops 52 and 53, where they are fixed by the signal from the first output of register 20 of the shift at input 73, Signals from the single outputs of flip-flops 52 and 53 through multiplexers 60 and 61 arrive at outputs 76 and 77, At the same time, the same signals are fed to the inputs of multiplexers 58 and 59, with the help of which the Change of characters operation is performed if necessary. Since all the tripers in the initial state are zeroed, the absence of a signal from the trigger 56, intended to form the value of the sign P, is set to a multiplexer 58 and 59.v forward mode transmission. The signal about the second output of the register 20 shift on the input 74 resolves the logic elements And 65 and 66, through which from the outputs of the multiplexers 58 and 59 arrive at the synchronous inputs of the flip-flops 55 and 54, designed to form the values of sign x and sign y. At the same time, the same signals are fed to the input of an EXCLUSIVE OR 72 logical element, which forms the product sign x sign Y (, the output signal goes to the counting input of the trigger 56. Signal; in the mode in question, the third output of the shift register 20 does not affect Pizov signs, since it is forbidden by zero According to the results of the analysis of the wasps and ij, we define P and Cp, which determine the final value of P and the need for changing signs. Filling of the graphs Pr and Cp was performed as follows. rock one is present

name coordinate, i.e. If there is no need to make a change, the column P is set to the value 0. The value zero in the column Cp is put in cases when the coordinates are of the same name. The comparison of the sign column (f and the angle indicator display column (sign q 1) is reversed by sign x. Thus, the combination of the values of P and sign (p must be converted into the corresponding combinations of Pr, cf. Such a conversion is performed on the base

output signal from the counter 6 cycles. In this mode, the current values of sign X are applied to the outputs of the character analysis block; , sign Y; and the value of T, which determines the necessity of converting the coordinate codes to a direct form and performing the operation Change. When processing the results of the cycles, the character analysis block 27 performs the actions, and in the triggers 55,54 and 56, the values sign, sign y and P are formed, which will be used in processing the resulting vector.

In the second retkim, the sign analysis unit 27 should form such values sign X, sign y C n, using which one could find the coordinates of the desired vector.

The values of ti and for various values of P, sign Cf are presented in the table.

decoder 64, to the input of which signcf values are fed through input 38 and P from trigger output 56. Analysis of graphs P and Pr shows that only in the second and fourth combination does P change to the opposite, therefore we connect the second output of the decoder 64 to the trigger input 56 , and the fourth output, respectively, with the reset input. Signs sign and sign are changed by multiplexers 62 and 63, which can be controlled by the third or fourth outputs of the decoder 64, connected by an OR 70 gate.

After the completion of the last (M-1) -th cycle, the value of the counter 6 of the cycle becomes equal to M-1 and a single sig appears at its output

111

It arrives at the control unit 12, and in particular, in which this signal inhibits the AND 65 and 66 logic elements, arrives at one of the inputs of the AND 68 logic element, resolves the AND 67 element and sets the multiplexers 60 and 61 to which, at their outputs, pass the values of the sign x and sign y formed during the conversion. The processing of the resultant vector E is performed by the first shift register 20. The pulses from the first and second outputs of the register entering the character analysis unit 27 do not lead to any actions. The signal from the third output register 20 enters input 75 to one of the inputs of the And 68 element and, if sign q q 1, then this logic element triggers a pulse, which triggers trigger 55, i.e. changes sign of sign x to opposite. The signal from input 75 also passes through the allowed element I 68 to the decoder 64, initiating its operation. The fourth pulse from the output of the register 20 permits the conversion of the codes into the appropriate form, the fifth pulse performs the overwriting of the contents of the adders 10 and 11 into registers 3 and 4, the sixth pulse blocks the generator 26, and the conversion is completed.

Formula of the invention

A device for converting coordinates that contains three triggers, two shifters, two adder a, a memory block of iteration constants and a control unit containing a pulse generator, a pulse shaper, a trigger, three AND elements and an OR element, the outputs of the multiplication factor of the control unit are connected to the control input inputs of the first and second shifters, the information inputs of which are connected respectively to the first and second outputs of the memory block of the iteration constants, the outputs of the first and second shifters are connected, to the first bubbled data inputs of the first and second adders, the reset inputs receiving timing are connected -c adders control group control unit outputs, which control register outputs are connected

j y 15 20 25 30

five

0

five

0

five

7512

with the synchronization inputs of the first and second registers, the input of the recording of the third с register is connected to the input of the rotation angle of the device, characterized in that, in order to reduce the equipment by eliminating the need to store the original data with significant bits,

it additionally includes two multiplexers and a counter, and the control unit contains three shift registers, two triggers, three AND elements, an OR element and a character analysis unit, with the first information inputs of the first and second multiplexers connected to the bits of the first adder, the second information inputs of the first and the second multiplexers are connected to the outputs of the bits of the second adder, the outputs of the sign bits of the first and second adders are connected to the "inputs of the values of characters, respectively, the abscissas and ordinates of the control unit laziness, the output of the attribute of abscissa change and ordinate of which is connected to control one input of the first and second multiplexers, the outputs of which are connected to the information inputs of the first and second registers, respectively, the bit outputs of which are the outputs of the resulting vector of the device, respectively The first, second, and third registers of the registers are connected to the first, second, and third address blocks of the memory of the iteration constants, respectively; connected to the memory control output of the iterative constants of the control unit, the loop control output of which is connected to the counting input of the counter and the shift input

the second register, the output of which the bit of which is connected to the input of the indicator of the correction of the vector of the control unit, the input of the mode setting of which is connected to the output of the higher discharge of the counter, the outputs of the bits of which are connected to the fourth input of the memory block of the iteration constants, the second information inputs of the first and second Cy1 "{mators are connected respectively to the inputs of the abscissa and ordinates of the device, and the device start input is connected to the same input of the control unit, which is the driver start input

31

pulses, the output of which is connected to the installation input of the first trigger of the control unit and the first input of the first element OR of the control unit, the output of the first trigger of the control unit is connected to the trigger input of the pulse generator, the output of which is connected to the first inputs of the first and second elements And the control unit whose outputs are connected to the synchronizing inputs of the first and second shift registers, respectively; the second inputs of the first and second elements of the control unit are connected respectively to the direct and inverse you The signals of the second trigger of the control unit, the installation and reset inputs of which are connected respectively to the output of the first element OR of the control unit and the output of the low-order bit of the first shift register, the outputs of the first bits of the first, second and third shift registers are connected to the inputs of the higher bits of these registers , the write inputs to the senior section of the first, second, and third shift registers are connected to the bus of the logical unit, the strobe inputs for recording the initial values of the first, second, and third registers are connected pulse shaper output, the second input of the first OR gate control unit connected to the output the least significant bit of the shift register and the output of the control cycles of the control unit, the outputs starpshh bits of the second shift register connected to the outputs of the shift control unit outputs bits

from the second to p-1 (p is the number of cycles) is connected to the inputs of the second OR element of the control unit, the output of which is connected to the first input of the third element AND of the control unit, the output of which is connected to the shift output of the group of register control outputs of the control unit, the second input of the third the control unit AND element is connected to the output of the second bit of the third shift register; the outputs of the third and lower bits of the third shift register are connected to the inputs of the installation and reset of the third trigger of the control block, respectively; th bit of the third register of the shift is connected to the synchronizing input of the second shift register, the rise of the third trigger block

:.

5 10 15 20 5 0 5

0

five

7.514

control is connected to the control output of the memory block of the iterative constants of the control block, the output control of the input of the angle code of which is connected to the output of the pulse generator and the output of the group of outputs of the control adders, the output of the fifth bit of the third shift register is connected to the output of the clock group of the outputs of the control adders, the input the reset of which is connected to the low-order output of the first shift register, the outputs of the abscissa transformation and the ordinates of the group of control outputs of the adders of the control unit Connected with the outputs, respectively, of the fourth and fifth elements AND the control unit, the first inputs of which are connected to the outputs of the values of the characters, respectively, the abscissas and ordinates of the character analysis unit, the output of the sign of the change of the abscissa and ordinates of which are connected to the same output of the control unit, the first, second and third clock inputs The unit for analyzing signs is connected to the outputs of the first, second and third bits of the first

the shift register, the output of the fourth bit of which is connected to the second inputs of the fourth and fifth elements And the control unit, the output of the fifth bit of the first shift register is connected to the write output of the group of control outputs of the control unit registers, the low-order output of the first shift register is connected to the first the input of the sixth element I, the second input of which is connected to the input of the indication of the setting of the mode of the control unit, which is the same input of the character analysis block, the inputs of the values of the digit bits of the abscissa and ordinate and characteristic correction control unit are homonymous input characters analysis unit, the analysis unit characters comprises six flip-flops, six multiplexers,

 the decoder, the even element And, the two elements OR and the element EXCLUSIVE OR, the inputs of the values of the abscissa characters and the ordinates of the character analysis block are connected to the information inputs of the first and second triggers of the character analysis block, the synchronization inputs of which are connected to the first clock input of the character analysis block, the output of the first block trigger

Sign analysis is connected to the first information inputs of the first, second, and third multiplexers of the character analysis unit, the output of the second trigger of which is connected to the first information input of the fourth multiplexer and the second information inputs of the first and second multiplexers of the character analysis block, the outputs of the first and second multi-third clock input of this unit

the plexors of the character analysis block are connected to the first inputs of the first and second elements AND the character analysis block, the second and third inverse inputs of which are connected to the second clock input and the input of the sign of setting the character analysis block mode, respectively, and the outputs of the first and second elements are respectively the first and second inputs of the EXCLUSIVE OR element, the outputs of the first and second elements AND the character analysis block are connected respectively to the first input of the first OR element and the counting input of the third the second trigger of the character analysis block, the output of the first OR element of which is connected to the counting input of the fourth trigger of the character analysis block, the output of the third trigger of which is connected to the first information inputs of the fifth and sixth multiplexers of the character analysis block whose second inputs of the fifth and sixth multiplexers are connected to the output the fourth trigger of the character analysis block, the outputs of the fifth and sixth multiplexers of which are connected to the second information inputs of the third and fourth, respectively th multiplexers characters analysis unit whose outputs are the outputs of the sign of the abscissa and ordinate, respectively.

the control inputs of the third and fourth multiplexers of the character analysis block are connected to the mode setting input of the block, with the first inputs of the third and fourth elements of the character analysis block, the second input of the third element and the character analysis block are connected to the second input of the fourth element and the character analysis block and

the input of the sign of the correction of which vector is connected to the third input of the fourth element AND the character analysis unit, the output of the fourth element AND is connected to the second input of the first element OR of the character analysis unit, the output of the third element AND the character analysis unit is connected to the enable input of the decoder, the first input of which is connected to the input of the characteristic of the control unit vector correction, the second input of the decoder is connected to the output of the fifth trigger of the character analysis block and the control inputs of the first and second multiplexers the second block, the second and fourth outputs of the decoder are connected respectively to the installation and reset inputs of the fifth trigger of the data analysis block; the trigger input is connected

with the output of the EXCLUSIVE OR element, the output of the 5th trigger of the character analysis block is connected to the output of the abscissa and ordinate reversal feature, the third and fourth decoder outputs are connected, to the inputs of the second OR element of the character analysis block, the output of the second OR element of this block is connected to the input installation of the sixth trigger, the direct output of which is connected to the control inputs of the fifth and sixth multiplexers of the character analysis unit.

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Compiled by S.Kulikov

Editor N.Slobod nickname Tehred L. Serdyukova Proofreader V. But ha

Order 4721/52 Circulation 671 Subscription

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., d. A / 5

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Claims (1)

Claim A coordinate conversion device comprising three triggers, two shifters, two adders, an iteration constant memory block and a control unit comprising a pulse generator, a pulse shaper, a trigger, three AND elements and an OR element, the outputs of the multiplication coefficient of the control unit being connected to control inputs of the first and second shifters, the information inputs of which are connected respectively with the first and second outputs of the memory block of iterative constants, the outputs of the first and second shifters are connected. with the first information inputs of the first and second adders, respectively, reset, receive inputs, clocking of which are connected. a group of control outputs of the adders of the control unit, the control outputs of the registers of which are connected to the synchronizing inputs of the first and second registers, the input of the recording of the third register is connected to the input of the angle of rotation of the device, characterized in that, in order to reduce equipment by eliminating the need to store the original data (x sign digits, in the digits of the second sign digits of the adders of the connected two additional multiplexers and a counter are introduced, and the control unit contains three shift registers, two a trigger, three AND elements, an OR element, and a character analysis unit, the first information inputs of the first and second multiplexers connected to the outputs of the bits of the first adder, the second information inputs of the first and second multiplexers connected to the outputs of the adder, the outputs of the first and second ones with “inputs of sign values respectively, the abscissas and ordinates of the control unit, the output of the sign of changing the abscissas and ordinates of which are connected to the control inputs of the first and second multiplexers, the outputs of which are connected to information the inputs of the first and second registers, respectively, whose outputs are the outputs of the abscissas and ordinates of the resulting device vector, the high-order outputs of the first, second, and third registers are connected respectively to the first, second, and third address inputs of the memory block of iterative constants, the selection resolution input of which is connected with the control output of the memory unit of the iteration constants of the control unit, the loop control output of which is connected to the counting input of the counter and the input the shift of the third register, the output of the character series of which is connected to the input: for the correction of the vector of the control unit, the input of the mode setting of which is connected to the output of the highest bit of the counter, the outputs of the bits of which are connected to the fourth input of the memory block of iterative constants, the second information inputs of the first and second adders are connected respectively with the inputs of the abscissa and the ordinate of the device, and the input of the start of the device is connected to the input of the control unit of the same name, which is the start input of the shaper p zprz1 3 pulses, the output of which is connected to the installation input of the first trigger of the control unit and the first input of the first OR element of the control unit, the output of the first trigger of the control unit 5 is connected to the start input of the pulse generator, the output of which is connected to the first inputs of the first and second elements AND of the control unit, the outputs of which are connected to the synchronous 10 inputs of the first and second shift registers, respectively, the second inputs of the first and second elements AND of the control unit are connected respectively to direct and With a total of 15 outputs of the second trigger of the control unit, the installation and reset inputs of which are connected respectively to the output of the first OR element of the control unit and the output of the least significant bit. 20. to the first shift register, the outputs of the ί-least significant bits of the first, second and third shift registers are connected to the inputs of the senior bits of these registers, the entries in the high order 25 row of the first, second and third shift registers are connected to the bus of the logical unit, the gating inputs of the record of the initial values of the first, second and third registers 30 connected to the output of the pulse shaper, the second input of the first OR element of the control unit is connected to the output of the least significant bit of the shift register and the control output of the cycles 35 of the control unit, the outputs of the highest bits of the second shift register are connected to the outputs of the shift value of the control unit, the outputs of the bits from second to p-1 (p is the number of clock cycles) 40 are connected to the inputs of the second OR element of the control unit, the output of which is connected to the first input of the third element AND of the control unit, the output of which is connected to the shift output of the group of outputs s control registers of the control unit, the second input of the third element AND of the control unit is connected to the output of the second bit of the third shift register, the outputs of the third and least significant bits of the third shift register are connected to the inputs of the installation and reset of the third trigger of the control unit, the low-order output of the third shift register is connected to by the synchronizing input of the second shift register, the output of the third trigger of the control unit is connected to the control output of the memory unit of the iteration constants of the control unit I, the control output of the input of the angle code of which is connected to the output of the pulse former and the reception output of the group of outputs for controlling the adders, the output of the fifth bit of the third shift register is connected to the clock output of the group of outputs of the control of adders, the reset input of which is connected to the output of the least significant bit of the first shift register, the conversion outputs abscissas and ordinates of the group of control outputs by adders of the control unit are connected to the outputs of the fourth and fifth elements AND of the control unit, respectively, the first inputs which are connected to the outputs of the sign values, respectively, the abscissas and ordinates of the sign analysis unit, the output of the sign of the change of abscissas and ordinates of which is connected to the same output of the control unit, the first, second, and third clock inputs of the sign analysis unit are connected to the outputs of the first, second, and third bits of the first the shift register, the fourth discharge of which is connected to the second inputs of the fourth and fifth elements AND of the control unit, the fifth output of the first shift register is connected to the output om records of the group of outputs of the control of the registers of the control unit, the low-order output of the first shift register is connected to the first input of the sixth element And, the second input of which is connected to the input of the setting sign of the control unit mode, which is the input of the sign analysis unit of the same name, the inputs of the sign digits of the abscissa and ordinate and the input of the sign of correction of the control unit are the same inputs of the character analysis unit, and the character analysis unit contains six triggers, six multiplexers, a decoder, even lementa And, two OR gates and an exclusive OR, and inputs the values of abscissa and ordinate marks Marks analysis unit connected to the data inputs of the first and second analysis unit triggers marks, clock inputs of which are connected to a first input of the timing marks analysis unit, an output of the first trigger unit 1 6 character analysis is connected to the first information inputs of the first, second and third multiplexers of the character analysis unit, the output of the second trigger of which is connected to the first information input of the fourth multiplexer and to the second information inputs of the first and second multiplexers of the sign analysis unit, the outputs of the first and second multi 1 about the plexors of the sign analysis unit are connected to the first inputs of the first and second elements AND of the sign analysis unit, the second and third inverse inputs of which are connected respectively with the second clock input and the input of the sign of specifying the mode of the character analysis unit, the outputs of the first and second elements AND of which are connected respectively to the first 20 and second inputs of the EXCLUSIVE OR element, the outputs of the first and second elements AND of the character analysis unit are connected respectively to the first input of the first element OR and a counting 25 input of the third trigger of the character analysis unit, the output of the first OR element of which is connected to the counting input of the fourth trigger of the character analysis unit, the output of the third trigger of which is connected with the first information inputs of the fifth and sixth multiplexers of the character analysis unit, the second information inputs of the fifth and sixth multiplexers of which _{33 are} connected to the output of the fourth trigger of the character analysis unit, the outputs of the fifth and sixth multiplexers of which are connected to the second information inputs of the third and fourth multiplexers of the character analysis unit, the outputs of which are the outputs of the magnitudes of the signs, respectively, the abscissas and ordinates, the control inputs of the third and fourth multiplexers bl the character analysis windows are connected to the input of the job mode of this block, with the first inputs of the third and fourth elements And the character analysis unit, the second input of the third element And the character analysis unit is connected to the second input of the fourth element And the character analysis unit and with the third clock input of this block, the input of the vector adjustment flag of which is connected to the third input of the fourth element AND of the character analysis unit, the output of the fourth element And 15 is connected to the second input of the first element OR of the character analysis unit, the output of the third AND element the character analysis lock is connected to the decoder operation enable input, the first input of which is connected to the input of the correction sign of the control unit vector, the second decoder input is connected to the output of the fifth trigger of the character analysis unit and the control inputs of the first and second multiplexers of this block, the second and fourth decoder outputs are connected respectively with the installation and reset inputs of the fifth trigger of the data analysis unit, the trigger synchronizing input is connected to the output of the EXCLUSIVE OR element, the output of the fifth trigger is b the sign analysis window is connected to the output of the sign of change of the abscissas and ordinates of this block, the third and fourth outputs of the decoder are connected to the inputs of the second element OR of the sign analysis block, the output of the second OR element of this block is connected to the input of the installation of the sixth trigger, the direct output of which is connected to the control the inputs of the fifth and sixth multiplexers of the character analysis unit. FIG. 1 73 74 36 76 Fig. 3'a} th przom to! A5onte