SU1418700A1 - Device for dividing numbers - Google Patents

Abstract

The invention relates to computing and is intended to divide multi-digit numbers in a binary number system. The purpose of the invention is to expand the field of application by operating in the binary t-number system. The goal is achieved by the fact that the device for dividing numbers contains the register 1 of the dividend, subtractor 3, the register 4 divisor, the register 5 of the remainder, the generator 6 times, the control unit 7 and the register 8 private. contains circuit 2 comparison with the corresponding links. 1 hp f-ly, 2 ill. and s

Description

00

The invention relates to computing technology and is intended to divide multi-digit numbers in a binary number system.

The aim of the invention is to expand the field of application by operating in the binary t-number system. Figure 1 is a diagram of the device for dividing numbers; Figure 2 is a block diagram of the control unit. I The device (Fig. 1) contains a register 1 of the dividend, a comparison circuit 2, a subtractor 3, a divider register 4, a residual register 5, a 6-fold generator, a control block 7, a register 8: private, a device start input 9, an installation input 10 of the register 1 delimi | Mygo, the first input 11 of the resolution of the issuance of the register 1 of the dividend, information input 12 of the register of the dividend, the second input of the resolution 13 of the register jpa 1 of the dividend, the first and second outputs | dy 14 and 15 register 1 divisible, set | new input 16 register 4 divider, I output 17 register 4 divider, input 18 I resolution of reg Istra divider, information input 19 of generator 6; multiples, input 20 of start of generator 6: multiples, input 21 of installation in generator 6 O, generator 22, first and second outputs 23 and 24 of generator 6, input 25 of installation in O register 1 divisible, the first output 26 of the control unit 7, the first input 27 of the control unit 7, the second output 28 of the control unit 7, the second input 29; the control unit 7, the third to the sixth outputs 30-33 of the control unit 7, the first installation input 34 of the control unit gistra 8 private, exit 35 register 8 private, the first and second inputs 36 and 37 of scheme 2 In addition, the outputs 38 and 39, respectively, are More and Less than the comparison circuit 2, the information input 40 of the residue register 5, the input 41 of the installation in the residue register 5, the input 42 of the resolution for issuing the residue register 5, the output 43 of the balance register 5, inputs 44 and 45

deductible and diminutive subtractors 3, output 46 of difference of subtractor 3, output 47 of end of subtraction of subtractor 3, seventh output 48 of control unit 7, second set input 49 of register 8 private, start input 30 of control unit 7, output 51 Equal to comparison circuit 2 and the third input 52 of the control unit 7.

The control unit 7 (FIG. 2) contains the element OR 53, the element 54 of the delay, the elements OR 55 and 56, the counts 57 and the decoders 58 and 59.

Any number A in the binary t-number system can be represented as

1 A Z (K), (1)

where a, e f 0,

O when K - 0; p (K) 1 at O K 6 t; (2)

t + (

t |) .CK-t-j) with k t,

The value of (f. (K + 1) is the power of the K-th binary code in the minimum form of the images.

Algorithm division,

I. The divisible A is compared with the binary number system with the initial conditions B-divider defined by the expression

1 (Yu

About when K «i 0;

B at O i K t (3)

 eight

2Ic. (K-t-j) at K t

is searched for a bit such that

A -) D,

(four)

4, v

V

where O G C fi. (K-t-j),

jtrl

in the Kth bit, the logical 1 is represented and it is the highest bit of the quotient.

Ii. If GO, the division is over. t + (

If 0 Г i Z1 tVt (t-j), then Г

R

clauses are divisible and clauses I and II are repeated until the condition Γ 0 is met.

Analysis of the proposed algorithm shows that the quotient is obtained in the minimum image.

.j14187004

The generator 6 is designed for Genele 3, a subtraction operation takes place, the radios of the weights of the binary t-system, the number of which is recorded in relation to arbitrary initial conditions. Gistr 1 through its input 12, from the output of the catch in accordance with the expression 47 of the subtractor 3, a signal, indicating (3), indicating the end of the subtraction, the Inputs of the decoder 58 are connected to the input 29 of the control unit 7,

To (K-1) th inputs of the private register, which forms a signal from output 33

the outputs of the depshfratora 59 are connected with a reset in O to the input 21 of the generator

K-mi inputs of the register 8 private, 6, then from the output 32 - sig “to the delay element 54” is used to record into the generator 6 the contents of the signal register from input 29 to output 4 to its input 18, as well as

control unit at the time required to enter 34 register 8, recording

mine for rewriting the contents of regi-logical 1 in its (K-1) -th bit,

page 1.-15 Then, a signal is generated from output 26

The device operates by following the control block 7 to the input 11 of the register 1 1 and from the output 31 to the input 20 of the generator. The dividend is fed to the input 10 of the rector 6, which is the beginning of a new

Gistra 1 is divisible and is recorded in a work cycle. If the dividend is equal to vena. The divider is fed to the input of the 16–20 sous of the K-th bit of the sequence of the register 4 of the divider, where it remembers the binary t-number system from the query. The control block 7 forms by arbitrary initial conditions, then

mandu for input 11 of register 1 divisible from output .51 of circuit 2 comparison to input

On this, the number from the output 15 of the re-52 of the control block 7 enters the siggistra 1 and is fed to the input 36 of the circuit 5, the processing of which 2 comparisons, and also the result that the register 8 through

Manda to input 18 of register 4 for recording input 49 is written into the K-th bit of the divider into generator 6, which is logical-logical 1, in this case with the input 19 that disappears at input 19, id 35 of register 8 is the result

at the input 20 of the generator 6, allowing 30 divisions, before the start of the overwrite of the first start of generation, From the output 23 of the ge number to the register 1, its turner to the input 40 of the register 5 occurs, the input 25 from the output 47 returns the value (K -1) the number of subtractor 3.

with the weight of the binary t-system, control block 7 operates the followers with arbitrary initial conditions. The signal to input 50 is triggered and recorded. With the output signals at outputs 26 and 32.

24 generator 6 to the input 37 of the circuit. The signal to the input 27 causes signals

2 comparisons, the number K arrives, at the outputs 28 and 31, and also counted by the weight of the binary t-system is counted by the counter 57. The signal to the lazy input with arbitrary initial conditions is 40 52 counted in the counter 57 by catch (K is the current bit d, generated by and resolves the operation of the decoder 59, generated by the generator 6). Circuit 2 sravne-signal to the input 29 vyzgeaet signals

nor does it compare the dividend sleep outputs 26, 32 and 33, calculate the curtain of the K-th bit received by the set counter 57 and allow the operation

generator 6. If the dividend is greater than 45 of the decoder 58,

the weight of the K-th bit, then from output 38 of the circuit - Additional positive efma 2 comparison to input 27 of block 7, the effect is to receive a particular form, a signal is given that minimizes and increases quickly from output 31 of control 7 submission. signal on the next cycle of the gen- jq

Claims (2)

walkie-talkies to input 20 of generator 6, pre-formula of the invention On output from 28 of control block 7, a reg-1 zero signal is given. A device for dividing numbers, country 5 to its input 41. If the dividend containing the register of the dividend, the register is less than the weight of the K-th digit, then from the output gg divider, subtracter, remainder register, 39 of comparison circuit 2, the signal generator is generated , the control unit, the input and the divider, and the subtractor 3, respectively, are connected to the register; inputs 45 and 44 are connected to the register; In the subtraction now. the input of the register of the dividend, first the output of which is connected to the input of the decremented subtractor, the input of the sharing device is connected to the installation-fm input of the divider register, the output of the private register is the output of the Private device, the start input of which is connected to the start input of the control unit, the first output of which is connected of the register of the dividend, which is due to the fact that, for the purpose of P (aspiranty of the field of application due to the work | in the binary t-system is not included), it contains a comparison circuit, 1 output of the register of the divider the second input of the register is de-connected to the first input of the comparison circuit, the output of which is More than, connected to the primary input of the control unit - J leni, the output of the register of the remainder is connected to the input of the subtracted subtractor, the difference fcode of which is connected with the information input of the shared register, the second input of the resolution of which is connected to the input of the resolution of the register of the remainder and from the output Smaller comparison circuit, the output of the end of the subtraction of the subtractor HJeH from the setting of the register of the dividend and the second input one control unit, the third output of which is connected to the output Equal to the comparison circuit, the first and second outputs of the generation Tjopa are connected respectively to the information input of the remainder register and the second input of the comparison circuit, the outputs from the second to the seventh block controls are connected, respectively, to the input of the installation in the remainder register register, to the first installation input of the private register, to the generator start input multiples, to the register enable input of the divider, to the installation input to the generator multiples, and to the second installation private input of the private register. 2. The device according to claim 1, characterized in that the control unit contains three OR elements, a delay element, two decoders, a counter, wherein the control input of the control unit is connected to the first inputs of the first and second OR elements, the outputs of which are respectively first and The first outputs of the control unit, the first input of which is connected to the first input of the third OR element, and the second and fourth outputs of the control unit, the second input of which is connected to the second input of the third OR element, to the resolution input of the first decoder, m input of the second element SHS, with the sixth output of the control unit and through the delay element with the second input of the first element OR, the information inputs of the first and second decoders are connected to the output of the counter, the counting input of which is connected to the output of the third element OR, the outputs of the first and second decoders are connected to the reset input of the counter and are respectively the third and seventh outputs of the control unit, the third input of which is connected to the third input of the third OR element and to the enable input of the second decoder. 27 28 52 О О О , L 6 FIG. 2 2S ABOUT Compiled by A. Klyuev Editor O. Yurkovetska Tehred A. Kravchuk Proofreader M. AefMHK Order 4153/45 Circulation 704 VNIISH State Committee of the USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Subscription