SU1270758A1 - Device for dividing binary numbers - Google Patents

Abstract

The invention relates to computing and can be used to create specialized computers. The purpose of the invention is to increase the speed by eliminating the loss of time on the divider shift before dividing and quitting after it ends, as well as minimizing the number of division cycles for a given accuracy of the result. The device contains units for determining the significant part of the dividend and divider, commutators of the dividend and divider, registers of the dividend, divider and private, two comparison blocks, an adder, two adders-subtractors and a control block. 2 ill., 1 tab.

Description

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This invention relates to advanced engineering and can be used in specialized computing machines.

The purpose of the invention is to increase speed.

FIG. Figure 1 shows the block diagram of the device for dividing binary numbers, Fig. 2 is a functional block diagram of the control unit.

A device for dividing binary numbers (Fig. 1) contains input 1 of the dividend code, input 2 of the divider code, input 3 of the division accuracy code, input 4 of the tracking signal, block 5 for determining the significant part of the dividend, consisting of priority 5, and the encoder 5, block 6 op2

determining the significant part of the divider, consisting of priority allocation node 6 and encoder 6j, adder 7, additional adder-subtractor 8, dividend switch 9, divider switch 10, control unit 11, additional code comparison unit 12, divisor register 13, divider register T4, adder-subtractor 15, block 16 comparison of codes, register T7 private, output private 18, output 19 ending the division of the device.

The control unit (Fig. 2) contains a trigger 20, a subtracting counter of 21 cycles, the first element is NOT 22, the first element is AND 23, the generator 24 of pulses, the register 25 is shifting5 D-flip-flop 26, the second element is NOT 27, the second element is AND 28, the element OR 29, the third element and 30.

Tstrustvo works as follows.

The inputs 1, 2 and 4 devices (Fig. 1) are received n and

Dividebie codes for the divisible A, divider B, together with the tracking signal. In blocks 5 and 6, the definition of the significant part of the dividend and divisor is determined by the number of significant bits of the dividend codes, and the divider, and the result is encoded by the m, m bits and the code. In this case, the number of significant bits of each code is determined as the difference between the size of the corresponding code (n, n) and the number of higher zero bits, the next ones in it. If, for example, the inputs 1 and 2 of the device receive 8-bit codes A and B, which are equal to 10010010 and 00010101, respectively, then 4-bit codes 1000, 0101 are formed at the outputs of the direct code of blocks 5 and 6 of the meaningful definition, the part of the dividend and the divider, and the outputs of the return code of the block 6 of the meaningful part of the divider are received code 1010.

The output codes of blocks 5 and 6 determine the significant part of the dividend and

the divider controls the switching process of the corresponding input codes in the switches 9 and 10 of the dividend and the divider so that the first bit of their output code corresponds to the first significant bit (1) of the input code, the second bit of the output code to the second, next to the significant one, code, etc. Therefore, for the considered values of codes A 10010010 and B 00010101, codes A 10010010 and B 10101000, which are recorded in registers 13, arrive at the outputs of switches 9 and 10 of the dividend and divider, respectively.

5 and 14 divisible and divisor according to the resolution signals of the recording of the dividend and divider formed at the outputs of the control unit 11.

After writing the dividend and the divider into the corresponding registers 13 and 14, the division process begins, which is as follows. The contents of registers 13 and 14 of the dividend and the divider are compared in block 16 of the code comparison, and at the same time, at the output of the adder 15, the difference of the registers 13 and 14 of the dividend and divider is recorded, which is written to the switch 9 of the divisible by the synchronization signal (TV signal) from the first output of register 25 shift control unit 11. In the event that the contents of the register 13 of the dividend are not less than the contents of the register of the divisor, i.e. A / B, the difference between the dividend and the divider from the output of the switch 9 of the dividend is then rewritten according to the signal; the resolution of the record is divisible in the register 13 of the dividend with a shift due to switching one bit to the left. Simultaneously with the recording of the difference (A-B) in the switch 9 of the dividend, a shift is made in register 17 of the private and writing to the lower bit of its unit, since A B. In that case, if

 the contents of the register 13 divisible

less than the contents of the register 14 divider, i.e. A i B, then the overwriting of the A – B difference from the switch 9, which is not divided into the register 13, is not made, and the contents of the register 13, the dividend is shifted to the left by one bit according to the Shift signal generated at the output of the And 30 element of the control block 11. Moreover, the control unit 11 generates either the recording resolution signal of the 28 A / B element divisible at the output, or the Shift signal at the And 30 element output, and the formation of one of these signals always occurs after generating signals at the first output of the shift register 25 of the control unit 11, t . after the time of writing the difference in the switch 9 dividend and shift information in the register 17 private. In the case of A B, then the low-order bit of register 17 of the private record is 0, since when the information in it is shifted, a low level from block 16 of the code comparison arrives at the information input. This concludes the process of forming the next private digit. The number of division cycles is r, i.e. the number of characters in the private is not constant, but depends on the division accuracy code supplied to the input 3 of the device and on the ratio of the significant parts of the dividend and the divisor in accordance with the expression r (f, w-K) - t K is the division accuracy code that arrives at input 3 of the divider; t - bit codes of the number of characters in the significant part of the dividend and the divisor. The code formation of the number of division cycles is performed by the adder 7 and the adder-subtractor 8 before the start of the division, i.e. upon receipt of codes divisible and divisor on the inputs 1 and 2 of the device. The value of r from the output of the additional adder-subtractor 8 is recorded by the signal followed by the input 4 of the device to the control unit 11, which, after performing the corresponding number of division cycles, produces a signal arriving at the output 19 of the device. The signal shaping moment-55 by the control unit 11 determines the moment when the division process ends, when the division register 17 of the partial 758 records the division result, and the lower K bits of the private register 17 are the fractional part of the division result, the number of digits in which is equal to the division code by Inlet 3 device. The result of the division can be formed at the output of the device immediately after the arrival of the codes of the dividend, the divisor and the tracking signal, if it is equal to zero. In this case, for a given accuracy, the quotient is zero, therefore the sum is not the output of the sum, torus 7 and. + K is less than the significant part and the output of the divider 12 is -. comparison, a signal is formed which sets the private register 17 to zero and the number of cycles of control block 11; therefore, the output of counter 21 of cycles of control block 11 receives a signal defining the end of dividing the numbers A and B. The codes denoting the significant part of the dividend and the divider are generated similarly , therefore, blocks 5 and 6 contain the priority allocation node and the encoder, and the size of the code for designating the significant part is: log (n + 1), where n is the size of the dividend or divisor; the nearest greatest integer. The divider code from the block input goes to the priority allocation node, which decodes the code combinations 01 ..., 001, 00100000001, respectively, and forms a high level at the output, and for codes whose most significant bit is 1, no decryption is performed and the signal from the input The 2 dividers arrive at the first input of the encoder 6, the remaining inputs of which receive the output signals of the priority section 6. When the code is generated. indicating the significant part of the divider in the encoder 6, converts the positional code of the channel output number of the priority sharing node, on which the high level is formed, into the binary 4-bit forward and reverse codes in accordance with the data in the table. 001 0001 00001 ... 000001 .. 0000001. 00000001 Due to the fact that in block 6 for determining the significant part of the divider, the reverse code of the divider is used, the NOT elements are contained in the named block. The control of the dividing process in the device is carried out by the control unit 1 (Fig. 2) operating in the standby mode, and it is started when the tracking signal arrives at the input of the S-flip-flop 20. In the initial state, the flip-flop 20 and the D-flip-flop 26 are set to zero, at the input Reset counter 21 - a high level, so it does not count pulses, and on all outputs of control unit 11 - a low level. When a follow-up signal arrives, trigger input 20 is set to a low level at the input. Resetting the counting counter 21 cycles. The signal from the direct output of the trigger 20 allows the unit to be written to the shift register 25 according to the signal from the generator of 24 pulses. After a high level, on the first output of the shift register 25, the next signal of the generator 24 on the first output of the shift register 25 appears low, and on the second output a high level. As a result, a shift register 25 is started synchronously with the tracking signal, thus forming two pulses T. and T „at the outputs, which do not coincide

L lvo time, follow each other. The signal T, L. arrives at the first control output 11, synchronizing the block with the process of writing information to the switch 10 of the divider and shifting the information in the register 17 of the private. The first signal T, formed after the arrival of the tracking signal, goes through element I 28 to the output of the control unit, and on the trailing edge sets the D flip-flop 26 to one, the high level from the direct output of which goes to the output of control unit 11, controlling the information switching, and on the leading edge, entering into the register 14 is a divider code divider. The signal T is fed to the output of the AND 28 element if it is the first in a row since the beginning of the division, or if the input of the analysis of the element OR 29 is high, i.e. if the dividend is not less than the divisor. In the first case, the input code of the dividend, and in the second, the code of the difference between the dividend and the divisor is written to the register 13 of the dividend. If fe for some division cycle, the dividend is less than the divider, then the analysis input receives a low level, which prohibits the passage of the signal T to the second output of the control unit and permits its passage to the output of the E30 element, i.e. to the output of the control unit, with one shift to the left in the register 13 of the dividend. The control of the number of division cycles is performed by the counter 21, before the start of the division, into which a low level from the code of the D-flip-flop 26 (until it is turned on) introduces the code of the number of division cycles from the input of the control unit. Each division cycle includes two ticks (T and T signals), and in the first cycle, in the register of the dividend and divider 13 and 14, the dividend and the divider are recorded, and in all subsequent ones, the numbers are directly divided. After the end of the next division cycle according to the CT signal, one is subtracted from the contents of counter 2. After performing the number of division cycles per unit of the larger code of the number of division cycles per information

In the output counter Loader Counter 21, a signal is generated that determines when the division ends. This signal arrives at the device output 19, and in the control unit, the signal at the output of the cycle counter sets the trigger (20) and D-trigger 26 to the initial (zero) state.

In the event that the division of these numbers is not necessary (the result is zero), then a high level goes to the reset input of the counter 21 of the subtractive cycles, which sets the counter to zero and, on the first signal T, the shift register 25, the Loan signal is generated defining the end of the division process.

In the proposed device, the division process begins immediately after the arrival of the dividend, the divider and the tracking signal at the inputs 1, 2 and A of the device, and the result of the division is formed simultaneously with the end of the division (on the leading edge of the clock signal).

Claims (1)

Invention Formula A device for dividing binary numbers, containing registers of the dividend, divisor, private, adder-subtractor, code comparison unit and control unit, containing shift register, subtracting cycle counter, trigger, pulse generator, three elements, And the output of the register of the dividend is connected to the first inputs of the adder and the code comparison unit, the second input of the subtractor is connected to the output of the reverse code of the register of the divider, the output of the direct code of which is connected to the second input of the code comparison unit, the output of which n with the analysis input of the control unit, the output of recording the dividend of which is connected to the input of the recording resolution of the dividend, the input shift offset of which is connected to the output of the shift resolution of the control unit, the output of the recording resolution of the splitter of which is connected to the input of the recording resolution of the splitter, the output of the register private The output of the result of the device, characterized in that, with the aim above 707588 No speed, a significant part of the divisible part determining block containing the priority allocation node and the encoder, the significant part definition part of the divider, the priority highlighting node and the encoder, the dividend and divider switches, the adder, the additional adder-subtractor and the comparison block are entered into it. 0 codes, and the input of the block for determining the significant part of the dividend is the input of the dividend device and is connected to the input of the priority priority block of the block for determining the significant hour-15 of the dividend and to the first information input of the switchboard divisible, the second information input of which is connected to the output of the adder-subtractor, dividend switch code 20 is connected to the information input of the register of the dividend, the input of the unit for determining the significant part of the divider is the input of the device divider and is connected to the input of the allocation unit  the priority of the block for determining the significant part of the divider and with the information input of the switch the divider, whose output is connected to the information input of the register of the divider, the output 30 of the allocation node, the priority of the block for determining the significant part of the dividend is connected to the input of the encoder of the block for determining the significant part of the dividend, the output of which is connected to the first control output of the switchboard of the dividend and to the first input of the adder, the second input of which is the device division accuracy code , the direct output of the node of the prioritization of the block of determining the significant part of the divider is connected to the input of the encoder of the block of the significant part of the divider, the direct output of which is connected to the control input of the switch and the divider and the first information input of the additional code comparison block, the second information input of which is connected to the output of the adder and the first input of the additional subtractor-subtractor, the second input of which is connected to the inverse output of the encoder of the significant part of the divider, the output of the code comparison block is connected with the private register information input, the reset permission input of which is connected to the output of the additional code comparison unit and the first reset enable input of the subtracting cycle counter of the control unit, the information input of which is connected to the output of the additional adder-subtractor, the synchronization input of the additional code comparison unit is the input of the device tracking signal and connected to the single trigger input of the control unit, into which D- are additionally inserted trigger and two elements NOT, element OR, and the direct output of the trigger is connected to the first input of the first element AND, the output of which is connected to the information input of the register Moving, the timing input connected to the output of the pulse generator, the output MSB of the shift register is connected to. the shift enable input of the private register and the synchronization input of the switch of the dividend device and with the input of the first element NOT, the output of which is connected to the second input of the first element AND, the output of the lower bit of the shift register is connected to the first inputs of the second and third, elements AND, with the clocking input D- trigger and loan entry of the start loop counter, second input -30 the reset resolution of which t with the inverse-trigger output, the reset resolution input of which is connected to the reset input of the D-flip-flop and with the output of the subtractive counter 1 and dc is the output of the dividing end of the device, the D input of the D-flip-flop is connected to the input of the logical unit, direct output of the D-flip-flop - with the inverse input of the write resolution of the subtractive loop counter and with the second input of the third element-I, the third input of which is connected to the output the second element is NOT, the input of which is connected to the second input of the second element AND and the output of the OR element, the first input of which is connected to the inverse output of the D-flip-flop, the second the input of the OR element is the analysis input of the control unit, the output of the second element AND is the output of the write resolution of the divisible control unit, the direct output of the D-flip-flop is the output of the recording resolution of the control unit divider and is connected to the second control input of the split switch, the output of the third element I is the code for the resolution of the shift of the control unit. FIG. 2 one