SU1141407A1 - Device for calculating value of square root - Google Patents

Abstract

DEVICE FOR CALCULATION. SQUARE ROOT, containing the first, second and third registers, my comparison circuit, adder, control unit containing the pulse generator and the first AND element, the first input of which is connected to the output of the pulse generator, the information outputs of the first register are connected to the first group of inputs of the comparison circuit, the second group of inputs of which are connected to the outputs of the adder and to the information inputs of the second register, the inputs of the first term of the adder are connected to the outputs of a third of its register, characterized in that, in order to increase the device speed, entered into the counter, a group of elements And, the fourth and fifth registers, and the control unit - the first and second pulse distributors, the second and third elements And, three elements OR, element NOT, trigger, the output of which is connected to the second input the first element And, the output of which is connected to the input of the first pulse distributor, the output of the comparison circuit is connected to the first inputs of the elements AND of the group, the first input of the second element And and the input of the element NOT, the output of which is connected to the first input of the third element And the output of which is connected to the first input of the first OR element, to the counter subtraction resolution input and the synchronization input of the second register, whose information outputs (which are connected to the inputs of the second term of the adder, the second input of the first OR element, and the addition of the counter, the first input of the second (P1I PIC element is connected to the output of the second AND element, the device synchronization input is connected to the 4th synchronization input of the first register and S1 by the first input of the third OR element, the output of which the first output of the first Pficch pulse limiter is connected to the clock input of the counter and the shift input by three bits towards the square bits of the fourth register, the second output of the first pulse distributor is connected to the second input of the second OR element, the output of which is connected with the add resolution enable input, the account control input of which is connected to the output of the first OR element, the third output of the first pulse distributor

Description

connected to the shift input by one bit in the direction of the higher bits of the fourth register, the clock input of the fifth register and the input of the second pulse distributor, the fourth output of the first pulse distributor is connected to the second inputs of the second and third elements And the fifth output of the first pulse distributor is connected to clock input of the third register, the bit outputs of which are connected with a shift by one bit towards the younger ones with the first group of bit inputs of the counter, the second and third groups of the bit inputs of the counter oedineny respectively with straight and inverted outputs of the fourth discharge dnymi

the register, the bit outputs of the counter are connected respectively to the information inputs of the third register, the outputs of the second pulse distributor from the first to the kth (V is the result size) are connected respectively to the second inputs of the AND elements of the group, the outputs of which are connected respectively to the information inputs of the fifth register , vkhd code of the argument of the device is connected with a shift of 2fT bits towards the older (t is the number of bits of the fractional part of the result) with the information inputs of the first register, the V-th output of the second distribution A pulse pulse is connected to the second input of the third OR element.

one

The invention relates to automation and computing and can be used in the construction of specialized computing devices, functional information converters and as a specialized processor of large digital computers.

A device is known for calculating the square root, the content (its three adders, the counter, the comparison circuit, the shift unit 1, and the three registers Cl.

The disadvantage of the device is low speed.

The closest in technical essence to the present invention is a device for calculating the square root, containing the first, second and third registers, the matching circuit, the first and second accumulating adders, the control unit, the memory unit, while the information outputs of the first register are connected to the first group of inputs comparison circuits, the output of which is connected to the first input of the control unit, are connected to the second group of inputs of the comparison circuit the outputs of the first adder, which are also connected to the information inputs of the second register Istra, the inputs of the first adder are connected to the information outputs of the third register, the information inputs of which are connected to the outputs of the second adder, which are also connected to the information inputs of the first register, the inputs of the second adder are connected to the information outputs of the second register, the information inputs of the second accumulator register, and its adder connected to the input of the argument code, as well as with the outputs of the first sum: torus; the first output of the memory unit is connected to the second input of the control unit; and the second output of the pa m to the information inputs of the second register, the input of the memory unit is connected to the first output of the control unit, the second output of which is connected to the synchronization input of the second register, is clocked (the third output of the control unit is connected to the input of the second adder, the fourth output of which is connected to the synchronization input the third register, the fifth output of the control unit is connected to the clock input of the first totalizer; the sixth output of the control unit is connected to the third input of the comparison circuit, the seventh output of which is connected to the input chronization of the first register 2.

A disadvantage of the known device is relatively low speed. 3 The purpose of the invention is to increase the speed of the device. The goal is achieved by the fact that the device for calculating the square root containing the first, second and third registers (Comparison circuit - adder, a control unit containing a pulse generator and the first And element, the first input of which is connected to the output of the pulse generator, information outputs the first register - with the first I group of inputs of the comparison circuit, the second group of inputs of which is connected to the outputs of the adder and information inputs of the second register, the inputs of the first term of the adder with the outputs of the third register , entered the counter, a group of elements And, the fourth and fifth registers, and in the control unit - the first and second pulse distributors, the second and third elements AND, three elements OR, the element NOT, a trigger, the output of which is connected to the second input of the first element I, the output of which is connected to the input of the first pulse distributor, the output of the comparison circuit — with the first inputs of the elements AND of the group, the first input of the second element AND, and the input of the element NO, the output of which is connected to the first input of the third element AND, the output of which is connected to the first input OR, with the counter subtraction resolution input and the synchronization input of the second register, whose information outputs are connected to the inputs of the second term of the adder, the second input of the first OR element — with the output of the second OR element, and the addition input of the counter; the first input of the second OR element — with the output the second element AND, the device synchronization input — with the synchronization input of the first register and the first input of the third OR element, the output of which is connected to the trigger input; the first output of the first distribution body - with the clock input of the counter and the shift input three times in the direction of the lower bits of the fourth register, the second output of the first pulse distributor with the second input of the second element whose output is connected to the input of the addition of the counter, the control input of which is connected to the output of the first element OR, the third 074 output of the first pulse distributor - with a shift input for one bit towards the higher bits of the fourth register, a clock input of the fifth register and the input of the second pulse distributor, the fourth output ervogo distributor pulses - with the second inputs of the second and third AND gates, n ty first distributor output pulses to a clock input of the third register, The discharge outlets of which are joined by a shift by one bit in the direction of the first group of younger discharge railway. the counter inputs, the second and third groups of the bit inputs of the counter, respectively, with the direct and inverse bit outputs of the fourth register, the bit outputs of the counter, respectively, with the information inputs of the third register, the outputs of the second pulse distributor from the first to the Vth (V - result size) - respectively, with the second inputs of the elements AND of the group, the outputs of which are connected respectively to the information inputs of the fifth register, the input of the device argument code - with a shift by 2 tons of bits towards the highest x (number of bits m is a fractional part of the result) to data inputs of the first register, the ith output of the second pulse distributor - to the second input of the third OR gate, FIG. 1 shows a block diagram of the device, FIG. 2 is a functional block diagram of the control unit; FIG. 3, two bits of counter 6; in fig. 4 is a fragment of the binary representation of the function Y Vx. The device (Fig. 1) contains a register 1, a comparison circuit 2, an adder 3, registers 4 and 5, a counter 6, a shift register 7, a control block 8, a group of elements AND 9, a register 10, a sync signal input 11 and an argument code input 12 . The functional block diagram I control contains a generator of 13 clock pulses, elements OR 14-16, trigger 17, element NOT 18, elements AND 19-21, distributors 22 and 23 pulses, functional diagram of two bits of counter 6 contains triggers

 one

24 and 25, elements 2I-IPI 26 and 27, elements AND-NO 28-33.

The principle of operation of the device is based on the following positions.

1. In the binary representation of the function Y yx 1 -digit

Ic-m-l

Y, 2

difference S L (j + 1) - L.j (j)

 WITH; const,

where m 7-1 is the number of fractional bits j L (j) is the j-th interval of the i-bit bit constant, equal to the length of the j-th segment of the argument, on which the i-th bit takes only a single or zero value about

2. Between adjacent intervals of constancy in the i-th and (i-1) -th digits of the binary representation of the function Y V, the following relations take place, written in a form convenient for organizing the computational process

M (0) / U., (2j) L. (j) / 2rSj8;

L,., (.., (, / 4;

t, (. uj) - /.

(ei (ii where L; (j), L (j) - respectively

the zero and one intervals of the constant i-ro bit,

on which the j-th bit takes only zero (on L, - (j) or only one (on L, (j) value.

 Determining which function constant interval — single or zero in each bit of the binary representation of the function Y.Vx obtained when the change in the argument of DX, 2 is discrete, belongs to the value of the argument X-221, makes it possible to form the values of all bits of the function Y. This definition is realized by comparing with current 1414076

the common value of the sum of the integrals of the shafts of the constant Y of the function Y

 -1tek 5UM

° l-17T and the result at the output of circuit 2

if SUM

 5. if SUM

MO A MOA

In the diagram of the device shown in FIG. 1, the comparison of SUM .... with

MO

The mole is performed in comparison circuit 2, calculating the current value

is carried out in the adder 3, the calculation of the intervals of constant in the counter 6, the formation and storage of the difference B. the intervals of the constancy is realized in the shift register 7,

the result Y Vx is formed in register 10.

The device works as follows.

In the initial state in the register 5 and the counter 6 the code of the first interval of the constant bit of the binary representation of the function Y TX L 1, (1) 221-2 is written, in the register 7 the code of the difference S Lj (2) is written L, (( 1), the rest are all registers and the trigger is reset.

On the sync signal from input 11, the code of the argument X from input 12 is written to register 1. So how does the recording occur? goes with a shift due to a hard link by 2m bits towards the older ones, then the code appears in the register

X-22. Sync input

X

WOA

11 also goes to the second entrance

control unit 8, in which the clock signal passes the element OR 14 and switches to 1 flip-flop 17. The logical 1 signal from the direct output of the flip-flop 17 opens element 19 and the clock pulses from the generator 13 clocks start to flow to the distributor 22 pulses, which commutes them on

five directions. The first clock pulse from the distributor 22 pulses is fed to the first output of the control unit 8 and then to the input of the reception of the information of the counter 6

and to the input of the shift register control 7, while in the counter 6 the information is received from the register 5 with a shift due to the hard connection one bit in the direction of the younger ones, and in register 7 the shift of its contents to. three ranks in the direction of the younger ones. The second clock pulse from the second output of the pulse distributor 22 is fed to the second input of the element OR 15, the output of which is the second output of the control unit 8, in addition, the signal from the output of the element OR 15 is fed to the second input of the element OR 16 and from its output to the sixth control unit 8 output. From the second output of the control unit 8, a clock pulse is fed to the input of the addition of the counter 6, Simultaneously from the sixth output of the block. 8, the control signal of logical 1 is fed to the counter control input of counter 6, the first group of bit inputs of which is fed to the code from the direct outputs of register bits 7 containing one 1, and the third group of bit inputs of counter 6 is supplied with code inverse outputs of register bits 7. Counter 6 realizes the addition of its contents with register code 7. Simultaneously with the execution of operations synchronized by the first and second clock pulses, in the adder 3, it calculates the current value of the sum of the constant interval from this the interval of constancy of register 5 is added to the previous value SUM in register 4. The value obtained is compared in scheme 2 comparison with | CODE. , u (of, meaning that in the 1st bit of the binary representation of the function Y -Vx, this value of argument X corresponds to a unit interval of constancy, otherwise - zero. The result of the comparison from the comparison circuit 2 goes to the first group of inputs of the group of elements And 9 The third clock pulse comes from the third output of the distributor 22 pulses to the input of the distributor 23 pulses which commutes the input pulses to k directions, which are the 1-seventh seventh output of the control unit 8. The code from the seventh output of the control block 8 events that associate one 1 in iM bit, rises to the second group of inputs of the group of elements AND 9 and opens the i-th element in 1 78 of it. The signal from the output of the i-th element and the group of elements And is recorded in the i-th bit of the register 10 of the result of calculating the function Y, whose clock input receives the clock pulse from the third output of the control block B. Comparisons in the comparison circuit 2 and writing the values of the bits of the function Y Vx to the register 10 are made starting from the higher bits. The clock pulse from the third output of the control unit 8 also enters the shift control input of the register 7 and shifts its contents by one, the bit in the direction of the start. The fourth. Tactical pulse from the fourth output of the distributor 22 pulses is fed to the second input of the I-21 element, the first input of which is the value of the signal from the output of the comparison circuit 2, which is inverted to the HE 18 element. If the output of the comparison circuit 2 is logical O, then the And 21 element is open, and the quarter clock and fly is passed to the fourth output of control unit 8 and further to the input of the subtraction resolution of the counter 6, in addition, the fourth clock pulse goes to the OR 16 element the sixth output of the control unit 8 and then to the counter control input of the counter 6. In the counter 6, a subtraction operation is performed, as a result of which in the counter 6 there appears the (2J - 1) -th constant interval of the next (i - T) -th the bit is Lj. (2j - 1). If the output of comparison circuit 2 is logical 1, then And 21 is closed, And 20 is open, and the fourth clock pulse through the open AND 20 is fed to the first input of the OR 15 element, the output of which is the second output of control unit 8. From the second output of the control unit 8, the fourth clock pulse is fed to the input of the resolution addition of counter 6. In addition, the fourth clock pulse comes from the output of the OR element 15 to the second input of the OR element 16 and from its output, which is the sixth output of the control block 8, to the counter control input. 6. In the counter 6, the operation of the counter is realized, as a result of which the counter (2j + 1) -th interval of the next (i - 1) -th bit - L- (2j + 1) Fifth a clock pulse comes from the fifth output of control block 8 register synchronization input 5. In register 5, the code of the computed current interval of a constant from counter 6 is rewritten. Thus, one iteration of the computational process is performed in five cycles. The computational process consists of fc iterations, each of which is formed by the value of one bit Y functions YX. Calculate. The personal process ends when a clock pulse appears on the last front of the last output of the pulse distributor 23. which in the register 10 is formed the value of the low-order bit, and in the rear - the trigger 17 switches to O and closes the Element AND 19o. The counter 6 operates as follows. Register 5 information is recorded into counter 6 as usual via RS-controlled zero inputs and clocked in counter 6 by a signal from the first output of control block 8 using AND-NE 29-32 elements, while eaJ, I-inputs are fed logical O from the outputs of the AND-NE elements 28 and 33. The reversal is also controlled in the usual way, opening signals from the fourth or second output of the control unit 8 to the corresponding element AND in the element 2И-OR 26 and switching to the counting input of the trigger 25 direct or inverse trigger output 24 "When performing an operation and addition (subtraction) in the counter 6 code from the inverse outputs of register bits 7, containing a single O in (i + 1) -th bit, closes the first element AND in element 2I-OR 27, the second input of which is connected to the output of element 2I -OR 26, and only 1, containing in the (1 + 1) -th code of the code coming from the direct outputs of register bits 7, through the second element AND in element 2I-OR open the logical 1 signal from the sixth output control block 8 is fed to the counting input of the trigger 25 (L + 1) -th bit of the counter 6. 0710 Thus, in the counter 6, the opera Ace of addition (subtraction), Register 10 is executed on counting triggers triggered by a leading edge of the signal, to the counting inputs of which the outputs of a group of elements AND 9 are connected. In a known device, the computational process is divided into two stages. At the first stage, preparatory calculations are performed that use write operations to the register (execution time tj), read from the memory block (t c jp), add in the adder (), convert the code to additional (t) Execute time of the first stage T , mc ... 2t.m "x {l (t, t), (% t.) - (1 In the second stage, the known device implements a direct square root calculation. This also uses the comparison () and shift () tg.) Burden of performing the second stage V () where is the result size. Total computing time is square The root is 05 1 In the proposed device, due to the simultaneous execution of operations, the computation time of the square root will be (); 11- л l. HH, (I where tp is the execution time of the addition operation on the counter. , we see that the time costs for calculating the square root in the proposed device are approximately equal to the time costs of the second stage of the computational process in the known device. Taking into account that T: -T, we do the output: the performance of the proposed device is about two times higher than that known with an increase in hardware costs by 10%. The accuracy of calculating the square root in the proposed device corresponds to the accuracy of calculating in the known device. For example, when calculating the square root of X 0.3645, the result is Y 0.6035156 (the fractional part size is chosen to be 12, as in the known device), while the true square root value of Y is 0.603738. The calculation error was 0.037%. Note that the error in calculating the square root in the proposed device is caused only by the limited difference in the representation of the result. The positive technical and economic effect of the invention is to increase the speed of the device by about a factor of two with increasing hardware; costs by 10%. Since both the known and proposed devices relate to devices whose performance is close to the limit, the achieved performance increase by half with an increase in hardware costs of 10% is a significant technical effect. The proposed device can be used in specialized sensing devices, functional converters of information, microcalculators, etc.

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Claims (1)

DEVICE FOR CALCULATING A SQUARE ROOT, containing first, second and third registers, a comparison circuit, an adder, a control unit containing a pulse generator and a first element AND, the first input of which is connected to the output of the pulse generator, the information outputs of the first register are connected to the first group of inputs comparison circuit, the second group of inputs of which is connected to the outputs of the adder and with the information inputs of the second register, the inputs of the first term of the adder are connected to the outputs of the third * of its register, characterized in that o, in order to improve the performance of the device, a counter, a group of AND elements, fourth and fifth registers are entered into it, and the first and second pulse distributors, the second and third AND elements, three OR elements, a NOT element, a trigger whose output is introduced into the control unit connected to the second input of the first element And, the output of which is connected to the input of the first distribution. pulse generator, the output of the comparison circuit is connected to the first inputs of the AND elements of the group, the first input of the second AND element and the input of the element NOT, the output of which is connected to the first input of the third AND element, the output of which is connected to the first input of the first OR element, with the input of the subtraction of the counter and the second register synchronization input, the information outputs of which are connected to the inputs of the second term of the adder, the second input of the first OR element is connected to the output of the second OR element and the counter addition input, the first input is W The OR element is connected to the output of the second AND element, the device synchronization input is connected to the synchronization input of the first register and the first input of the third OR element, the output of which is connected to the trigger input, the first output of the first pulse distributor is connected to the clock input of the counter and the shift input by three digits the side of the lower digits of the fourth register, the second output of the first pulse distributor is connected to the second input of the second OR element, the output of which is connected to the counter enable input, input The account control od which is connected to the output of the first OR element, the third output of the first pulse distributor SU. ..1141407 is connected to the shift input by one bit in the direction of the higher bits of the fourth register, the clock input of the fifth register and the input of the second pulse distributor, the fourth output of the first pulse distributor is connected to the second inputs of the second and third elements And, the fifth output of the first pulse distributor is connected to the clock the input of the third register, the bit outputs of which are connected with a shift by one bit toward the lower with the first * group of bit inputs of the counter, the second and third groups of bit inputs of the counter and are connected respectively to direct and inverse bit outputs of the fourth register, bit outputs of the counter are connected respectively to information inputs of the third register, outputs of the second pulse distributor from first to k-th (k-bit capacity of the result) are connected respectively to the second inputs of elements And groups, the outputs of which are connected respectively to the information inputs of the fifth register, the input of the device argument code is connected with a shift of 2fn bits towards the senior (hl is the number of bits of the fractional part p result) to data inputs of the first register, the k-th pulse of the second distributor output connected to the second input of the third OR gate.