SU1571609A1 - Device for computing number factorial - Google Patents

Abstract

The invention relates to computing and can be used to calculate functions in specialized computing systems. The purpose of the invention is to increase the speed of the device. The device contains a pulse generator, accumulating adder, first register, first and second subtractive counters, elements AND, elements OR, elements NOT, second register, first and second decoders zero, summing counter, trigger. The proposed device is faster, since the cycles of calculating intermediate factorial numbers for even factors are implemented by extracting a binary number that is a multiple of the even factor. 1 il.

Description

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The invention relates to computing and can be used to calculate functions in specialized computing systems.

The purpose of the invention is to increase the speed of the device.

The drawing shows a block diagram of the device.

The device contains a pulse generator 1, accumulating adder 2, first register 3, subtractive counters 4 and 5, elements AND 6-11, elements OR 12-15, elements NOT 16-19, second register 20, first 21 and second 22 decoders zero, summing counter 23, trigger 24.

The device works as follows.

Before starting operation, a negative pulse at the input of the initial installation of the device will reset the first 3 and second 20 registers, the first 4 and second 5 subtractive counters, summing counter 23. After the initial installation signal is removed, accumulator 2 must be written in the first register 3 . In this case, O from the output of the second register 20 will turn on the pulse generator 1, enabling the pulses from the last output to the synchronization input, the second register 20, the trigger 24. On the output of the first decoder 21, the zero keeps the output of the trigger 24 in the zero state, thereby blocking counting the input of the counter 23 and sets the second register 20 parallel recording mode.

In the initial state, after removing the initial installation, elements And 7, 8,

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10 will be blocked by the zero state of the information at the outputs of the first subtractive counter 4. With each pulse at the input of the second register 20, zero information is output from the output of the second subtractive counter 5, which does not change the operating state of the device.

The factorial calculation of a given J number is performed in cycles. Each calculation cycle is characterized by the presence of an initial intermediate value, which is the result of the calculation of the previous cycle. For the first calculation cycle, the initial value is the pre-recorded unit in accumulation adder 2 and in the first register 3. The number of calculation cycles is determined by j, the number of factorial factors of a given number. The last calculation cycle ends with the zero state of the outputs of the second subtractive counter 5 and a negative signal at its 2 output.

The factorial multipliers of a given number are set in turn, starting with a higher value, in the second subtractive counter, 5 — when the unit is deducted from its contents in each cycle of calculating a unit. Computation cycles for odd factors of a factorial of a given number are implemented by accumulations, and even ones by allocating an n-bit binary number that is a multiple of an even factor, storing it, followed by the number of accumulations equal to the remainder of dividing the even factor by an n-bit binary 4 number. However, the contents of the second subtractive count 5, i.e. the value of the next multiplier determines the number of accumulations in accumulative adder 2, in the next 4 calculation cycle.

A negative pulse at the synchronization input of the device records information from its input group, i.e. the binary value of the number whose factorial is to be calculated is written. During recording, the output of the element And 6 will be blocked, i.e. the operation of the second register 20 is excluded from the recording. After removing the negative write pulse from the synchronization input, the output of the And 6 element will be unblocked and after the first pulse arrives at the input of the second register 20, the contents of the second subtractive counter 5 will be recorded. The non-zero information at the outputs of the register 20 sets it through the first decoder 21 zero to shift the information left (in the direction of the younger bits). In this case, the reset signal of the trigger 24 is absent.

If the second register 20 contains the binary value of an even number whose parity is O at its output, the n-bit binary number is extracted by shifting the information to the left by one bit in the second register 20 until it appears at its output 1. When In this case, each shift cycle is accompanied by the operation of the counter 23 at its counting input. In case of occurrence of 1, the output of the second register 20 will block the element 6, turn on the pulse generator and record information from the outputs of the second register 20 into the first subtractive counter 4. Then the accumulation process will be organized later.

If a binary value of an odd number is written in the second register 20, then 1 at its output will cause the value of this number to be written to the first subtractive counter 4. i

After the binary value of any number is written to the first subtractive counter 4, and it will always be odd, the device directly implements the accumulation process in accumulative adder 2. The number of accumulations will be one less than the value of the odd number. 1 from the output of the element OR 13, the recording mode for the first subtractive counter 4 is turned off, the pulse generator 1 is turned on, the pulses from the pulse generator 1 are enabled to input the subtraction of the first subtractive counter 4 and to the input of accumulator 2. And on the leading edge of the signal at the output of the NOT element 17, the unit is subtracted from the contents of the second subtractive counter 5. The accumulation in accumulating adder 2 will occur until the contents of the first subtractive counter 4 become equal to the binary value of the unit, 0 from the output of the second decoder 22 zero is blocked work item

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And 10, from the output of the element And 9, the second register 20 is reset. And on the falling edge of the signal from the output of the second decoder 22 zero, the accumulation result is recorded in the first register 3. The second register 20 is held in the zero state by a reset signal until the last unit is subtracted from the contents of the first subtractive counter 4. After the reset is removed, a new cycle of the intermediate result of the calculation begins in the second register 20. After completion of all calculation cycles, the result of calculating the factorial of a given number will combine the result of the accumulation located at the first information output of the device with the value of the n-bit binary number located at the second information output of the device.

Consider an example of the operation of the device when calculating the factorial of the number three. The factorial of the number three contains factors of 1 - 3, of which two are odd and one is even. In accumulative adder 2 in the subtraction cycle for the odd multiplier 3, two accumulations are made. As a result, the first intermediate result of the calculation will be written to the first register 3, equal to the binary value of the number 3. For an even multiplier 2, the calculation cycle consists only of extracting a binary number that is a multiple of 2, resulting in the contents of the counter becoming 1. For the next odd multiplier 1 the amount of savings is zero. Thus, the result of calculating the factorial of a given number is contained in the first register 3 and the counter 23 and is equal to 3 and 2, respectively, whose product is 6.

Claims (1)

Invention Formula A device for calculating a factorial of a number, containing a pulse generator, accumulating adder, first register, first and second subtractive counters, first AND element, first decoder zero, first NOT element, the input of the initial installation of the device connected to the reset input of the first and second subtractive counters and the first register, the device sync input is connected to the input 09 (, enable the recording of the second subtractive counter, the overflow output of which is connected to the device readiness output, the information input of the accumulating adder is connected to the first information output of the device and the output of the first register, characterized in that, in order to improve speed, the second to sixth elements are entered into it, items two through four are NOT, items one through four, or, summing counter, second register, 5 is a second zero decoder and a trigger, with the device synchronization input connected to the first input of the first element I, the second input of which is connected to the output of the pulse generator 0 and the first input of the second element AND, the second input of which is connected to the output of the third element AND and the first input of the first element OR, the output and. the second input of which is connected respectively to the trigger input of the pulse generator and the third input of the first element AND, the overflow output of the first subtractive counter is connected to the first input of the second element OR and 0 through the first element NOT to the first input of the third element OR, the output of which is connected to the first input of the fourth element AND, the second input of which is connected to the input of the initial device, device installation and the reset input of the summing counter, the synchronization input of which is connected to the output of the fifth element AND, the first input of which is connected to the output of the first element Q AND, the synchronization input of the second register and the trigger synchronization input, the direct output of which is connected to the second input of the fifth AND element, the output of the second OR element, is connected to the first input of the fourth OR element and the first input of the third AND element, the second input of which is connected to the input the second element is NOT and the output of the fourth element OR, the second input 0 which is connected to the output of the third element NOT and the third input of the first element I, the output of the pulse generator is connected to the first input of the sixth element I, the second input of which is connected to the output of the second decoder five zero, the second inputs of the second and third elements OR, and through the fourth element is NOT with the synchronization input of the first register, the output of the sixth element AND is connected to the synchronization input of the accumulating adder, the output of the fourth element And is connected to the reset input of the second register, the mode selection input of which is connected to the output the first decoder zero and the reset input and information input of the trigger, the output of the second element is NOT connected to the subtractive input of the second subtractive counter, the parallel output of which is connected to the information the input of the second register, the serial output of which is connected to the input of the third element NOT, the parallel output of the second register is connected to the input of the first decoder zero and information input of the first subtractive counter, recording and subtraction resolution inputs of which are connected respectively to the output of the fourth element OR and the output of the second element AND, the output of the fourth element I is connected to the reset input of the second register, the parallel output of the first subtractive counter is connected to the input of the second decoder zero, information the device input is connected to the information input of the second subtractive counter, the output of the summing counter is connected to the second information output of the device.