SU1325467A1 - Dividing device - Google Patents

Abstract

The invention relates to computing and can be used in high-performance computers and systems. The aim of the invention is to increase the speed of the device. This is achieved by the fact that the device for dividing, containing registers of divider 2, remainder 1 and quotient 12, memory block 3, multiplier 4, adder-subtractor 6, subtractive counter 5, microprogram control block 11, loop counter 10 and functional connections, additionally equipped with a group of 7 elements AND, a group of 8 elements AND-NOT, a group of 9 elements OR, and additional functional connections, this allows the division algorithm to be implemented without restoring the remainder, in each cycle of which the par private bits are determined (p 2 , 3, ..., p-3; p is the bit width of operands), and provides an increase in the device speed by 15% at p 4, p 32, 3 sludge. 00 to SP 4 05

Description

The invention relates to digital computing, intended for dividing numbers represented in a binary number system, and can be used as an operating unit in high-performance computing machines and systems.

The purpose of the invention is to increase the speed of the device for dividing.

FIG. 1 shows the functional scheme of the device for dividing; in fig. 2 is a graph of transitions of states and outputs of the firmware control block; in fig. 3 is a diagram of a firmware control unit based on D-flip-flops with asynchronous S and R inputs with variable unit. The device for dividing (Fig. 1) contains a register of 1 residue, a register 2 of a divider, a memory block 3, a multiplier 4, a subtractive counter 5, an adder-subtractor 6, a group of 7 AND elements, a group of 8 AND-NOT elements, a group of 9 OR elements , counter 10 cycles, microprogram control unit 11, private register 12. Block 11 (Fig. 3) contains D-triggers 13-19, elements AND 20-25, elements OR 26-34, elements 35 and 36 of the delay. Block 3 stores the p-bit codes of the preliminary values of the next p bits of the private block 3 firmware, taking into account the fact that the high bit of register 2 is 1 and (p- | -1) is the second address of the block 3 connected to the higher bits of register 2, starting with the second most significant bit, excluding the first, Block 11 is designed to organize the division process, which consists of repeated cycles of the same type. In each cycle, the values of the next series of bits of the quotient are determined. For this, block 11 generates a sequence of control signals at its outputs. On the graph (Fig. 2) of the transitions of states and outputs, the block 11 controls Ao ... Ab are states, on arcs the conditions of transitions are indicated, and above the arrows are the names of the output signals generated during the transition to the corresponding state. The device works as follows. In the initial state AO in register 1 is a dividend, in register 2 it is a divisor, counter 10 is in the initial state (zeroed or by the signal "Reset the addition code is written to it).

On the "Start" signal, signifying the beginning of the division operation, block 11 transitions from the AO state to the Ai state. At the same time, according to the values of the corresponding higher bits of the divider and the module of the next (for the first cycle - initial) dividend, coming from registers 2 and 1 on corresponding address inputs of memory block 3, selects a code that is a preliminary value of the next private bits.

At the output of the multiplier 4, the product of the selected code by the divider is formed.

0

five

Then, block 11 transitions from the state AI to the state AZ. At the same time, the contents of counter 10 are incremented by one, and on subtractor 6, the difference between the next dividend and the product obtained at the multiplier 4 is calculated. The remainder thus obtained is recorded with a shift by the rank of bits in the direction of the higher bits in register 1. As a result, on register 1, a new next dividend is formed. Counter 5 records a code selected from memory block 3.

In the future, in the operation of the device, there is a combination in time of operations for determining the values of two groups (of-5 times in each) of the private bits.

Block 11, depending on the sign of the next residue obtained on the adder-subtractor 6, goes into the AZ state (the remainder is negative) or the AI state (otherwise). But regardless of this, the transition to state A; and Az, the product is formed, as described for the transition, by a divider by a code selected from block 3 of the memory according to the corresponding values of the leading digits of the module of the next dividend and the divider.

If A.e transition occurred, then to get the true values of the next private bits, the contents of counter 5 are reduced by one low-order one, and the resulting code from counter 5 is written 0 to the lower p bits of register 12.

If there was a transition. then the code stored on the counter 5 is written to the younger p bits of the register 12. After this, the block 11 changes from the AI state to the AZ state, while the register 12 shifts by the p bits to the high bits.

From state AZ to state A4, block 11 proceeds as described for transition. The difference is that instead of the difference on the subtractor 6, the sum of the new product and the new dividend is calculated. The next remainder thus written is written with a shift by p) of the streams towards the higher bits in register 1.

From state A, b) к 11, depending on the sign of the next residue, goes to the state of Hell or AI, similarly to the transitions, n Ar. The difference lies only in the formation of the true values of the next p bits of the quotient. Since the next dividend is negative (transition to the A4 state), then the true values of the next private bits are obtained by taking the addition from the code stored on counter 5 (state A, -), or by taking a fraction from the code increased by unit of low order (state Ae). Therefore, during the transition A. | K A.-, the code on the counter 5 decreases by one and is inverted, after which it is written into the minor p bits

five

0

five

0

five

register 12. When switching Ae, the counter code 5 is simply inverted (-1 and 0) and written into the lower-order bits of register 12.

Subsequently, the division process proceeds similarly and ends when the signal appears Stop from counter 10, according to which unit 11 enters the AO state and generates a Reset signal that sets the counter to the initial state.

Claims (1)

Invention Formula A device for dividing, containing dividers, quotient and remainder registers, multiplier, memory block, cycle counter, totalizer-subtractor, subtraction counter, firmware control unit, with the outputs of the higher (p- | -2) bits of the remainder register (where p 2 , 3, .... n-3; n is the width of the operands) is connected to the first address input of the memory block, the second address input of which is connected to the output (p + -t-1) of the high bits of the divider register whose output is connected with the input of the first multiplier multiplier, the input of the second multiplier of which is connected to the output the memory unit house and the information input of the subtracting counter, the output of the adder-calculator is connected to the information input of the register of the remainder, the output of which is connected to the first information input of the adder-subtractor, the output of the sign bit of which is connected to the input-analysis of the sign of the remainder of the microprogrammed control unit , the first output of which is connected to the reset input of the loop counter, the transfer output of which is 7 It is connected to the stop input of the microprogram control unit, the second output of which is connected to the counting input of the cycle counter, the third output of the microprogram control unit is connected to the enable input of the subtraction of the totalizer-subtractor, the input resolution of which is connected to the fourth output of the microprogram control unit, the start input Which Q is the start input of the device, characterized in that, in order to increase speed, a group of AND elements are entered into it, a group of AND-NOT elements, a group of OR elements, and the output of the multiplier is connected to the second information input of the adder-subtractor, the fifth output the microprogram control unit is connected to the multiplication multiplier enable input and to the write register write enable input input, the shift enable input of which is connected to the subtractive counter write enable input and to the sixth microprogram block output a lot of control, the seventh output of which is connected to the input of the loan of the subtracting counter, the outputs of the bits of which are connected to the first 5 inputs of the elements AND, the group and elements of the IS-NOT group, the second inputs of which are connected to the eighth output of the microprogram control unit, the ninth output of which is connected to the second inputs of the AND elements of the group, the outputs of which are connected to the first inputs of the elements of the OR group, the second inputs of which are connected to the outputs of the elements of the NAND group, the outputs of the elements of the OR group are connected to the information inputs ASP rows private register. 0 ETC ETC ffv “Hard Cffpac FIG. 2