SU1357946A1 - Device for division - Google Patents

Abstract

The invention relates to computing and can be applied to quickly divide numbers in any positional number system. The aim of the invention is to increase the speed of the device. Sleep is achieved by shortening the cycle time of the device containing the registers 1 and 2 of the dividend and divisor, adder 3 private, switches 4, 5 and 10, subtractor 6, register 7 most significant bits of the divider, adder 8 forced rounding, node 9 computing. Reverse values, multiplication blocks 11 and 12, and firmware control block 13. 4 il. CO SD with 1 about

Description

with n-bit binary code divides

The invention relates to computing and can be applied in high-speed arithmetic devices for performing the operation of dividing numbers.

The purpose of the invention is to increase the speed of the device by reducing the duration of the tact of forming k private and residual figures.

Figure 1 shows a block diagram of a device for dividing; figure 2 is a functional diagram of the adder private; on fig.Z - functional-. on the scheme of the microprogram block control unit when performing the division operation in FIG. 4 - the microprogram of the process of forming the correct

ten

unsigned, pressed to the left prana of register 2, and at the beginning of its own division, it records (n + k + digits of the product of the n-bit splitter by (k + 2) higher digits to the reciprocal calculated by the value (k + 3) forcibly surrounded (increased by a unit of the smaller category) senior divisions of bodies.

The adder 3 is designed for private storage. He also participates

device operation.

The dd division device (Fig. 1) contains registers 1 and 2 of the dividend and divisor, adder 3 of the quotient, first 4 and third 5 switches, subtractor

6, the high-order register 7, the splitter, the adder 8 forcibly rounding the splitter, the return calculation unit 9, the second switch 10, the second 11 and the first 12 multiplicators, the microprogram control unit 13, the data inputs 14 and synchronization 15, the input 16 of logical 1, output, 17 private, output 18 of the register of the dividend, output of the 19 most significant bits of the register of the dividend, output 20 of the register

7, the output 21 of the adder 8, the output of 22 Oza 9, the outputs 23 and 24 of the switches 4

and 5, the output 25 of register 2, the output 26 of the switch 10, the outputs 27 and 28 of the blocks 11 and 12, the output 29 of the subtractor, the outputs 30 - 36 of the block 13.,

The adder of the quotient (Fig. 2) contains the inputs 28, -28 (k + 5) high and (k-1) low bits of the product of block 12, the adder 37 and the register 38.

The microprogram control unit (Fig. 3) contains a counter 39 and a micro-instruction memory element 40.

Consider the functional purpose and implementation of the main units and units of the device for dividing.

Register 1 - (n + k + 5) -parsed, of which one bit is located to the left of the comma and n bits - to the right of the comma. In the initial state, the n-bit binary code of the divisible unsigned is stored in this register, and in the process of division, the values of the residuals are written into it. Register 2 is (n + k + +1) -discharge, with all bits located to the right of the comma. In register 2, the n-bit binary code of the divider is stored in the initial state.

when performing a division operation in the process of forming the correct

unsigned, pressed to the left page of register 2, and at the beginning of the division itself, it writes (n + k + 1) digits of the product of the n-bit divisor by (k + 2) higher digits of the inverse value calculated by the value (k 3) forcibly rounded (increased by a unit of the junior category) senior bits of the divider.

The adder 3 is designed to store the quotient. He is also involved

0

value of the quotient. After the division is completed, the quotient formed in it enters the output 17 of the private device. Before performing in the division device itself, the adder 3 is zeroed by applying a pulse from the input 15 of the device to the synchronous input of the register 38 and the enabling potential from the first output 30 of the control unit 13 to the installation input to the register 38. In the process of dividing in the adder 3 via the bus 28, is added to the value

Q low bits of the contents of register 38, which is fed to the inputs of the adder 37 with a shift to the left (E side of the high bits) to (k-1) regions, values (k + 5) high bits 2 (k + 2) - of the bit product formed at the outputs 28 of the block 12. The low (k-1) bits of this product are directly transferred to the information inputs of the lower bits of the register 38 via the bus 282. The result obtained at the outputs of the combinational 37 is written without a shift to the corresponding high bits of the register 38. In (k-1) lower bits of the register 38 with w Ina 28 record

0

five

0

five

The (k-1) lower-order bits of the product formed at the outputs 28 of multiplier 12 are output. Recording information into the register 38 is carried out: rc on a clock pulse in the presence of a resolving potential at its recording resolution input, which is connected to the second output 31 of the control unit 13.

Using the switch 4, the data inputs of the register 1 are divisible or divisible from the input 14 of these devices, when the first output of the 30 block 13 produces a logical 1 signal, or the remainder formed at the outputs 29 of the subtractor 6, when the second output 31 of the block 13, a logical 1 signal is generated.

Using the switch 5, the divider 2 or the divider from the device data input 14 is transmitted to the information inputs of the register 2 when a logical signal 1 is generated at the sixth output 35 of block 13, or a product formed at the outputs 27 of block 11 when the seventh output 36 of block 13, a logical 1 signal is generated. The first 4 and second 5 switches can be distributed on the 2I-2IL elements.

With the help of subtractor 6, subtraction is made from the values of the current balance entering the inputs of the decrementing subtractor 6 from the outputs of 18 bits of register 1 divisible, and the product entering the inputs of the subtracted subtractor 6 from outputs 27 of the multiplication unit 11. 6-combinator is a combination type with an accelerated spread of the loan.

The formation of k digits of quotient to the remainder at each step of the operation of the dividing device is performed as follows.

Let the divisible x and the divisor y be positive normalized binary fractions, that is, 1/2 X 1 and 1. However, this is true only in the first step of dividing. Later, when intermediate residues act as a dividend, the normalization of the dividend both to the left and to the right is possible. In the general case, the divisible X in the device may vary within O & k, Let x, be the value of the most significant (k + 3) digits of the dividend (remainder) y, be the value of the most significant, (k + 3) divisor bits; y, y, +2 - the value of the forcibly rounded (k + 3) divider bits; C is the reciprocal of the forcibly rounded high (k + 3) divider bits (C 1 / (y, +), - C, is the value of the highest (k + 2) bits of the return value C.

In the device, the formation of k digits of quotient Z is performed by calculating the product of Z x, C, the highest k bits of which are quotients of Z. In parallel with the formation of k digits of quotient Z, the next remainder is also calculated. To do this in the device at the preparatory stage

the division forms the product W of the divider by the value of the highest (k + 2) bits of the inverse C, (W of the C,). When the division itself is performed, the next residue x is calculated by the formula x X-W X, in parallel with the calculation of the kv numbers of the quotient Z by the formula Z x, -C ,.

Cr C - C,,, у2 У У, the younger parts, respectively, of the reciprocal, the dividend and the divisor. Absolute error (the difference between the value of the quotient, obtained by dividing the n-bit

X

the numbers Z - and the product Z X, C,) when this is concluded in the BD .- (.-

or

O - - X, - (C - C) Prove inequality

. , (C-C,),

The maximum error will be

In the case when C C «- (k-O.

With this in mind, get 2, l / (y, +

X

y, y

X,

.. 9

+

g ()

h

  X 9

+

):

To prove this inequality, it suffices to prove the following system of inequalities:

X X (

y, 2

The left part in the first inequality takes its maximum value when y O (i.e. y. Y,), x

.Hma (1ss. At moks. - 2.

Given this, the first inequalities can be rewritten as

x (y, +) - y,. x, 2.y, X

X (y, + 2- or

(2- -2-) y, + (2y, -2-) X

.2 -%, (y, +).

The last inequality holds if the following is true.

y

- (Kt-0

2

whether that

 2 - 2

five

y, (y

-and-e)

4-2

)

The second inequality of this system can be rewritten as

x, 2.

These ratios are fulfilled at all values of the divider y, enclosed within 1/2 y - 1. Register 7 is (k + 3) -digit and is intended for storing y-senior (k + 2) divider bits without sign.

The adder 8 is a combination

In block 12, the value of (k + 2) higher reciprocal digits of the reciprocal from the compulsory 1Q rounded value of the higher divisor digits formed at the outputs 22 of node 9 and fed to the first group of inputs of block 12 and the values of the most significant (k + 3) is multiplied divisible bits.

scheme. It forces the 15 higher-order incoming from the outputs of the 19 most senior ones to round the high (k + 3) bits of the divider by adding one to its younger bit, which is fed to the transfer input of the adder 8 through the input 16 of the logical 1 device (t ie in the adder 8, the value of y, +) is calculated. At the outputs 21 of the adder 8, the value of the higher bits of the divider is formed.

The rows of register 1 are divided into a group of inputs of block 12. At outputs 28 of block 12, a 2 (k + 2) -bit result is generated, which is fed to inputs 2Q of the lower bits of adder 3.

The firmware control unit 13 coordinates the operation of the nodes and units of the device when performing the division of numbers in it. Account Login

the enlarged per unit junior time-25 counter 39 is connected to the input 15 of the synchronous circuit. This eliminates the possibility of device synchronization. As

ness of obtaining at outputs 28 of the block 12 of the private with an excess.

The node 9 calculates the value of the oldest (k + 2) bits of the inverse C, from the forced rounded value of the higher bits of the divider to the inputs of node 9 from the outputs 21 of the adder 8. The outputs of the 22 nodes of node 9 form the value of the most significant (k + 2 ) the bits of the reciprocal of the value of the forcibly rounded truncated divider.

Using the switch 10, the values of the higher (k + 2) bits of the return value from the forcibly rounded value of the higher bits of the divider formed at the outputs 22 of the node 9 are transmitted to the inputs of block 11, when the output 36 of block 13 forms a logical signal

KOI 1, or the values of the most significant (k + 3) bits of the dividend coming from the outputs 19 of register 1, when a logical signal 1 is formed at the second output 31 of block 13.

In block 11, the p-bit divider stored in register 2 is multiplied and fed to the first group of inputs of block 11 from outputs 25 of register 2, and the value or higher digits of the reciprocal from the forcedly rounded value of the higher digits of the divider, or

3579466

the higher-order bits being supplied to the second group of inputs of block 11 from the outputs 26 of the switch 10. At the outputs 27 of the multiplication unit 11, a product is formed in a single-phase code,

In block 12, the value of (k + 2) higher reciprocal digits of the reciprocal from the compulsory 1Q rounded value of the higher divisor digits formed at the outputs 22 of node 9 and fed to the first group of inputs of block 12 and the values of the most significant (k + 3) is multiplied divisible bits.

arriving from the outputs of 19 older

The rows of register 1 are divided into a group of inputs of block 12. At outputs 28 of block 12, a 2 (k + 2) -bit result is formed, which is fed to the inputs of the lower bits of adder 3.

The firmware control unit 13 coordinates the operation of the nodes and units of the device when performing the division of numbers in it. Account Login

element of memory of microinstructions 40 can be used high-speed permanent memory with a capacity of (t + 3) x 7,

where m

P

 , t at the very beginning of work

GS I

The device counter 39 is set to some initial state, for example, in O (in FIG. 3, the circuit for setting the counter 39 to its initial state is not shown).

The device for dividing works as follows.

Let the n-bit binary code of the divider y already be received at the input 14 of the device data, and the counter 39 of the block 13 is set to the initial zero state. According to the contents of the counter 39, which serves as the address for accessing the memory element 40 of the microcommands of the 13th command, the microcommand 1 is read from the microcommand memory element 40, which corresponds to the control signals of the USS, U35 (Fig. 4). As a result, respectively, the fourth 33 and sixth 35 outputs of block 13 are set to logical 1 levels. Under the action of these control signals, the second switch 5 passes information to the information inputs of register 2, the divider from input 14, register 2 and register 7 are prepared to receive information, since on their inputs write permission

there are logical potentials

1. With the arrival of the first impulse on II

the input 15 of the device records the binary code of the divider y into register 2 and the binary code of the higher bits of the divider y, into register 7, and also sets the counter 39 of block 13 to state 1. Since the end of

the sync pulse ends the first cycle of the device.

In the second cycle of operation of the device, micro-command 2 is read from the micro-command memory element 40, which corresponds to the control signals of RCD, U32, UZZ and U36. As a result, respectively, the first 30, third 32, fourth 33 and seventh 36 outputs of block 13 are set to logic level 1. Under the action of these control signals, switch 4 passes informational inputs of register 1 to the dividend x from input 14, register 1 is prepared to receive information , the switch 10 passes to the inputs of the block 11 multiplying the value of the higher bits of the reciprocal C, formed at the outputs 22 of the node 9 according to the value of the 8 bits of the divider y, forcibly rounded in the adder, stored in the register 7. On the output block 11 is formed product of n-bit divider and the values of MSB inverse of C rows I (W C y),

-jg of the bits of the adder 3. In parallel with the operation of the block 12 and the adder 3, the block 11 and the subtractor 6 operate. At the outputs of the block 11, the product of the value of W at C, is stored

Under the action of the control signal from the output 36 of the block 13, the switch 5 passes to the information inputs of the register 2 this product W C, the 40 register 2 and the input to the outputs 27 of the block 11, and under the actions of the block 11 from the outputs 25 bits

register 2, to the value of the higher bits of the dividend x stored in register 1 and coming from its outputs 19 45 through the switch 10 to the inputs of block 11. As a result, the outputs x 27 of block 11 form the value x, y, C ,. The next residue x is formed at the outputs 29 of the subtractor 6 by the values of but 1 and 2, as well as the resetting of the totalizer of the divisible x, which enters the inputs of the pa 3 and installs the counter 39 of the unit 13 of the decremented subtractor 6 from the outputs to state 2. Since the end of 18 register bits 1 and the value of the action of the second pulse at the input of 15 products, - C, the incoming

to the inputs of a deductible subtractor 6 with g (- outputs 27 of block 11 (x x - x, –Y x X C,). With the arrival of the third pulse

With the control signal from output 33 of block 13, register 2 is prepared for receiving information. In addition, the adder 3 is set to zero. With the arrival of the second pulse at the device synchronization input 15, the binary codes of the dividend x are written and the product W is recorded in the corresponding synchronization registers of the device and the second cycle (and preparatory stage) of the device ends and the division itself begins, during which m (k-1 ) +1 binary digits of quotient.

at the input 15 of sync, it is the device in the register 1 is written formed at the outputs 29 of the subtractor 6 osta-.

I

th a

ten

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In the first cycle of the actual division from the memory element 40 of the micro-commands of block 13, micro-command 3 is read, to which the control signals U31 and U32 correspond, and respectively, the outputs 31 and 32 of block 13 are set to logic level 1. Under the action of these control signals, the switch 4 passes information inputs of register 1 result from outputs 29 of subtractor 6, register 1 and adder 3 are prepared for receiving information, switch 10 passes

15 to the inputs of block 11, the value of the upper bits divisible from the outputs 19 of register 1. This allows the device to perform the following calculations. According to the value of the higher bits of the dividend X (on the next clock cycles, the remainder stored in the register 1 of the dividend will act as a dividend) and the value of the higher digits of the reciprocal C, formed at the outputs of 22 nodes 9 according to the value of forcibly rounded high bits the divider is stored in register 7,

at outputs 28 of block 12, the product Z x, C ,, of the highest k

The 30 bits of which are k successive digits of the quotient Z. Formed at the outputs 28 of the block 12 2 (k + 2) -discharge product z is fed to the information inputs of the lowest jg bits of the adder 3. In parallel with the operation of the block 12 and the adder 3, the block 11 and the subtractor 6. At the outputs of the block 11, produced 40 register 2 and incoming to the inputs of block 11 from the outputs of 25 bits

maintaining the value of W at C ,,

  register 2 and incoming to the inputs of block 11 from the outputs of 25 bits

at the input 15 of sync, it is the device in the register 1 is written formed at the outputs 29 of the subtractor 6 osta-.

9

the current x, in the register 38 of the adder 3 is stored the result of the adder 37, and the counter 39 of the block 13 is set to state 3.

Similarly, the device works in other cycles. However, in each clock cycle, the value of the product formed at the outputs of block 28 is summed to the lower bits of the contents of adder 3, shifted by (k-1) bits to its higher bits, and the remainder formed at outputs 29 of the subtractor 6, enters the information inputs of the switch 4 with a shift to (k-1) bits in the direction of his senior bits.

After the last (m + 2) clock has been executed, an n-bit quotient is formed at the output 17 of the partial device. At the same time, a microcommand (t + 3) is read from the microcommand memory element 40 of block 13, which corresponds to the control of the 1st signal U34 and, accordingly, the logical output 1 is set at the fifth output 34 of block 13, signaling the end of the division operation.

13

Claims (1)

Invention Formula A device for dividing, its registers are divisible, divisor, high-order divider, two multipliers, adder private, subtractor, two switches, microprogrammed control unit, adder of forced rounding divider, inverse calculation unit, and the device data input is connected with the information input of the register of senior bits of the divider and with the first information input of the first switch, the output of which is connected to the information input of the register of the dividend, the output of the register of senior bits divides The e is connected to the information input of the forced rounding adder, the output of which is connected to the input of the reciprocal calculation unit, the output of which is connected to the first information input of the first multiplication unit, the output of the divider register is connected to the first information input of the second multiplication unit, the output of which is connected to the input of the subtracted subtractor the output of which is connected , m, 15 20 25 35794610 with the second information input of the first switch, the first and second control inputs of which are connected to the installation inputs to O and enable recording, respectively, of the quotient quotient, and the first and second outputs, respectively, of the microprogram control unit, the third and fourth outputs of which are connected to the enable inputs of writing dividend registers and the divider, respectively, whose sync circuits are connected to the sync inputs of the register of the senior bits of the divider, private adder, microprogrammed control unit and the sync input the device is renamed, the output of the private1 sum is the output of the private device, the fifth output of the firmware control block is the output of the device dividing end signaling, the logical input 1 of the device is the transfer input of the forced rounding adder, characterized in that, in order to increase the speed of the device , a third switch is inserted into it, the first and second information inputs of which are connected to the data input of the device and the output of the second multiplication unit, respectively, the sixth and seventh my outputs of the firmware control block are connected to the first and second control inputs of the third switch, respectively, the output of which is connected to the information input of the register of the divider, the input of the decremented subtractor is connected to the output of the register of the dividend, the code of the high bits of which is connected to the first information input of the second switch and the second the information input of the first multiplication block j whose output is connected to the information input of the private adder, the output of the reciprocal calculation node is connected the second information input of the second switch, the vpsod of which is connected to the second information input of the second multiplication unit, the write enable input of the high-order register of the splitter is connected to the sixth output of the microprogram control unit, the second and seventh of which are connected to the first and second control inputs of the second switch. thirty 35 40 45 50 55 JOJ132333 J5J6 F g g t t g t .2 JL / 50- / j U30.uzg, uzz, yj6 srig.z y33, y3S U31, uzg yj4 Srig.