RU1783523C - Device for dividing - Google Patents

Abstract

The invention relates to computer technology and can be used in high-speed arithmetic devices for performing a number division operation. The purpose of the invention is to increase the speed of the device by reducing the duration of the cycle of generating K digits of quotient. The device contains the first and second registers 1-2 of the remainder, register 3 divider, register 4 reciprocal, adder 5 private, adder 6 forced rounding of the divider, node 7 for calculating the reciprocal, two adders 8, 9. block 10 multiplication, switch 13, selector 14, the element 15 is NOT, the firmware control unit 19 and the newly introduced controllable partial product generator 11 and the summing unit 12. 4 ill., 1 tab.

Description

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The invention relates to computer technology and can be applied in high-speed arithmetic devices for performing the operation of division of numbers.

A device for dividing, forming in each cycle digits private

(where 2 K t;. p - bit divisibility

and a divider) and comprising two remainder registers, a divider register, a private adder, a forced rounding combiner of the divider, a reciprocal calculation unit, two adders, two multiplication units, a subtractor, an NAND element, two switches, and a firmware control unit. The main disadvantage of this device is the low speed caused by the long cycle time of the formation of the digits of the quotient and the remainder.

A device for dividing, forming in each cycle digits private

(where 2, p is the resolution of the dividend

11 - L g

and a divider) and comprising two remainder registers, a divider register, a private adder, a forced rounding combiner of the divider, an inverse computation unit, two adders, two multiplication units, a switch, a selector, a subtractor, a NOT element and a firmware control unit. Although the speed of this device is slightly higher compared to the previously considered, it is not high enough due to the relatively long cycle time, in the case when at the input of the device’s data there are simultaneously binary bits of the dividend X and the divisor Y and load into the first register of the remainder and the register of the divider at the same time. Closest to the technical nature of the invention is a device for dividing, forming in each cycle

digits of the quotient (where 2 К j that I n is the bit of the dividend and the divisor) and containing two remainder registers, the divisor register, the reciprocal register, the quotient adder, the forced rounding adder, the reciprocal calculator, the two adders, the two multiplication units, the switch , a selector, a subtracter, an element NOT, and a firmware control unit, the device data input being connected to the information input of the divider register and to the first information input of the switch, the output of which is connected to the information input of the first the remainder register, the outputs of the first and second balance registers are connected to the first and second

information inputs of the first adder, respectively, whose output is the output of the remainder of the device and connected to the input of the reducible subtractor, the inputs of which are subtracted and borrowed are connected by the outputs of the first and second groups of the first multiplication block, respectively, the first information input of the first multiplication block is connected to the output

0 registers, the outputs of the difference and the loan of the subtractors are connected to the second information input of the switch and the information input of the second register of the balance, respectively, the outputs of the higher bits of the first and

5 second registers of the remainder are connected to the first and second information inputs of the second adder, respectively, the low-order output of which is connected to the first information input of the second multiplication block, the high-order output of the second adder is connected to the input of the element NOT, the output of which is connected to the control input of the selector, information whose input is connected to

5 by the output of the second block of multiplication, the output of the selector is connected to the information input of the lower bits of the adder private and to the second information input of the first block of multiplication, the output of the senior

0 bits of the input data divider of the device is connected to the information input of the adder rounding adder, the transfer input of which is connected to the input of the logical unit of the device, the output 5 of the adder rounding adder is connected to the information input of the reciprocal calculation unit, the output of which is connected to the information input of the reciprocal register ,

0 the output of which is connected to the second information input of the second multiplication unit, the synchronization input of the device is connected to the sync inputs of the first and second registers of the remainder, divider register, inverse register, adder private and microprogram control unit, the first output of which is connected to the write enable input of the divider, inverse register, with the first control input of the switch and the zero input of the second register of the remainder and the adder private, the output of which is the output of the private of the second device, the second output of the microprogram control unit is connected to the second control input of the switch and the write enable inputs of the second remainder register and the adder private, the third output of the microprogram control unit is connected to the write enable input nepeot about the remaining register

Thus, the fourth output of the microprogram control unit is the output of the sign of the end of the division of the device. A disadvantage of the known device is its relatively low speed caused by the sufficiently long duration of the clock cycle to form digits of the quotient.

The purpose of the invention is to increase the speed of the device by reducing the duration of the clock cycle to the digits of the quotient. It is achieved by the fact that the delay time is not affected by the delay of the selector and the delay of the subtractor is eliminated.

This goal is achieved by the fact that in the device for dividing, containing two remainder registers, divider register, register of the return value, adder private, adder forced rounding of the divider, node for calculating the return value, two adders, multiplication unit, switch, selector, element NOT and unit firmware control, and the input of the device data via the device data bus is connected to the information input of the divider register and to the first information input of the switch, the output of which is connected to the information by the input of the first balance register, the outputs of the first and second balance registers are connected to the first and second information inputs of the first adder, respectively, the output of which is the output of the remainder of the device, the high-order outputs of the first and second balance registers are connected to the first and second information inputs of the second the adder, respectively, the output of the least significant bits of which is connected to the first information input of the multiplication unit, the output of the highest bit of the adder is connected to the control input of the selector, the input of which is connected to the output of the multiplication unit, the output of the selector is connected to the information input of the least significant bits of the adder private, the output of the highest bits of the divider via the data bus of the device is connected to the information input of the adder for forced rounding of the divider, the input of the logical unit of the device is connected to the transfer input of the adder for rounding a divider, the output of which is connected to the information input of the reciprocal variable calculation node, whose output is connected to the information input of the reg reciprocal isstra, whose output is connected to the second information input of the multiplication unit, the device synchronization input is connected to the sync inputs of the first and second registers of the remainder, divider register, register

reciprocal, adder private and firmware control unit, the first output of which is connected to the recording permission input of the divider register, 5 registers of the reciprocal value, with the first control input of the switch and the zero input of the second register of the remainder and adder private, the output of which is the output of the private device, the second output of the firmware control unit is connected to the second control input of the switch and the recording enable inputs of the second register of the remainder and the adder private, the third output the microprogram control unit is connected to the write enable input of the first remainder register, the fourth output of the microprogram control unit is the output of the sign of the end of the division of the device;

0, a controlled partial product shaper and a summing unit are introduced, with the divider register output connected to the first information input of the controlled partial product shaper, the output of the truncated number division unit is connected to the second information input of the controlled partial product shaper, the control input of which is connected to the output element NOT

0 the output of the first adder is connected to the first information input of the summing unit, the second information input of the summing unit is connected to the output of the controlled partial shaper

5 products, the outputs of the sums and transfers of the summing unit are connected to the second information input of the switch and the information input of the second balance register, respectively. The dividing device contains distinctive features not found in any of the known devices - the presence of a controlled shaper of partial works and a summing unit with corresponding 5 links. These features allow to increase the speed of the prototype device by reducing the duration of the formation cycle to digits of the quotient. Thus, since in the claimed technical solution

If there are distinctive features that ensure the achievement of the goal and not found in any other known similar technical solution, then it meets the criterion of significant differences.

Figure 1 is a structural diagram of a division device; Fig. 2 is a functional diagram of a controlled shaper of partial works; in Fig.Z - firmware operation of the device; on the

Fig. 4 is a functional diagram of a firmware control unit.

The device for dividing contains (Fig. 1) first 1 and second 2 registers of remainder, register 3 of the divider, register 4 of inverse value, adder 5 quotient, adder 6 of forced rounding of the divider, node 7 for calculating inverse value, first and second adders 8,9, respectively , multiplication unit 10, controllable partial product generator 11, summing unit 12, switch 13, selector 14, HE 15 element, firmware control unit 16, device data input 17, device synchronization input 18, device logical unit input 19, outputs 2 0 and 21, respectively, of the remainder and the private device, outputs 22 and 23 of registers 1 and 2, outputs 24, 25 of the upper bits of the registers 1 and 2, respectively; output 26 of register 3, output 27 of the upper bits of the divider of the input 17 of the device data, output 28 of the adder b, output 29 of the inverse computation unit 7, output 30 of register 4, output of 31 lower bits and output of 32 high bits of the adder 9, output 33 element 15, output 34 of the multiplication unit 10, output 35 of the selector 14, output 36 of the first adder 8, output 37 of the controlled shaper 11 of the partial products, the first 38 and second 39 outputs of the adder 12, output 40 of the switch 13, outputs 41-44 s first to fourth firmware control units 16, respectively. The data input 17 through the device data bus is connected to the information input of the divider register 3 and to the first information input of the switch 13, the output 40 of which is connected to the information input of the first remainder register 1, outputs 22, 23 of the first 1 and second 2 registers of the remainder are connected to the first and second information inputs of the first adder 8, respectively, the output 36 of which is the output 20 of the remainder of the device and is connected to the first input of the summing unit 12, the second input of which is connected to the output 37 of the controlled shaper 11 of the part works, the first information input of the controlled generator of partial works 11 is connected to the output 26 of the divider register 3, the output of 38 sums and the output 39 of transfers of the summing unit 12 are connected to the second information input of the switch 13 and the information input of the second register 2 of the remainder, respectively, outputs 24, 25 high-order bits of the first 1 and second 2 registers of the remainder are connected to the first and second information inputs of the second adder 9, respectively, the output of the lower 31 bits of which is connected to the first information th input unit 10 multiplies, the output 32 of the second most significant bit of the adder 9 is connected to the input of NOT element 15, the output 33 of which is connected to a control input of the selector 14 and the control input of the controllably shaper 11 partial products, yield 34 multiplying unit 10

0 is connected to the information input of the selector 14 and to the second information input of the controlled shaper 11 of the partial works, the output 35 of the selector 14 is connected to the information input

5 low-order bits of the adder 5 private, the output of the 27 high-order bits of the divider is connected through the data bus of the device to the information flow of the adder 6 forcing the divider round off, input 19

0 of the logical unit of the device is connected to the transfer input of the adder 6 for rounding the divider, the output 28 of which is connected to the input of the reciprocal calculation unit 7, the output 29 of which is connected to the information input of the reciprocal register 4, the output 30 of which is connected to the second information input of the multiplication unit 10 , sync input 18 of the device is connected to

0 sync inputs of the first 1 and second 2 registers of the remainder, register 3 of the divider, register 4 of the inverse value, adder 5 of the private and block 16 of the firmware control, the first output 41 of which is connected 5 with the write enable input of register 3 of the divider, register 4 of the inverse value, with the first control the input of the switch 13 and the input of setting to zero the second register 2 and the adder 5 private, output

0 of which is the output 21 of the private device, the second output 42 of the firmware control unit 16 is connected to the second control input of the switch 13, the write enable inputs of the second balance register 2 and the adder 5 private, the third output 43 of the firmware control unit 16 is connected to the write enable input first register 1 remainder, fourth output 44 of microprogram unit 16 A lot of control is the output of the indication of the end of division of the device. Consider the functional value and implementation of the main nodes and blocks of the proposed device for division. The first

5 register 1 remainder (n + 2) -bit. of which two bits are located to the left of the comma, and the rest are to the right of the comma. In the initial state, the n-bit binary code of the unsigned dividend is stored in the bits to the right of the comma of this register, and in

the process of dividing it from the output 38 of block 12, the values of the sums of the next residues are recorded. The second register 2 of the remainder contains (n-I) bits, of which two are located to the left of the comma, and the rest to the right of the comma. In the initial state, this register is reset, and in the process of dividing it from the output 39 of block 12, the transfer values of the next residues are recorded.

The divider register 3 is n-bit, with all the bits located to the right of the comma. In the register 3 of the divider in the initial state and during the division process, the n-bit binary code of the unsigned divider is stored.

Inverse register 4 - (k-f-2) - bit, of which one bit is located to the left of the comma, and the rest - to the right. Register 4 is intended for storing () high-order bits of the reciprocal value of a forcibly rounded truncated divider coming from the output 29 of the reciprocal-value computing unit 7. It is assumed that all the device registers are implemented on push-pull synchronous DV flip-flops. Information is recorded in the registers according to the clock pulse with the enabling potential at the V-inputs. The adder 5 private is intended for storing private. He also participates in the division operation in the process of forming the correct quotient. In the first division clock, the adder 5 of the quotient is reset by applying a clock from the synchronization input 18 of the device to its sync input and a resolving potential from the first output 41 of the microprogram control unit 16 to the enable input of setting the totalizer to zero B private. In all other clock cycles of the device in the adder 5 private accumulator value private. To this end, the k value of the quotient formed at the output 35 of the selector 14 in the current clock cycle is added to the quotient value generated at the previous clock cycles of the device and shifted by bits to the left (towards the higher bits). The information is recorded in the adder 5 by a sync pulse in the presence of an enable potential at its write enable input, which is connected to the second output 42 of the microprogram control unit 16. After the completion of the division, the quotient formed in the adder 5 is output to the private device output 21. It is assumed that the adder 5 private is implemented as in the prototype device, i.e. on the combiner and register.

The formation of k digits of the quotient in each step of the operation of the dividing device is performed by multiplying the single-row code of the truncated remainder generated on the 5th output of the 31 lower-order bits of the second adder 9 by the high-order bits of the reciprocal of the truncated divider stored in the inverse register 4 and supplied from the outputs of the ZO register 4 of the inverse value. In order to eliminate the possibility of obtaining excess private digits in the device, the value of the high-order bits of the divider coming from the output 27 of the input 17 of the device is increased by one lower-order bit in the adder 6 for the rounding of the divider. Let the dividend X and the divisor Y be normalized binary fractions, i.e. 1/2 X 1 and 1/2 Y 1, This is true only in the first measure of division. In the future, when intermediate residues act as the dividend, a violation of the normalization of the dividend is possible both to the left and to the right. In general, the divisible X in the proposed device

5 may vary within O X 2Y. “It can be shown that in order to obtain the binary digits of the quotient 14 at the output of the 35 selector, up to the unit of their least significant digit, it is sufficient to process the (k + 4) senior

0 bits of the divisible X (one bit to the left of the comma, and the rest to the right of the comma), (+3) high bits of the divisor Y (all bits are located to the right of the comma) and (k + 2) high inverse bits

5 forcibly rounded truncated divider (one bit to the left of the comma, and the rest to the right of the comma). The adder is a 6 - (and + 3) -bit combination type. In the adder 6, the divider is forced to round by adding to the value (k + 3) the senior bits of the divider, which are fed to the information input of adder 6 from output 27 through the device data bus from data input 17,

5 units in the low order, which is input to the transfer input of the adder 6 for forced rounding of the divider through the input 19 of the logical unit of the device. At the output 28 of the adder 6 forced rounding

0 divider, a +4} -bit result is formed (one bit to the left of the comma, and the rest to the right of the comma), which then goes to the information input of the inverse calculation unit 7. Knot

5 7 calculating the reciprocal value calculates the value (k + 2) of the most significant bits of the reciprocal of the forcedly rounded value (k + 3) of the highest bits of the divider received at the information input of the node for calculating the reciprocal of the output 28 of the adder 6 of the forced rounding of the divider. At the output 29 of the reciprocal-calculating unit 7, a value (k + 2) of the most significant bits of the reciprocal of the forced-rounded truncated divider is generated. Node 7 can be made in the form of a combinational circuit that implements the Stefanelli dividing method, or together with adder b into ROM according to the corresponding truth table. Using the first combiner-type adder 8, the two-row remainder code stored in the first 1 and second 2 remainder registers is converted to a single-row code. The second combiner-type adder 9 converts (kt-5) high-order bits of the two-digit remainder code stored in the remainder registers 1 and 2 into a single-digit code (two bits to the left of the comma and (k + 3) bits - to the right of the app.). At the output of the 31 least significant bits of the second adder 9, a single-row code (k + 4) of the highest bits of the remainder is generated (one bit is to the left of the comma, (k + 3) bits are to the right of the comma), and at the output 32 the leading bit of the second adder 9, the leading additional bit of the remainder is formed. In the multiplication block 10, the value of the single-row code (k + 4) of the upper bits of the remainder arriving at its first information input from the output of 31 lower bits of the second adder 9 is multiplied by the value (k + 2) of the upper bits of the reciprocal of the rounded truncated a divider arriving at its second information input from the output 30 of the inverse register 4. At the output 34 of the multiplication unit 10, a value of k digits is generated. The value of the k-bit quotient obtained at the output 35 of the selector 14 can either be equal to the value of the highest k bits of the quotient obtained by dividing n-bit numbers, or less than it by a unit of the least significant bit with weight. The multiplication unit 10 is of combinational type and can be designed by well-known methods, for example, in the form of a multilayer structure with transport propagation only in the last layer. In the controlled partial product shaper 11, partial products are generated that are obtained by multiplying the value of the n-bit divider stored in the divider register 3 in the direct code and fed to the first information input of the controlled partial product shaper from the output 26 of the divider 3 register and a k-bit quotient generated at the output 34 of the multiplication unit 10 in the direct code and fed to the second information input of the controlled partial product former.

At the same time, at the output 37 of the controlled shaper 11 of the partial products, a series of partial products are generated corresponding to multiplying the multiplier by a negative factor in the additional code without presenting the factor in the additional code. An n-bit divider is used as the multiplier. As the multiplier used to digits quotient obtained at the output of 34 block 10

5 times.

The control input of the controlled shaper 11 of the partial products receives a signal from the output 33 of the element 15.

0 Fig. 2 shows a functional diagram of a controlled shaper 11 of partial products at k-4. At the first information input of the shaper 11C output 26 of register 3 receives the value

5 of the n-bit divider, and to the second information input from the output 34 of the multiplication block 10, the value of the k-bit quotient in the form, Z2, Za, Z4. In order to form partial products, the algorithm of multiplying by two bits of the factor is applied, starting with the least significant bits, each partial product corresponding to multiplying the factor multiplied by two bits of the negative factor in the additional

5 code. At the output 37 of the controlled shaper 11 of the partial products at k-4, three partial products are formed. The controlled shaper of 11 partial works is implemented on decrypto pax 45-47 and switches 48-50.

The table explains the formation of a partial product at the output of one of the switches of the controlled driver 11, depending on the decryption of a single two-bit group of bits of the multiplier together with the highest bit of the neighboring younger group with a single or zero control signal at the output 33 of the HE 15 element . Using block 12

0 summation is the addition of the current balance generated at the output 36 of the first adder 8, with a number of partial products formed at the output 37 of the controlled shaper 11

5 partial works and shifted relative to each other in a certain way. The result of this addition is the next remainder and is obtained at the outputs of the sums 38 and transfers 39 of the summing block 12 in a two-row code. Block 12

summation is actually a multi-line to two-line code converter and can be implemented by various methods. Using the switch 13, the remainder is either transferred to the information inputs of the first register 1, either the remainder divisible via the data bus of the device from the data input 17, when a logical unit signal or the result generated at the first output 38 of block 12 is generated at the first output 41. of the microprogram control unit summation, when a logical unit signal is generated at the second output 42 of the firmware control unit 16. The switch 13 can be implemented on the elements 2Y-2OR.

Since in the apparatus according to the invention, when forming k digits of the quotient, the leading bits of the remainder obtained by running the second adder 9 to the single-row high-order code of the two-digit remainder code are used, it becomes possible to form the wrong value to the digits of the quotient. So, if the value of the leading bits of the reduced remainder obtained at the outputs 36 of the first adder 8 is equal to zero, then when generating a single-row code of the leading bits of the remainder by adding on the second adder 9 high-order bits of the two-digit remainder code, it is possible to obtain the value of the sum at the output The 31 least significant bits of the adder 9 are less than zero per unit of the least significant bit, i.e. values

1 11 1

-.- t A. but in this case the logical unit is formed at the output 32 of the high order of the second adder 9, and if the value of the high order bits of the reduced remainder received at the output 36 of the first adder 8 is not zero, the output is 32 In the high order of the second adder 9, a logical zero is generated. In order to exclude the possibility of obtaining in the first case an incorrect value for the digits of the quotient, the device provides for blocking (generating the value of digits of the quotient, equal to zero) to the digits of the quotient received at the output 34 of the multiplication unit 10 by supplying a logic zero level of s to the control input of the selector 14 output 33 of the element NOT 15, the logic zero level at its output is set if the logical unit level is set at the output 32 of the high order bit of the second adder 9. In all other cases, the value k of the digits of the quotient from the output 34 of the multiplier 10 is passed to the output 35 of the selector 14. Note that the logic zero level at the output 33 of the element is NOT 15

also blocks the operation of the shaper 11, i.e. at its output 37, zero codes are generated. The selector 14 produces the formation at the output of 35 values to digits of quotient,

5 equal to zero if a logical zero signal is present at its control input or passes to the output, 35 values of digits of the quotient of the output 34 of the multiplication unit 10, if a logical unit signal is present at its control input. It is assumed that the selector 14 is implemented as in the rototype device, i.e. contains two-input AND elements having one common input, which serves as a control input.

The microprogram control unit 16 coordinates the operation of the nodes and blocks of the device during the division operation. As in the prototype device, he

0 can be implemented on a counter 51 and a memory 52 of microcommands (Fig. 4). The counter 51 is an accumulating type and is intended for the natural addressing of microcommands. The input of the counter 51 is connected to the input

5 18 device synchronization. As a memory of 52 microcommands, a constant memory with a capacity of (M + 2) x4 can be used

, a bit, where M is the number of eigenframes during which Mx (k-1) +1 digits of the quotient are generated in the device; X is the nearest integer greater than or equal to X. At the very beginning of the operation of the device, the counter 51 is set to some initial state, for example, to zero. (Fig. 4, the chain for setting the counter 51 to its initial state is not shown). The firmware of the device is presented in Fig.Z.

0 The device for dividing works as follows.

Let n-bit binary codes of the divisor Y and the dividend X be present at the input 17 of the device data

5 codes of the fractional parts of the divider and the dividend), and the counter 51 of the microprogram control unit 16 is set to the initial zero state. Then, at the first 41 and third 43 outputs of the unit 16 of the firmware, single signals will be formed, under the influence of which the switch 13 passes the divisible X from the input 17 of the device data to the information input of the first register 1 of the remainder, to information

5 inputs of adders 6 for forced rounding of the divider the value of the highest bits of the divider is received via the device data bus from output 27 of data input 17, then the forcedly rounded value of the truncated divider from output 28 of adder b is fed to the information input of the reciprocal calculation unit 7, at the output 29 of which the value (k + 2) of the highest bits of the reciprocal of the forcedly rounded truncated divider, registers 1,3,4 are prepared for receiving information, and the second register 2 of the remainder and adder 5 of the private one are zeroing. With the arrival of the first clock pulse to the device synchronization input 18, the binary codes of the divisible X and the divisor Y are recorded in registers 1 and 3, respectively, in register 4 are the values (k + 2) of the highest bits of the inverse value of the forcibly rounded truncated divider, as well as the second register 2 remainder and adder 5 private. The counter 51 of the microprogram control unit 16 is set to state 1. After the operation of the first pulse at the device synchronization input 18, the first clock cycle (preparatory stage) ends and the division itself begins, during which M x (k-1) + is formed during M clock cycles 1 binary digits private.

In the second clock cycle (in the first of the M clock cycles of the actual division) of the operation of the device, logical unit signals are generated at the second 42 and third 43 outputs of the microprogram control unit 16. Under the influence of these control signals, the following actions are performed in the device. According to the value of the leading bits of the dividend (in the next clock cycles, the remainder stored in registers 1 and 2 of the remainder in the two-digit code will act as the dividend) and the divider at the output 34 of the multiplication unit 10, the value of the binary digits of the quotient is formed. In parallel with the operation of the second adder 9 and the multiplication unit 10, the first adder 8 operates, which converts the two-row code of the current remainder into a single-row. Based on the value of the high order of the second adder 9%, the selector 14 is finally converted to the digits of the quotient 14. If the signal at the output 32 of the second adder 9 corresponds to the level of a logical unit, then the output of the element 15 is a logical zero signal, which sets the k value of the digits of the quotient at the output of the selector 14 equal to kul and blocks the operation of the driver 11. Otherwise, the value of k digits of the quotient generated at the output 34 of the block 10 is used as the k-bit quotient Multiplication. Formed at the output 34 of the block 10 multiplication, the value of the digits of the quotient is fed to the information input of the selector 14 and to the second information

input of the controlled driver of 11 partial works. The 14-bit quotient n formed at the output of the 35 selector 14 (in the following steps, p, where i is the measure number

own division) is fed to the low-order information input of the adder B private. At the output 37 of the controlled shaper 11 of the partial products, a series of partial products are obtained that are obtained by multiplying Y x (-Z1) (in the following steps (-Z1, where e Z is the value of k digits of the quotient generated at the output 34 of the multiplication block 10, and I is the measure number of its own division) with

5, taking into account the signal input to the control input of the controlled driver 11 from the output 33 of the element NOT 15. Using the summing unit 12, the sum X + X x (-Z) is generated in a two-row code, which in

0 further serves as a remainder and is fed to the second information input of the switch 13 and to the information input of the second register 2 of the remainder with a shift by (k-1) bits to the left (towards the higher bits). Registers 5 1.2 and adder 5 private are prepared for receiving information. With the arrival of the second clock pulse at the synchronization input 18 of the device, registers 1 and 2 of the remainder are written formed at the outputs 38, 39

0 of block 12 of summation, the two-digit code of the remainder, in the lower bits of the adder 5 private are entered to the high digits of the quotient from the output 35 of the selector 14, and the counter 51 of the block 16 of the microprogram control is set to state 2. This completes the second clock cycle of the device and further M-1 similar clock cycles are performed. Note that in each of these measures the elder binary digit from to the next

0 digits of the private, formed at the output 35 of the selector 14 and fed to the information input of the lower bits of the adder 5 of the private, are summed to the low-order bit of the contents of the adder 5 of the private,

5 shifted by (k-1) bits toward its higher bits.

Claims (1)

SUMMARY OF THE INVENTION A divider device comprising two remainder registers, a divisor register, a reciprocal register, an adder private, a forced rounding-off adder, an inverse computation unit, two adders, a multiplication unit, a switch, a selector, a NOT element and a block 5 microprogram control, the input and other devices through the data bus of the device connected to the information input of the divider register and the first information input of the switch, the output of which is connected to the information input of the first register of the remainder, the outputs of the first and second registers of the remainder are connected to the first and second information inputs of the first the adder, respectively, whose output is the output of the remainder of the device, the high-order outputs of the first and second registers of the remainder are connected to the first and second in the input inputs of the second adder, respectively, whose low-order output is connected to the first information input of the multiplication unit, the high-order output of the second adder is connected to the input of the element NOT, the output of which is connected to the control input of the selector, the information input of which is connected to the output of the multiplication unit, the output of the selector is connected with the information input of the lower bits of the adder private, the output of the high bits of the divider through the data bus of the devices is connected to the information input of the adder In order to round the divider, the input of the logical unit of the device is connected to the transfer input of the adder for rounding the divider, the output of which is connected to the information input of the reciprocal calculation unit, the output of which is connected to the information input of the reciprocal register, the output of which is connected to the second information input of the multiplication unit, - the synchronization input of the device is connected to the synchro inputs of the first and second registers of the remainder, register of the divider, register of reciprocal value, adder private and Lok firmware control, a first output connected to the input enable recording the divider register, the reciprocal register, with the first control input of the switch and the installation input in O of the second register of remainder and 5 of the adder private, the output of which is the output of the private device, the second output of the firmware control unit is connected to the second control input of the switch, inputs j write permissions 0 of the second remainder register and adder private, the third output of the firmware control unit is connected to the write enable input of the first remainder register, the fourth output of the microprogram control unit is an output of the end sign of dividing the device, characterized in that, in order to increase the speed of the device, it further comprises controlled 0 shaper of partial products and a summing unit, the output of the divider register being connected to the first information input of the controlled shaper of partial works, the output of the mind block1 5. The scribe is connected to the second information input of the controlled partial shaper, the control input of which is connected to the output of the element NOT, the output of the first adder is connected to 0 the first information input of the summing unit, the second information input of the summing unit is connected to the output of the controlled shaper of partial works, the outputs of the sums and 5 transfers of the summing unit are connected to the second information input of the switch and the information input of the second balance register, respectively.  5J C 1 + 1 i / "V3 w R Ls Jo