SU1317431A1 - Dividing device - Google Patents

Abstract

The invention relates to the field of digital computing and can be used in high-performance specialized computing machines and systems. The aim of the invention is to reduce hardware costs. The device for dividing contains two cleaners 1 and 9, a divider register 2 and a dividend register 10, a private formation unit 3, a switch 4, two tabular multipliers 13, 14 and a memory unit 11. The division process consists of repetitive cycles of the same type. During the next ij-ro cycle, first, based on the analysis of the values of the higher bits of the divider and the dividend or remainder, the preliminary value of the next p-bits of the quotient is determined, after which the difference sign is analyzed and the quotient is corrected. 3 il. S (L with 4 CO cfjueA

Description

113

The invention relates to digital computing, is intended to divide the numbers represented in the binary number system, and can be used as an operation unit in high-performance specialized computers and systems.

The aim of the invention is to reduce hardware costs.

FIG. 1 shows a functional diagram of a device for dividing; in fig. 2 illustrates an exemplary functional diagram of a private site; in fig. 3 - timing diagram of the generation of clock signals.

The device for dividing (Fig. 1) contains the second subtractor 1, the register 2 of the divider, the node 3 of formation of the private, the switch 4, which includes two groups of 5-6 elements AND and group 7 of elements OR, the third synchronous input 8 , the first subtractor 9, the register 10 of the dividend, the memory block 11, the first synchronization input 12, table multipliers 13 and 14, the second synchronization input 15 Node 3 is designed to form - and store a private one, which includes a p-bit subtraction counter 16 and ( AP) -discharge register 17. The outputs p of the discharge bits of the counter 16 are connected to the inputs of the p bits Register 17. Node 3 has a shift resolution input 18, reading 1st input 19, information input 20, and recording permission input 21.

Block 11. Has two address inputs of size: p + 2 and p + 1, respectively, which determine the address space size. In block 11, p-bit codes are stored, which are used as preliminary values of the next p bits.

Table multipliers 13 and 14 are intended for storage of (n + p) -disk codes, multiple divisors of 105 and have p-bit address inputs.

Switch 4 implements the function

aA (B) (,) (a4bt) ....

 J.

The device for dividing numbers works as follows.

In the initial state in the lower-order bits of register 10 there is the dividend X, in register 2 the divider Y, in block 13, starting with the zero address, the numbers Y, 2Y, charger are written ... (2-2) Y (2-1) Y, and in block 14, starting with 12

left address, recorded numbers 0, Y, 2Y, ..., (2-2) Y, (2-1) Y, (2-1) Y.

In each division cycle, inputs 12, 15, and 8 receive signals in series, as shown in FIG. 3. The number of division cycles is -,

where and is the operand size.

With the arrival of the signal at input 12, a shift to the left by p bits at nodes 10 and 3 is accomplished. As a result, the next dividend appears in register 10. After this, the values of p + 1 most significant bits (starting with the second most significant bit, excluding the first) of register 2 and p + 2 most significant bits of register 10 from block 11 are addressed, the inputs of multipliers 13 and 14 are given Z, Zj, ..., Zp is a preliminary value of the next bits of the quotient.

The signal at input 15 receives this code in the lower p bits of node 3, from multipliers 13

R

and 14 select the number 2 Zp2 -Y

eh

and (Zo 2 -1) Y, respectively. On

.e subtractors 9 and 1 calculate the differences of the contents of the register 10 and the numbers

PP

Z Y and (Z Z 2) Y respectively 1

pn

venno. If the sign bit of the subtractor 9 is equal to -1. - (the difference is negative), the signal -1 is sent to the subtracting input of node 3, as a result of which the content of node 3 decreases by one.

The signal at input 9, depending on the sign of the difference obtained on the emitter 9, records the positive remainder Q (-1 to the lower n bits of the register 10 of the lower bits of the subtractors 9 or 1. After this cycle, the division is repeated.

Claims (1)

Invention Formula A device for dividing, containing registers of a dividend and a divider, a private node, two subtractors, a memory unit, two tabular multipliers, and a switch, with the output of the register divisible connected to the inputs of the decremented first and second subtractors, the inputs of which are subtracted are connected to the outputs of the first and second tabular multipliers, respectively, the address inputs of which are connected to the output of the memory unit, the output of the sign bit of the first subtractor is connected to the control input of the switch, the first and second information inputs of which are connected with the outputs of the first and second calibrators, respectively, the switch output is connected to the information input of the register of the dividend, characterized in that, in order to reduce hardware costs, the speed (p + 2) high-order bits The register of the delimited (where, 3 ... n-3, n is the width of the operands) is connected to the first address input of the memory block, the second T qi / gmg dezhni Compiler N.Markelova Editor A.Makovska Tehred A.Kravchuk Proofreader. M.Sharoshi Order 2424/43 Circulation 672. Subscription VNISHU USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 -Production and printing company, Uzhgorod, Projecto st., 4 the address input of which is connected to the output (p + 1) of the upper bits of the divider register, the output of the memory block is connected to the information input of the private node, the subtractive input of which is connected to the output of the sign bit of the first reader, the first synchronous input of the device - A divider divisor and a private node formation, the second synchronized input of the device is connected to the read resolution inputs of the first and second table multipliers, with the resolution 15 inputs of the subtraction of the first and second subtractors, and swing assembly write enable formation quotient register write enable input of the dividend is the third clock terminal device. fpi / yy 18