SU1417007A1 - Squaring device - Google Patents

Description

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The invention relates to computing technology and can be used in the design and development of J: e specialized, and universal digital computers. j The purpose of the invention is to reduce ap (contractual: atrat.

i The drawing shows the functional diagram of the device. : The device for squaring contains the register of 1 argument, the register of result 2, the combination counter 3, the combination adder {A, AND 5, the inputs 6-8 and the outputs 9 of the device.

The argument register is the usual L1 shift register. Cig; shift shells of the in. I register come from | input 6 of the device. From entry 7, the post: number, erected in the vadrat with the old bits ahead. : The outputs of the most significant bits of the register 1: are connected to the first group of inputs of the combinational adder 4. The output of the lower bit of register 1 is connected to the input of the lower bit of register 2. The input of the second bit of register 2 is constantly zeroed signal. The inputs of the remaining 2p-2 bits of the register 2 are connected to the outputs of the adder 4 and the combination counter 3. The outputs 2p-2 of the bits of the register 2 are connected to the inputs of the adder and the combination counter. The transfer output from the adder 4 is connected to the counting input of the counter 3, Register 2 is a conventional sum register that can perform the L2 shift operation. When a shift signal is received from input 6, the register is shifted 2 bits to the left. The recording of the sum in register 2 is controlled by an AND 5 element on a signal coming from the input 8 of the device. The formed square of the number is read from the outputs 9 of register 2.

The scheme works as follows. In the first loop, input 7 is supplied to the high bit of the argument X. At the same time, a shift signal is inputted to input 6 and X is written to the first register bit 1. In the next clock cycle, a write signal is applied to input 8 and digit X is written to register 2 as the first partial square.

In the second cycle, the second bit of the argument Xj is fed to input 7. By sig7007 .2

Shift bit X is transferred to the second bit of register 1, and bit X is written to the first. At the same time, in register 2 the first partial square is shifted by two bits. In the next cycle, a write signal is applied to input 8. If X Oj this signal does not pass to the control input

Q is a record of register 2 and the content of the latter does not change. If X 1, in register 2, the bit and sum from the adder 4 and the combination counter 3 are written to the register

5 2, i.e. in register 2 is formed

the sum of the first partial square and the second partial square shifted by 2 bits.

Q Similarly, p-2 is still performed.

cycle. The search square is read.

from the outputs of the register 2.. Example. Let p-6,, 111011,

X 0.110110011001. 5 The device will work in

table view.

Claims (1)

Invention Formula A device for squaring, containing the argument register, the result register, the combinational adder, the AND element, and the information input and the shift register input of the argument are respectively the input of the argument setting and the input of the shift of the device, in order to reduce hardware cost, it contains a combinational counter, and the output of the low bit of the register of the argument is connected to the input of the low bit of the result register and the first input of the element K, the second input of which is connected to the sync the device’s output and the output to the resolution enable input of the result register; the second bit input is connected to the logical zero bus input of the device; the higher bits of the argument register are connected to the first group of inputs of the combinational adder; the outputs and the second group of inputs are connected respectively with inputs and outputs, starting from the third to (n + 1) -th bit, result register (where n is the width of the argument), the outputs and inputs of bits from the first to (n-1) -th combination counter with entrances and exits, na5 0 five 31417007, the rank of the (n + 2) -th bit, the register of the input of the register of the result of the result subsystem, the transfer of the combination key to the input of the device shift, the accumulator adder are connected to the counter; the outputs of the result register are the input of the combination counter,; device outputs